From 095fb43fb49788de7d698c4fcfaaa0a4229c8506 Mon Sep 17 00:00:00 2001
From: Maulik Shah <mkshah@qti.qualcomm.com>
Date: Tue, 25 Aug 2020 12:04:22 +0530
Subject: [PATCH] ARM: dts: msm: Add cmd_db, RSC and PDC devices for sm6150

This change adds three items.

	1. cmd_db reserved memory area
	2. apps and display RSC devices
	3. PDC irqchip device

cmd_db and RSC devices are required for communication with AOSS.
PDC irqchip is required to wakeup device from deep sleep low power
modes.

Change-Id: Idae1cf07113978e66300954809e624d7289c7717
---
 qcom/sm6150-pinctrl.dtsi | 11 ++++++++++-
 qcom/sm6150.dtsi         | 29 +++++++++++++++++++++++++++++
 2 files changed, 39 insertions(+), 1 deletion(-)

diff --git a/qcom/sm6150-pinctrl.dtsi b/qcom/sm6150-pinctrl.dtsi
index 71308852030e..bfebee7214a0 100644
--- a/qcom/sm6150-pinctrl.dtsi
+++ b/qcom/sm6150-pinctrl.dtsi
@@ -3,11 +3,20 @@
 		compatible = "qcom,sm6150-pinctrl";
 		reg = <0x03000000 0xdc2000>, <0x17c000f0 0x50>;
 		reg-names = "pinctrl", "spi_cfg";
-		interrupts = <0 208 0>;
+		interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
 		gpio-controller;
 		#gpio-cells = <2>;
 		interrupt-controller;
 		#interrupt-cells = <2>;
+		wakeup-parent = <&pdc>;
 
 		ufs_dev_reset_assert: ufs_dev_reset_assert {
 			config {
diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi
index 7cfff14ca003..523b6b482d69 100644
--- a/qcom/sm6150.dtsi
+++ b/qcom/sm6150.dtsi
@@ -362,6 +362,12 @@
 			reg = <0x0 0x85e00000 0x0 0x140000>;
 		};
 
+		aop_cmd_db: memory@85f20000 {
+			compatible = "qcom,cmd-db";
+			reg = <0x0 0x85f20000 0x0 0x20000>;
+			no-map;
+		};
+
 		sec_apps_mem: sec_apps_region@85fff000 {
 			no-map;
 			reg = <0x0 0x85fff000 0x0 0x1000>;
@@ -592,6 +598,15 @@
 		};
 	};
 
+	pdc: interrupt-controller@b220000 {
+		compatible = "qcom,sm6150-pdc";
+		reg = <0xb220000 0x30000>, <0x17c000f0 0x60>;
+		qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&intc>;
+		interrupt-controller;
+	};
+
 	qcom,msm-imem@146aa000 {
 		compatible = "qcom,msm-imem";
 		reg = <0x146aa000 0x1000>;
@@ -677,6 +692,20 @@
 			compatible = "qcom,system-pm";
 		};
 	};
+
+	disp_rsc: rsc@af20000 {
+		label = "disp_rsc";
+		compatible = "qcom,rpmh-rsc";
+		reg = <0xaf20000 0x10000>;
+		reg-names = "drv-0";
+		interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,tcs-offset = <0x1c00>;
+		qcom,drv-id = <0>;
+		qcom,tcs-config = <SLEEP_TCS   1>,
+				  <WAKE_TCS    1>,
+				  <ACTIVE_TCS  2>,
+				  <CONTROL_TCS 0>;
+	};
 };
 
 #include "sm6150-qupv3.dtsi"