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ARM: dts: msm: Enable 747MHz GPU Fmax for Shima

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Enable 747MHz GPU Fmax as per SKU definitions.

Change-Id: I2f38e8399ddda1aa30d5e1ef5fc56ffffc8d5b2b
This commit is contained in:
Deepak Kumar 2020-09-11 13:05:35 +05:30
commit 09a68ad8b2
1 changed files with 48 additions and 20 deletions
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68
qcom/shima-gpu.dtsi
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@ -143,10 +143,24 @@
#size-cells = <0>;
qcom,speed-bin = <0>;
qcom,initial-pwrlevel = <4>;
qcom,initial-pwrlevel = <5>;
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <747000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
qcom,bus-freq-ddr7 = <11>;
qcom,bus-min-ddr7 = <11>;
qcom,bus-max-ddr7 = <11>;
qcom,bus-freq-ddr8 = <11>;
qcom,bus-min-ddr8 = <10>;
qcom,bus-max-ddr8 = <11>;
};
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <676000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
@ -154,13 +168,13 @@
qcom,bus-min-ddr7 = <10>;
qcom,bus-max-ddr7 = <11>;
qcom,bus-freq-ddr8 = <11>;
qcom,bus-freq-ddr8 = <10>;
qcom,bus-min-ddr8 = <9>;
qcom,bus-max-ddr8 = <11>;
};
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <608000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
@ -173,8 +187,8 @@
qcom,bus-max-ddr8 = <11>;
};
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <540000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
@ -187,8 +201,8 @@
qcom,bus-max-ddr8 = <10>;
};
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <443000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
@ -201,8 +215,8 @@
qcom,bus-max-ddr8 = <9>;
};
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <285000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
@ -307,10 +321,24 @@
#size-cells = <0>;
qcom,speed-bin = <158>;
qcom,initial-pwrlevel = <4>;
qcom,initial-pwrlevel = <5>;
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <747000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
qcom,bus-freq-ddr7 = <11>;
qcom,bus-min-ddr7 = <11>;
qcom,bus-max-ddr7 = <11>;
qcom,bus-freq-ddr8 = <11>;
qcom,bus-min-ddr8 = <10>;
qcom,bus-max-ddr8 = <11>;
};
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <676000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
@ -318,13 +346,13 @@
qcom,bus-min-ddr7 = <10>;
qcom,bus-max-ddr7 = <11>;
qcom,bus-freq-ddr8 = <11>;
qcom,bus-freq-ddr8 = <10>;
qcom,bus-min-ddr8 = <9>;
qcom,bus-max-ddr8 = <11>;
};
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <608000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
@ -337,8 +365,8 @@
qcom,bus-max-ddr8 = <11>;
};
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <540000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
@ -351,8 +379,8 @@
qcom,bus-max-ddr8 = <10>;
};
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <443000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
@ -365,8 +393,8 @@
qcom,bus-max-ddr8 = <9>;
};
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <285000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;