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clk: qcom: gpucc-lahaina: Fix gpu_cc_cx_gmu_clk stuck off warning
Earlier gpu_cc_cx_gmu_clk, gpu_cc_hub_cx_int_clk are kept always on, due to SMMU hw voting missed tying these 2 clocks. Update gpu_cc_cx_gmu_clk flag to CLK_DONT_HOLD_STATE as this clk is used with aon ops and should not be warned by clk framework as clk hold off state during the kernel boot. Change-Id: I8fcfffa8c7e4dc6e9ca66bb82cda75c855b35b74 Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org>
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parent
b318939c3f
commit
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1 changed files with 3 additions and 3 deletions
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@ -332,7 +332,7 @@ static struct clk_branch gpu_cc_cx_gmu_clk = {
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.hw = &gpu_cc_gmu_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.flags = CLK_SET_RATE_PARENT | CLK_DONT_HOLD_STATE,
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.ops = &clk_branch2_aon_ops,
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},
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},
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@ -507,7 +507,7 @@ static struct clk_branch gpu_cc_hub_aon_clk = {
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static struct clk_branch gpu_cc_hub_cx_int_clk = {
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.halt_reg = 0x1204,
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.halt_check = BRANCH_HALT_SKIP,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x1204,
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.enable_mask = BIT(0),
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@ -517,7 +517,7 @@ static struct clk_branch gpu_cc_hub_cx_int_clk = {
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.hw = &gpu_cc_hub_cx_int_div_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.flags = CLK_SET_RATE_PARENT | CLK_DONT_HOLD_STATE,
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.ops = &clk_branch2_aon_ops,
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},
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},
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