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i40e: add mask to apply valid bits for itr_idx
[ Upstream commit eac04428abe9f9cb203ffae4600791ea1d24eb18 ]
The ITR index (itr_idx) is only 2 bits wide. When constructing the
register value for QINT_RQCTL, all fields are ORed together. Without
masking, higher bits from itr_idx may overwrite adjacent fields in the
register.
Apply I40E_QINT_RQCTL_ITR_INDX_MASK to ensure only the intended bits are
set.
Fixes: 5c3c48ac6b ("i40e: implement virtual device interface")
Cc: stable@vger.kernel.org
Signed-off-by: Lukasz Czapnik <lukasz.czapnik@intel.com>
Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com>
Signed-off-by: Przemek Kitszel <przemyslaw.kitszel@intel.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Tested-by: Rafal Romanowski <rafal.romanowski@intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
[ Added missing linux/bitfield.h header for FIELD_PREP macro ]
Signed-off-by: Sasha Levin <sashal@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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1 changed files with 2 additions and 1 deletions
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@ -1,6 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright(c) 2013 - 2018 Intel Corporation. */
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#include <linux/bitfield.h>
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#include "i40e.h"
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/*********************notification routines***********************/
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@ -393,7 +394,7 @@ static void i40e_config_irq_link_list(struct i40e_vf *vf, u16 vsi_id,
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(qtype << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
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(pf_queue_id << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
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BIT(I40E_QINT_RQCTL_CAUSE_ENA_SHIFT) |
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(itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT);
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FIELD_PREP(I40E_QINT_RQCTL_ITR_INDX_MASK, itr_idx);
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wr32(hw, reg_idx, reg);
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}
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