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Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (62 commits) powerpc/85xx: Fix signedness bug in cache-sram powerpc/fsl: 85xx: document cache sram bindings powerpc/fsl: define binding for fsl mpic interrupt controllers powerpc/fsl_msi: Handle msi-available-ranges better drivers/serial/ucc_uart.c: Add of_node_put to avoid memory leak powerpc/85xx: Fix SPE float to integer conversion failure powerpc/85xx: Update sata controller compatible for p1022ds board ATA: Add FSL sata v2 controller support powerpc/mpc8xxx_gpio: simplify searching for 'fsl, qoriq-gpio' compatiable powerpc/8xx: remove obsolete mgsuvd board powerpc/82xx: rename and update mgcoge board support powerpc/83xx: rename and update kmeter1 powerpc/85xx: Workaroudn e500 CPU erratum A005 powerpc/fsl_pci: Add support for FSL PCIe controllers v2.x powerpc/85xx: Fix writing to spin table 'cpu-release-addr' on ppc64e powerpc/pseries: Disable MSI using new interface if possible powerpc: Enable GENERIC_HARDIRQS_NO_DEPRECATED. powerpc: core irq_data conversion. powerpc: sysdev/xilinx_intc irq_data conversion. powerpc: sysdev/uic irq_data conversion. ... Fix up conflicts in arch/powerpc/sysdev/fsl_msi.c (due to getting rid of of_platform_driver in arch/powerpc)
This commit is contained in:
Linus Torvalds
commit
0a95d92c00
101 changed files with 2437 additions and 1394 deletions
20
Documentation/devicetree/bindings/powerpc/fsl/cache_sram.txt
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20
Documentation/devicetree/bindings/powerpc/fsl/cache_sram.txt
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@ -0,0 +1,20 @@
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* Freescale PQ3 and QorIQ based Cache SRAM
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Freescale's mpc85xx and some QorIQ platforms provide an
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option of configuring a part of (or full) cache memory
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as SRAM. This cache SRAM representation in the device
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tree should be done as under:-
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Required properties:
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- compatible : should be "fsl,p2020-cache-sram"
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- fsl,cache-sram-ctlr-handle : points to the L2 controller
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- reg : offset and length of the cache-sram.
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Example:
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cache-sram@fff00000 {
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fsl,cache-sram-ctlr-handle = <&L2>;
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reg = <0 0xfff00000 0 0x10000>;
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compatible = "fsl,p2020-cache-sram";
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};
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@ -1,42 +1,211 @@
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* OpenPIC and its interrupt numbers on Freescale's e500/e600 cores
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=====================================================================
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Freescale MPIC Interrupt Controller Node
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Copyright (C) 2010,2011 Freescale Semiconductor Inc.
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=====================================================================
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The OpenPIC specification does not specify which interrupt source has to
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become which interrupt number. This is up to the software implementation
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of the interrupt controller. The only requirement is that every
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interrupt source has to have an unique interrupt number / vector number.
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To accomplish this the current implementation assigns the number zero to
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the first source, the number one to the second source and so on until
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all interrupt sources have their unique number.
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Usually the assigned vector number equals the interrupt number mentioned
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in the documentation for a given core / CPU. This is however not true
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for the e500 cores (MPC85XX CPUs) where the documentation distinguishes
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between internal and external interrupt sources and starts counting at
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zero for both of them.
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The Freescale MPIC interrupt controller is found on all PowerQUICC
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and QorIQ processors and is compatible with the Open PIC. The
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notable difference from Open PIC binding is the addition of 2
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additional cells in the interrupt specifier defining interrupt type
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information.
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So what to write for external interrupt source X or internal interrupt
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source Y into the device tree? Here is an example:
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PROPERTIES
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The memory map for the interrupt controller in the MPC8544[0] shows,
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that the first interrupt source starts at 0x5_0000 (PIC Register Address
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Map-Interrupt Source Configuration Registers). This source becomes the
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number zero therefore:
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External interrupt 0 = interrupt number 0
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External interrupt 1 = interrupt number 1
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External interrupt 2 = interrupt number 2
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...
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Every interrupt number allocates 0x20 bytes register space. So to get
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its number it is sufficient to shift the lower 16bits to right by five.
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So for the external interrupt 10 we have:
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0x0140 >> 5 = 10
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- compatible
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Usage: required
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Value type: <string>
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Definition: Shall include "fsl,mpic". Freescale MPIC
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controllers compatible with this binding have Block
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Revision Registers BRR1 and BRR2 at offset 0x0 and
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0x10 in the MPIC.
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After the external sources, the internal sources follow. The in core I2C
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controller on the MPC8544 for instance has the internal source number
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27. Oo obtain its interrupt number we take the lower 16bits of its memory
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address (0x5_0560) and shift it right:
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0x0560 >> 5 = 43
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- reg
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Usage: required
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Value type: <prop-encoded-array>
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Definition: A standard property. Specifies the physical
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offset and length of the device's registers within the
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CCSR address space.
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Therefore the I2C device node for the MPC8544 CPU has to have the
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interrupt number 43 specified in the device tree.
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- interrupt-controller
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Usage: required
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Value type: <empty>
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Definition: Specifies that this node is an interrupt
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controller
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[0] MPC8544E PowerQUICCTM III, Integrated Host Processor Family Reference Manual
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MPC8544ERM Rev. 1 10/2007
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- #interrupt-cells
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Usage: required
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Value type: <u32>
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Definition: Shall be 2 or 4. A value of 2 means that interrupt
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specifiers do not contain the interrupt-type or type-specific
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information cells.
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- #address-cells
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Usage: required
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Value type: <u32>
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Definition: Shall be 0.
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- pic-no-reset
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Usage: optional
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Value type: <empty>
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Definition: The presence of this property specifies that the
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MPIC must not be reset by the client program, and that
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the boot program has initialized all interrupt source
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configuration registers to a sane state-- masked or
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directed at other cores. This ensures that the client
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program will not receive interrupts for sources not belonging
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to the client. The presence of this property also mandates
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that any initialization related to interrupt sources shall
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be limited to sources explicitly referenced in the device tree.
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INTERRUPT SPECIFIER DEFINITION
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Interrupt specifiers consists of 4 cells encoded as
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follows:
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<1st-cell> interrupt-number
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Identifies the interrupt source. The meaning
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depends on the type of interrupt.
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Note: If the interrupt-type cell is undefined
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(i.e. #interrupt-cells = 2), this cell
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should be interpreted the same as for
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interrupt-type 0-- i.e. an external or
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normal SoC device interrupt.
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<2nd-cell> level-sense information, encoded as follows:
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0 = low-to-high edge triggered
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1 = active low level-sensitive
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2 = active high level-sensitive
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3 = high-to-low edge triggered
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<3rd-cell> interrupt-type
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The following types are supported:
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0 = external or normal SoC device interrupt
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The interrupt-number cell contains
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the SoC device interrupt number. The
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type-specific cell is undefined. The
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interrupt-number is derived from the
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MPIC a block of registers referred to as
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the "Interrupt Source Configuration Registers".
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Each source has 32-bytes of registers
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(vector/priority and destination) in this
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region. So interrupt 0 is at offset 0x0,
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interrupt 1 is at offset 0x20, and so on.
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1 = error interrupt
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The interrupt-number cell contains
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the SoC device interrupt number for
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the error interrupt. The type-specific
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cell identifies the specific error
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interrupt number.
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2 = MPIC inter-processor interrupt (IPI)
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The interrupt-number cell identifies
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the MPIC IPI number. The type-specific
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cell is undefined.
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3 = MPIC timer interrupt
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The interrupt-number cell identifies
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the MPIC timer number. The type-specific
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cell is undefined.
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<4th-cell> type-specific information
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The type-specific cell is encoded as follows:
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- For interrupt-type 1 (error interrupt),
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the type-specific cell contains the
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bit number of the error interrupt in the
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Error Interrupt Summary Register.
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EXAMPLE 1
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/*
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* mpic interrupt controller with 4 cells per specifier
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*/
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mpic: pic@40000 {
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compatible = "fsl,mpic";
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interrupt-controller;
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#interrupt-cells = <4>;
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#address-cells = <0>;
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reg = <0x40000 0x40000>;
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};
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EXAMPLE 2
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/*
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* The MPC8544 I2C controller node has an internal
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* interrupt number of 27. As per the reference manual
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* this corresponds to interrupt source configuration
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* registers at 0x5_0560.
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*
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* The interrupt source configuration registers begin
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* at 0x5_0000.
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*
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* To compute the interrupt specifier interrupt number
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*
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* 0x560 >> 5 = 43
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*
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* The interrupt source configuration registers begin
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* at 0x5_0000, and so the i2c vector/priority registers
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* are at 0x5_0560.
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*/
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i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <0x3000 0x100>;
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interrupts = <43 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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EXAMPLE 3
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/*
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* Definition of a node defining the 4
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* MPIC IPI interrupts. Note the interrupt
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* type of 2.
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*/
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ipi@410a0 {
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compatible = "fsl,mpic-ipi";
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reg = <0x40040 0x10>;
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interrupts = <0 0 2 0
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1 0 2 0
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2 0 2 0
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3 0 2 0>;
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};
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EXAMPLE 4
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/*
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* Definition of a node defining the MPIC
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* global timers. Note the interrupt
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* type of 3.
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*/
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timer0: timer@41100 {
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compatible = "fsl,mpic-global-timer";
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reg = <0x41100 0x100>;
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interrupts = <0 0 3 0
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1 0 3 0
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2 0 3 0
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3 0 3 0>;
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};
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EXAMPLE 5
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/*
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* Definition of an error interrupt (interupt type 1).
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* SoC interrupt number is 16 and the specific error
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* interrupt bit in the error interrupt summary register
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* is 23.
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*/
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memory-controller@8000 {
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compatible = "fsl,p4080-memory-controller";
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reg = <0x8000 0x1000>;
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interrupts = <16 2 1 23>;
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};
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@ -5,14 +5,21 @@ Required properties:
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first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
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etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" depending on
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the parent type.
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- reg : should contain the address and the length of the shared message
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interrupt register set.
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- msi-available-ranges: use <start count> style section to define which
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msi interrupt can be used in the 256 msi interrupts. This property is
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optional, without this, all the 256 MSI interrupts can be used.
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Each available range must begin and end on a multiple of 32 (i.e.
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no splitting an individual MSI register or the associated PIC interrupt).
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- interrupts : each one of the interrupts here is one entry per 32 MSIs,
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and routed to the host interrupt controller. the interrupts should
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be set as edge sensitive.
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be set as edge sensitive. If msi-available-ranges is present, only
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the interrupts that correspond to available ranges shall be present.
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- interrupt-parent: the phandle for the interrupt controller
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that services interrupts for this device. for 83xx cpu, the interrupts
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are routed to IPIC, and for 85xx/86xx cpu the interrupts are routed
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