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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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Allwinner DT64 changes for 5.1
A few small improvements for the A64 this cycle:
- ARM PMU added
- Allwinner ARM architected timer workaround enabled
This works around timer value wrapping found in the Allwinner
implementation of the ARM architected timer.
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Merge tag 'sunxi-dt64-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt
Allwinner DT64 changes for 5.1
A few small improvements for the A64 this cycle:
- ARM PMU added
- Allwinner ARM architected timer workaround enabled
This works around timer value wrapping found in the Allwinner
implementation of the ARM architected timer.
* tag 'sunxi-dt64-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
arm64: dts: allwinner: a64: Enable A64 timer workaround
arm64: dts: allwinner: a64: Fix a typo
arm64: dts: allwinner: a64: Add PMU node
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
0b03e47d52
2 changed files with 11 additions and 1 deletions
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@ -239,7 +239,7 @@
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};
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/*
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* The A64 chip cannot work without this regulator off, although
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* The A64 chip cannot work with this regulator off, although
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* it seems to be only driving the AR100 core.
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* Maybe we don't still know well about CPUs domain.
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*/
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@ -142,6 +142,15 @@
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clock-output-names = "ext-osc32k";
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};
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pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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@ -191,6 +200,7 @@
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timer {
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compatible = "arm,armv8-timer";
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allwinner,erratum-unknown1;
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14
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