From f999c2e907a13d4c2790e7107fe4b621e1df89a1 Mon Sep 17 00:00:00 2001 From: Ke Du Date: Mon, 22 Nov 2021 11:34:00 +0530 Subject: [PATCH 1/9] ARM: dts: msm: add sde dts of display for QCS610 Add sde dtsi of display for QCS610. Change-Id: I246107b16eb4d29a557deef76792d464c8c7fc32 --- display/sm6150-sde-display.dtsi | 185 +++++++++++ display/sm6150-sde.dtsi | 540 ++++++++++++++++++++++++++++++++ 2 files changed, 725 insertions(+) create mode 100644 display/sm6150-sde-display.dtsi create mode 100644 display/sm6150-sde.dtsi diff --git a/display/sm6150-sde-display.dtsi b/display/sm6150-sde-display.dtsi new file mode 100644 index 000000000000..d15671815cfe --- /dev/null +++ b/display/sm6150-sde-display.dtsi @@ -0,0 +1,185 @@ +#include +#include "dsi-panel-ili988c-dual-video.dtsi" +#include "dsi-panel-ext-bridge-1080p.dtsi" + +&soc { + dsi_panel_pwr_supply: dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + dsi_panel_pwr_supply_labibb_amoled: dsi_panel_pwr_supply_labibb_amoled { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdda-3p3"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3000000>; + qcom,supply-enable-load = <13200>; + qcom,supply-disable-load = <80>; + }; + }; + + sde_dsi: qcom,dsi-display { + compatible = "qcom,dsi-display"; + label = "primary"; + + qcom,dsi-ctrl = <&mdss_dsi0>; + qcom,dsi-phy = <&mdss_dsi_phy0>; + + clocks = <&mdss_dsi_phy0 BYTE0_MUX_CLK>, + <&mdss_dsi_phy0 PIX0_MUX_CLK>, + <&mdss_dsi_phy0 BYTE0_SRC_CLK>, + <&mdss_dsi_phy0 PIX0_SRC_CLK>, + <&mdss_dsi_phy0 SHADOW_BYTE0_SRC_CLK>, + <&mdss_dsi_phy0 SHADOW_PIX0_SRC_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi_active &sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; + + qcom,platform-te-gpio = <&tlmm 90 0>; + qcom,panel-te-source = <0>; + + vddio-supply = <&pm6150_l13>; + vdda-3p3-supply = <&pm6150_l18>; + lab-supply = <&lcdb_ldo_vreg>; + ibb-supply = <&lcdb_ncp_vreg>; + + qcom,dsi-default-panel = <&dsi_ili9881c_720p_video>; + qcom,mdp = <&mdss_mdp>; + }; + + sde_wb: qcom,wb-display@0 { + compatible = "qcom,wb-display"; + cell-index = <0>; + label = "wb_display"; + }; +}; + +&sde_dp { + qcom,dp-usbpd-detection = <&pm6150_pdphy>; + hpd-pwr-supply = <&pm6150_l17>; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <975000>; + qcom,supply-enable-load = <36000>; + qcom,supply-disable-load = <0>; + }; + qcom,phy-supply-entry@1 { + reg = <1>; + qcom,supply-name = "hpd-pwr"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3230000>; + qcom,supply-enable-load = <30000>; + qcom,supply-disable-load = <0>; + }; + }; +}; + +&mdss_mdp { + connectors = <&smmu_sde_unsec &smmu_sde_sec &sde_rscc &sde_wb &sde_dp &sde_dsi>; +}; + +&dsi_ili9881c_720p_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0a>; + qcom,mdss-dsi-t-clk-pre = <0x21>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-timings = + [1F 1C 04 06 03 02 0a + 1F 1C 04 06 03 02 0a + 1F 1C 04 06 03 02 0a + 1F 1C 04 06 03 02 0a + 1F 10 04 06 03 02 0a]; + + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_ext_bridge_1080p { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = + [24 1f 08 09 05 03 04 a0 + 24 1f 08 09 05 03 04 a0 + 24 1f 08 09 05 03 04 a0 + 24 1f 08 09 05 03 04 a0 + 24 1b 08 09 05 03 04 a0]; + + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/display/sm6150-sde.dtsi b/display/sm6150-sde.dtsi new file mode 100644 index 000000000000..ddb27cb9fbcc --- /dev/null +++ b/display/sm6150-sde.dtsi @@ -0,0 +1,540 @@ +#include + +&soc { + mdss_mdp: qcom,mdss_mdp@ae00000 { + compatible = "qcom,sde-kms"; + reg = <0x0ae00000 0x84208>, + <0x0aeb0000 0x2008>, + <0x0aeac000 0x214>; + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys"; + + clocks = + <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>; + clock-names = "gcc_iface", "gcc_bus", + "iface_clk", "core_clk", "vsync_clk", + "lut_clk", "rot_clk"; + clock-rate = <0 0 0 256000000 19200000 192000000>; + clock-max-rate = <0 0 0 307000000 19200000 307000000>; + + /* Enable thermal cooling device */ + #cooling-cells = <2>; + + /* interrupt config */ + interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x45c>; + + qcom,sde-ctl-off = <0x2000 0x2200 0x2400 + 0x0 0x0 0x0>; + qcom,sde-ctl-size = <0x1e0>; + qcom,sde-ctl-display-pref = "primary", "none", "none", + "none", "none", "none"; + + qcom,sde-mixer-off = <0x45000 0x46000 0x47000 + 0x0 0x0 0x0>; + qcom,sde-mixer-size = <0x320>; + qcom,sde-mixer-display-pref = "primary", "none", "none", + "none", "none", "none"; + + qcom,sde-mixer-cwb-pref = "none", "none", "cwb", + "none", "none", "none"; + + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x80>; + qcom,sde-dspp-off = <0x55000>; + qcom,sde-dspp-size = <0x1800>; + + qcom,sde-wb-off = <0x66000>; + qcom,sde-wb-size = <0x2c8>; + qcom,sde-wb-xin-id = <6>; + qcom,sde-wb-id = <2>; + qcom,sde-wb-clk-ctrl = <0x3b8 24>; + + qcom,sde-intf-off = <0x6b000 0x6b800 0x6c000 + 0x6c800>; + + qcom,sde-intf-size = <0x2b8>; + qcom,sde-intf-type = "dp", "dsi","none", "dp"; + + qcom,sde-pp-off = <0x71000 0x71800 + 0x72000>; + qcom,sde-pp-slave = <0x0 0x0 0x0>; + qcom,sde-pp-size = <0xd4>; + + qcom,sde-te2-off = <0x2000 0x2000 0x0>; + + qcom,sde-cdm-off = <0x7a200>; + qcom,sde-cdm-size = <0x224>; + + qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0 0x30e0>; + qcom,sde-dither-version = <0x00010000>; + qcom,sde-dither-size = <0x20>; + + qcom,sde-sspp-type = "vig", "dma", "dma", "dma", "dma"; + qcom,sde-sspp-off = <0x5000 0x25000 0x27000 0x29000 + 0x2b000>; + qcom,sde-sspp-src-size = <0x1f0>; + + qcom,sde-sspp-xin-id = <0 1 5 9 13>; + qcom,sde-sspp-excl-rect = <1 1 1 1 1>; + qcom,sde-sspp-smart-dma-priority = <5 1 2 3 4>; + qcom,sde-smart-dma-rev = "smart_dma_v2p5"; + + qcom,sde-mixer-pair-mask = <3 0 1 0 0 0>; + + qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 + 0xb0 0xc8 0xe0 0xf8 0x110>; + + qcom,sde-max-per-pipe-bw-kbps = <4500000 + 4500000 4500000 + 4500000 4500000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = + <0x2ac 0>, <0x2ac 8>, <0x2b4 8>, <0x2bc 8>, + <0x2c4 8>; + qcom,sde-sspp-csc-off = <0x1a00>; + qcom,sde-csc-type = "csc-10bit"; + qcom,sde-qseed-type = "qseedv3lite"; + qcom,sde-sspp-qseed-off = <0xa00>; + qcom,sde-mixer-linewidth = <2560>; + qcom,sde-sspp-linewidth = <2160>; + qcom,sde-wb-linewidth = <2160>; + qcom,sde-mixer-blendstages = <0x9>; + qcom,sde-highest-bank-bit = <0x1>; + qcom,sde-ubwc-version = <0x200>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + + qcom,sde-has-dim-layer; + qcom,sde-has-idle-pc; + + qcom,sde-max-bw-low-kbps = <4800000>; + qcom,sde-max-bw-high-kbps = <4800000>; + qcom,sde-min-core-ib-kbps = <2400000>; + qcom,sde-min-llcc-ib-kbps = <800000>; + qcom,sde-min-dram-ib-kbps = <800000>; + qcom,sde-dram-channels = <2>; + qcom,sde-num-nrt-paths = <0>; + + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-size = <0x1040>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; + + qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; + qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; + + /* macrotile & macrotile-qseed has the same configs */ + qcom,sde-danger-lut = <0x0000000f 0x0000ffff + 0x00000000 0x00000000 0x0000ffff>; + + qcom,sde-safe-lut-linear = <0 0xfff8>; + qcom,sde-safe-lut-macrotile = <0 0xf000>; + /* same as safe-lut-macrotile */ + qcom,sde-safe-lut-macrotile-qseed = <0 0xf000>; + qcom,sde-safe-lut-nrt = <0 0xffff>; + qcom,sde-safe-lut-cwb = <0 0xffff>; + + qcom,sde-qos-lut-linear = <0 0x00112222 0x22223357>; + qcom,sde-qos-lut-macrotile = <0 0x00112233 0x44556677>; + qcom,sde-qos-lut-macrotile-qseed = <0 0x00112233 0x66777777>; + qcom,sde-qos-lut-nrt = <0 0x00000000 0x00000000>; + qcom,sde-qos-lut-cwb = <0 0x75300000 0x00000000>; + + qcom,sde-cdp-setting = <1 1>, <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-dma-latency = <300>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-reg-dma-off = <0>; + qcom,sde-reg-dma-version = <0x00010001>; + qcom,sde-reg-dma-trigger-off = <0x119c>; + + qcom,sde-secure-sid-mask = <0x0000801>; + + /* data and reg bus scale settings */ + interconnects = + <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", + "qcom,sde-reg-bus"; + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 76800>, + <0 150000>, + <0 300000>; + + qcom,sde-sspp-vig-blocks { + qcom,sde-vig-csc-off = <0x1a00>; + qcom,sde-vig-qseed-off = <0xa00>; + qcom,sde-vig-qseed-size = <0xa0>; + qcom,sde-vig-inverse-pma; + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x0 0x00030001>; + qcom,sde-dspp-hsic = <0x800 0x00010007>; + qcom,sde-dspp-memcolor = <0x880 0x00010007>; + qcom,sde-dspp-hist = <0x800 0x00010007>; + qcom,sde-dspp-sixzone= <0x900 0x00010007>; + qcom,sde-dspp-vlut = <0xa00 0x00010008>; + qcom,sde-dspp-gamut = <0x1000 0x00040001>; + qcom,sde-dspp-pcc = <0x1700 0x00040000>; + qcom,sde-dspp-gc = <0x17c0 0x00010008>; + qcom,sde-dspp-dither = <0x82c 0x00010007>; + }; + }; + + sde_rscc: qcom,sde_rscc@af20000 { + cell-index = <0>; + compatible = "qcom,sde-rsc"; + reg = <0xaf20000 0x1c44>, + <0xaf30000 0x3fd4>; + reg-names = "drv", "wrapper"; + qcom,sde-rsc-version = <2>; + + vdd-supply = <&mdss_core_gdsc>; + clocks = <&dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_NON_GDSC_AHB_CLK>, + <&dispcc DISP_CC_MDSS_RSCC_AHB_CLK>; + clock-names = "vsync_clk", "gdsc_clk", "iface_clk"; + clock-rate = <0 0 0>; + + qcom,sde-dram-channels = <2>; + + mboxes = <&disp_rsc 0>; + mbox-names = "disp_rsc"; + + qcom,msm-bus,active-only; + interconnects = + <&mmss_noc MASTER_MDP0_DISP &gem_noc SLAVE_LLCC_DISP>, + <&mc_virt MASTER_LLCC_DISP &mc_virt SLAVE_EBI1_DISP>; + interconnect-names = "qcom,sde-data-bus0", + "qcom,sde-ebi-bus"; + }; + + mdss_rotator: qcom,mdss_rotator@ae00000 { + compatible = "qcom,sde_rotator"; + reg = <0x0ae00000 0xac000>, + <0x0aeb8000 0x3000>; + reg-names = "mdp_phys", + "rot_vbif_phys"; + + #list-cells = <1>; + + qcom,mdss-rot-mode = <1>; + qcom,mdss-highest-bank-bit = <0x1>; + + interconnects = + <&mmss_noc MASTER_ROTATOR &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,rot-data-bus0", + "qcom,sde-reg-bus"; + qcom,msm-bus,active-only; + + rot-vdd-supply = <&mdss_core_gdsc>; + qcom,supply-names = "rot-vdd"; + + clocks = + <&gcc GCC_DISP_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>; + clock-names = "gcc_iface", + "iface_clk", "rot_clk"; + + interrupt-parent = <&mdss_mdp>; + interrupts = <2 0>; + + power-domains = <&mdss_mdp>; + + /* Offline rotator QoS setting */ + qcom,mdss-rot-vbif-qos-setting = <3 3 3 3 3 3 3 3>; + qcom,mdss-rot-vbif-memtype = <3 3>; + qcom,mdss-rot-cdp-setting = <1 1>; + qcom,mdss-rot-qos-lut = <0x0 0x0 0x0 0x0>; + qcom,mdss-rot-danger-lut = <0x0 0x0>; + qcom,mdss-rot-safe-lut = <0x0000ffff 0x0000ffff>; + + qcom,mdss-rot-qos-cpu-mask = <0xf>; + qcom,mdss-rot-qos-cpu-dma-latency = <75>; + + qcom,mdss-default-ot-rd-limit = <32>; + qcom,mdss-default-ot-wr-limit = <32>; + + qcom,mdss-sbuf-headroom = <20>; + + cache-slice-names = "rotator"; + + /* reg bus scale settings */ + rot_reg: qcom,rot-reg-bus { + qcom,msm-bus,name = "mdss_rot_reg"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 590 0 0>, + <1 590 0 76800>; + }; + + smmu_rot_unsec: qcom,smmu_rot_unsec_cb { + compatible = "qcom,smmu_sde_rot_unsec"; + iommus = <&apps_smmu 0xc40 0x0>; + }; + + smmu_rot_sec: qcom,smmu_rot_sec_cb { + compatible = "qcom,smmu_sde_rot_sec"; + iommus = <&apps_smmu 0xc41 0x0>; + }; + }; + + mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { + compatible = "qcom,dsi-ctrl-hw-v2.3"; + label = "dsi-ctrl-0"; + cell-index = <0>; + reg = <0xae94000 0x400>, + <0xaf08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + vdda-1p2-supply = <&pm6150l_l3>; + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", + "esc_clk"; + qcom,split-link-supported; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1232000>; + qcom,supply-max-voltage = <1232000>; + qcom,supply-enable-load = <21800>; + qcom,supply-disable-load = <0>; + }; + }; + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94400 { + compatible = "qcom,dsi-phy-v2.0"; + label = "dsi-phy-0"; + cell-index = <0>; + #clock-cells = <1>; + reg = <0xae94400 0x588>, + <0xae01400 0x100>, + <0xae94200 0x100>, + <0xae94400 0x588>, + <0xaf03000 0x8>; + reg-names = "dsi_phy", "phy_clamp_base", + "dyn_refresh_base", "pll_base", "gdsc_base"; + pll-label = "dsi_pll_14nm"; + memory-region = <&dfps_data_memory>; + vdda-0p9-supply = <&pm6150_l4>; + qcom,platform-strength-ctrl = [ff 06 + ff 06 + ff 06 + ff 06 + ff 00]; + qcom,platform-lane-config = [00 00 10 0f + 00 00 10 0f + 00 00 10 0f + 00 00 10 0f + 00 00 10 8f]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <975000>; + qcom,supply-enable-load = <36000>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + ext_disp: qcom,msm-ext-disp { + compatible = "qcom,msm-ext-disp"; + + ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { + compatible = "qcom,msm-ext-disp-audio-codec-rx"; + }; + }; + + qcom_msmhdcp: qcom,msm_hdcp { + compatible = "qcom,msm-hdcp"; + cell-index = <0>; + }; + + sde_dp: qcom,dp_display@ae90000 { + cell-index = <0>; + compatible = "qcom,dp-display"; + + vdda-1p2-supply = <&pm6150l_l3>; + vdda-0p9-supply = <&pm6150_l4>; + reg = <0xae90000 0x0f4>, + <0xae90200 0x0c0>, + <0xae90400 0x5e0>, + <0xae90a00 0x098>, + <0x88e9000 0x17c>, + <0x88e9400 0x10c>, + <0x88e9800 0x10c>, + <0xaf02130 0x8>, + <0x780000 0x621c>, + <0x88e9c30 0x10>, + <0xaee1000 0x34>, + <0x1fcb24c 0x4>, + <0xae91000 0x098>; + + /* dp_ctrl: dp_ahb, dp_aux, dp_link, dp_p0 */ + reg-names = "dp_ahb", "dp_aux", "dp_link", + "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", + "dp_pixel_mn", "qfprom_physical", "dp_pll", + "hdcp_physical", "dp_tcsr","dp_p1"; + + interrupt-parent = <&mdss_mdp>; + interrupts = <12 0>; + + clocks = <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_AHB2PHY_WEST_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>, + <&dispcc DISP_CC_MDSS_DP_CRYPTO_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&sde_dp DP_PHY_PLL_VCO_DIV_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>, + <&sde_dp DP_PHY_PLL_VCO_DIV_CLK>; + + clock-names = "core_aux_clk", "core_usb_ref_clk_src", + "core_usb_ahb_clk", "core_usb_sec_ref_clk", + "link_clk", "link_iface_clk", + "strm0_pixel_clk","strm1_pixel_clk", "crypto_clk", + "pixel_clk_rcg", "pixel_parent","pixel1_clk_rcg", + "pixel1_parent"; + + + qcom,phy-version = <0x200>; + qcom,aux-cfg0-settings = [20 00]; + qcom,aux-cfg1-settings = [24 13 23 1d]; + qcom,aux-cfg2-settings = [28 00]; + qcom,aux-cfg3-settings = [2c 00]; + qcom,aux-cfg4-settings = [30 0a]; + qcom,aux-cfg5-settings = [34 26]; + qcom,aux-cfg6-settings = [38 0a]; + qcom,aux-cfg7-settings = [3c 03]; + qcom,aux-cfg8-settings = [40 bb]; + qcom,aux-cfg9-settings = [44 03]; + + qcom,logical2physical-lane-map = [03 02 00 01]; + + qcom,max-lclk-frequency-khz = <540000>; + qcom,max-pclk-frequency-khz = <195000>; + + qcom,max-hdisplay = <1920>; + qcom,max-vdisplay = <1200>; + + qcom,ext-disp = <&ext_disp>; + qcom,dp-aux-switch = <&fsa4480>; + + qcom,mux-sel-gpio = <&tlmm 49 0>; + qcom,usbplug-cc-gpio = <&tlmm 104 0>; + + pinctrl-names = "mdss_dp_active", "mdss_dp_sleep", + "mdss_dp_hpd_active", "mdss_dp_hpd_tlmm", + "mdss_dp_hpd_ctrl"; + pinctrl-0 = <&sde_dp_usbplug_cc_active &sde_dp_switch_active>; + pinctrl-1 = <&sde_dp_usbplug_cc_suspend &sde_dp_switch_suspend>; + pinctrl-2 = <&sde_dp_connector_enable &sde_dp_switch_suspend + &sde_dp_hotplug_tlmm>; + pinctrl-3 = <&sde_dp_hotplug_tlmm>; + pinctrl-4 = <&sde_dp_hotplug_ctrl>; + + qcom,msm-hdcp = <&qcom_msmhdcp>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1232000>; + qcom,supply-max-voltage = <1232000>; + qcom,supply-enable-load = <21800>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + smmu_sde_sec: qcom,smmu_sde_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&apps_smmu 0x801 0x0>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-vmid = <0xa>; + }; + + smmu_sde_unsec:qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x800 0x0>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-earlymap; /* for cont-splash */ + }; +}; From a3ff157b4da55a6837384022a1640d57d1787ad9 Mon Sep 17 00:00:00 2001 From: Ke Du Date: Fri, 19 Nov 2021 17:57:37 +0530 Subject: [PATCH 2/9] ARM: dts: msm: add sde display dts for scuba Add sde display dts for scuba. Change-Id: Ibe872711442f2b809c9170c806acbc9cb662b5e0 --- display/scuba-sde-common.dtsi | 276 ++++++++++++++++++++++++++ display/scuba-sde-display-common.dtsi | 58 ++++++ display/scuba-sde-display-idp.dtsi | 9 + display/scuba-sde-display.dtsi | 27 +++ display/scuba-sde.dtsi | 57 ++++++ 5 files changed, 427 insertions(+) create mode 100644 display/scuba-sde-common.dtsi create mode 100644 display/scuba-sde-display-common.dtsi create mode 100644 display/scuba-sde-display-idp.dtsi create mode 100644 display/scuba-sde-display.dtsi create mode 100644 display/scuba-sde.dtsi diff --git a/display/scuba-sde-common.dtsi b/display/scuba-sde-common.dtsi new file mode 100644 index 000000000000..7656671b7126 --- /dev/null +++ b/display/scuba-sde-common.dtsi @@ -0,0 +1,276 @@ +#include + +&soc { + mdss_mdp: qcom,mdss_mdp { + compatible = "qcom,sde-kms"; + reg = <0x5e00000 0x8f030>, + <0x5eb0000 0x2008>, + <0x5e8f000 0x02c>, + <0xc125ba4 0x20>; + reg-names = "mdp_phys", + "vbif_phys", + "sid_phys", + "sde_imem_phys"; + + clock-rate = <0 0 0 300000000 19200000 192000000>; + clock-max-rate = <0 0 0 400000000 19200000 400000000>; + + sde-vdd-supply = <&mdss_core_gdsc>; + + /* Enable thermal cooling device */ + #cooling-cells = <2>; + + /* interrupt config */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + #power-domain-cells = <0>; + + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x494>; + + qcom,sde-ctl-off = <0x2000>; + qcom,sde-ctl-size = <0x1dc>; + qcom,sde-ctl-display-pref = "primary"; + + qcom,sde-mixer-off = <0x45000>; + qcom,sde-mixer-size = <0x320>; + qcom,sde-mixer-display-pref = "primary"; + + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x80>; + qcom,sde-dspp-off = <0x55000>; + qcom,sde-dspp-size = <0xfe4>; + + qcom,sde-intf-off = <0x0 0x6b800>; + qcom,sde-intf-size = <0x2b8>; + qcom,sde-intf-type = "none", "dsi"; + + qcom,sde-pp-off = <0x71000>; + qcom,sde-pp-size = <0xd4>; + + qcom,sde-dither-off = <0x30e0>; + qcom,sde-dither-version = <0x00010000>; + qcom,sde-dither-size = <0x20>; + + qcom,sde-sspp-type = "vig", "dma"; + + qcom,sde-sspp-off = <0x5000 0x25000>; + qcom,sde-sspp-src-size = <0x1f8>; + + qcom,sde-sspp-xin-id = <0 1>; + qcom,sde-sspp-excl-rect = <1 1>; + qcom,sde-sspp-smart-dma-priority = <2 1>; + qcom,sde-smart-dma-rev = "smart_dma_v2p5"; + + qcom,sde-mixer-pair-mask = <0>; + + qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 + 0xb0 0xc8 0xe0 0xf8 0x110>; + + qcom,sde-mixer-stage-base-layer; + + qcom,sde-max-per-pipe-bw-kbps = <2700000 2700000>; + + qcom,sde-max-per-pipe-bw-high-kbps = <2700000 2700000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2ac 8>; + qcom,sde-mixer-linewidth = <2048>; + qcom,sde-mixer-blendstages = <0x4>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + + qcom,sde-has-dim-layer; + qcom,sde-has-idle-pc; + + qcom,sde-max-bw-low-kbps = <2700000>; + qcom,sde-max-bw-high-kbps = <2700000>; + qcom,sde-min-core-ib-kbps = <1300000>; + qcom,sde-min-llcc-ib-kbps = <0>; + qcom,sde-min-dram-ib-kbps = <1600000>; + qcom,sde-dram-channels = <2>; + qcom,sde-num-nrt-paths = <0>; + + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-size = <0x2008>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; + + qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; + + /*Pending macrotile & macrotile-qseed has the same configs */ + + qcom,sde-danger-lut = <0x000000ff 0x00000000 + 0x00000000 0x00000000 0x00000000>; + + qcom,sde-safe-lut-linear = <0 0xfff0>; + + qcom,sde-qos-lut-linear = <0 0x00112222 0x22335777>; + + qcom,sde-cdp-setting = <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-dma-latency = <300>; + + qcom,sde-secure-sid-mask = <0x0000421>; + qcom,sde-num-mnoc-ports = <1>; + qcom,sde-axi-bus-width = <16>; + + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 76800>, + <0 150000>, + <0 300000>; + + qcom,sde-sspp-vig-blocks { + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x0 0x00030001>; + qcom,sde-dspp-hsic = <0x800 0x00010007>; + qcom,sde-dspp-memcolor = <0x880 0x00010007>; + qcom,sde-dspp-hist = <0x800 0x00010007>; + qcom,sde-dspp-sixzone= <0x900 0x00010007>; + qcom,sde-dspp-vlut = <0xa00 0x00010008>; + qcom,sde-dspp-pcc = <0x1700 0x00040000>; + qcom,sde-dspp-gc = <0x17c0 0x00010008>; + qcom,sde-dspp-dither = <0x82c 0x00010007>; + }; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "sde-vdd"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + + /* data and reg bus scale settings */ + qcom,sde-data-bus { + qcom,msm-bus,name = "mdss_sde"; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <22 512 0 0>, + <22 512 0 4800000>, + <22 512 0 4800000>; + }; + + qcom,sde-limits { + qcom,sde-linewidth-limits { + qcom,sde-limit-name = "sspp_linewidth_usecases"; + qcom,sde-limit-cases = "vig", "dma"; + qcom,sde-limit-ids= <0x1 0x2>; + qcom,sde-limit-values = <0x1 2160>, + <0x2 2160>; + }; + + qcom,sde-bw-limits { + qcom,sde-limit-name = "sde_bwlimit_usecases"; + qcom,sde-limit-cases = "per_vig_pipe", + "per_dma_pipe", + "total_max_bw", + "camera_concurrency"; + qcom,sde-limit-ids = <0x1 0x2 0x4 0x8>; + qcom,sde-limit-values = <0x1 2700000>, + <0x9 2700000>, + <0x2 2700000>, + <0xa 2700000>, + <0x4 2700000>, + <0xc 2700000>; + }; + }; + }; + + mdss_dsi0: qcom,mdss_dsi_ctrl0@5e94000 { + compatible = "qcom,dsi-ctrl-hw-v2.4"; + label = "dsi-ctrl-0"; + cell-index = <0>; + frame-threshold-time-us = <800>; + reg = <0x5e94000 0x400>, + <0x5f08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1232000>; + qcom,supply-max-voltage = <1312000>; + qcom,supply-enable-load = <21800>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy0 { + compatible = "qcom,dsi-phy-v2.0"; + label = "dsi-phy-0"; + cell-index = <0>; + #clock-cells = <1>; + reg = <0x5e94400 0x588>, + <0x5e01400 0x100>, + <0x5e94200 0x100>, + <0x5e94400 0x588>, + <0x5f03000 0x8>; + reg-names = "dsi_phy", "phy_clamp_base", + "dyn_refresh_base", "pll_base", "gdsc_base"; + pll-label = "dsi_pll_14nm"; + + qcom,platform-strength-ctrl = [ff 06 + ff 06 + ff 06 + ff 06 + ff 00]; + qcom,platform-lane-config = [00 00 10 0f + 00 00 10 0f + 00 00 10 0f + 00 00 10 0f + 00 00 10 8f]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = + ; + qcom,supply-max-voltage = + ; + qcom,supply-off-min-voltage = + ; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; +}; diff --git a/display/scuba-sde-display-common.dtsi b/display/scuba-sde-display-common.dtsi new file mode 100644 index 000000000000..874322b1111e --- /dev/null +++ b/display/scuba-sde-display-common.dtsi @@ -0,0 +1,58 @@ +#include "dsi-panel-ext-bridge-1080p.dtsi" +#include "dsi-panel-ili988c-dual-video.dtsi" +#include + +&soc { + dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <2000000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + sde_dsi: qcom,dsi-display-primary { + compatible = "qcom,dsi-display"; + label = "primary"; + + qcom,dsi-ctrl = <&mdss_dsi0>; + qcom,dsi-phy = <&mdss_dsi_phy0>; + + qcom,mdp = <&mdss_mdp>; + qcom,dsi-default-panel = <&dsi_ili9881c_720p_video>; + }; +}; + +&dsi_ext_bridge_1080p { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; +}; + +&dsi_ili9881c_720p_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0a>; + qcom,mdss-dsi-t-clk-pre = <0x21>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-timings = [ + 1F 1C 04 06 03 02 0a + 1F 1C 04 06 03 02 0a + 1F 1C 04 06 03 02 0a + 1F 1C 04 06 03 02 0a + 1F 10 04 06 03 02 0a + ]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/display/scuba-sde-display-idp.dtsi b/display/scuba-sde-display-idp.dtsi new file mode 100644 index 000000000000..af2fa18ab86f --- /dev/null +++ b/display/scuba-sde-display-idp.dtsi @@ -0,0 +1,9 @@ +#include "scuba-sde-display.dtsi" + +&dsi_ili9881c_720p_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 97 0>; +}; diff --git a/display/scuba-sde-display.dtsi b/display/scuba-sde-display.dtsi new file mode 100644 index 000000000000..a448b54798f4 --- /dev/null +++ b/display/scuba-sde-display.dtsi @@ -0,0 +1,27 @@ +#include "scuba-sde-display-common.dtsi" +#include + +&sde_dsi { + clocks = <&mdss_dsi_phy0 BYTE0_MUX_CLK>, + <&mdss_dsi_phy0 PIX0_MUX_CLK>, + <&mdss_dsi_phy0 BYTE0_SRC_CLK>, + <&mdss_dsi_phy0 PIX0_SRC_CLK>, + <&mdss_dsi_phy0 SHADOW_BYTE0_SRC_CLK>, + <&mdss_dsi_phy0 SHADOW_PIX0_SRC_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi_active &sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; + + qcom,platform-te-gpio = <&tlmm 40 0>; + qcom,panel-te-source = <0>; + + vddio-supply = <&L15A>; +}; + +&mdss_mdp { + connectors = <&smmu_sde_unsec &sde_dsi>; +}; diff --git a/display/scuba-sde.dtsi b/display/scuba-sde.dtsi new file mode 100644 index 000000000000..ee2f3c6e35c7 --- /dev/null +++ b/display/scuba-sde.dtsi @@ -0,0 +1,57 @@ +#include "scuba-sde-common.dtsi" +#include + +&soc { + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x420 0x2>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-earlymap; /* for cont-splash */ + }; + + smmu_sde_sec: qcom,smmu_sde_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&apps_smmu 0x421 0x0>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xa>; + }; +}; + +&mdss_mdp { + clocks = + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_THROTTLE_CORE_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; + clock-names = "gcc_bus", "throttle_clk", "iface_clk", + "core_clk", "vsync_clk", "lut_clk"; + + /* data and reg bus scale settings */ + interconnects = <&mmrt_virt MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", "qcom,sde-reg-bus"; +}; + +&mdss_dsi0 { + vdda-1p2-supply = <&L5A>; + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi_phy0 { + vdda-0p9-supply = <&VDD_MX_LEVEL>; + qcom,panel-allow-phy-poweroff; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + memory-region = <&dfps_data_memory>; +}; From 62832f81b3dda3c2109c916bef506dad660b3e67 Mon Sep 17 00:00:00 2001 From: Ke Du Date: Fri, 19 Nov 2021 18:20:22 +0530 Subject: [PATCH 3/9] ARM: dts: msm: add sde display dts for bengal Add sde display dts for bengal. Change-Id: I94aeab8f31fa699f93f7776d860c42a8fcdef2a2 --- display/bengal-sde-common.dtsi | 279 +++++++++++++++++++++++++ display/bengal-sde-display-common.dtsi | 58 +++++ display/bengal-sde-display-idp.dtsi | 9 + display/bengal-sde-display.dtsi | 27 +++ display/bengal-sde.dtsi | 57 +++++ 5 files changed, 430 insertions(+) create mode 100644 display/bengal-sde-common.dtsi create mode 100644 display/bengal-sde-display-common.dtsi create mode 100644 display/bengal-sde-display-idp.dtsi create mode 100644 display/bengal-sde-display.dtsi create mode 100644 display/bengal-sde.dtsi diff --git a/display/bengal-sde-common.dtsi b/display/bengal-sde-common.dtsi new file mode 100644 index 000000000000..3ec22e548880 --- /dev/null +++ b/display/bengal-sde-common.dtsi @@ -0,0 +1,279 @@ +#include + +&soc { + mdss_mdp: qcom,mdss_mdp { + compatible = "qcom,sde-kms"; + reg = <0x5e00000 0x8f030>, + <0x5eb0000 0x2008>, + <0x5e8f000 0x02c>, + <0xc125ba4 0x20>; + + reg-names = "mdp_phys", + "vbif_phys", + "sid_phys", + "sde_imem_phys"; + + clock-rate = <0 0 0 300000000 19200000 192000000>; + clock-max-rate = <0 0 0 400000000 19200000 400000000>; + + sde-vdd-supply = <&mdss_core_gdsc>; + + /* Enable thermal cooling device */ + #cooling-cells = <2>; + + /* interrupt config */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + #power-domain-cells = <0>; + + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x494>; + + qcom,sde-ctl-off = <0x2000>; + qcom,sde-ctl-size = <0x1dc>; + qcom,sde-ctl-display-pref = "primary"; + + qcom,sde-mixer-off = <0x45000>; + qcom,sde-mixer-size = <0x320>; + qcom,sde-mixer-display-pref = "primary"; + + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x80>; + qcom,sde-dspp-off = <0x55000>; + qcom,sde-dspp-size = <0xfe4>; + + qcom,sde-intf-off = <0x0 0x6b800>; + qcom,sde-intf-size = <0x2b8>; + qcom,sde-intf-type = "none", "dsi"; + + qcom,sde-pp-off = <0x71000>; + qcom,sde-pp-size = <0xd4>; + + qcom,sde-dither-off = <0x30e0>; + qcom,sde-dither-version = <0x00010000>; + qcom,sde-dither-size = <0x20>; + + qcom,sde-sspp-type = "vig", "dma"; + + qcom,sde-sspp-off = <0x5000 0x25000>; + qcom,sde-sspp-src-size = <0x1f8>; + + qcom,sde-sspp-xin-id = <0 1>; + qcom,sde-sspp-excl-rect = <1 1>; + qcom,sde-sspp-smart-dma-priority = <2 1>; + qcom,sde-smart-dma-rev = "smart_dma_v2p5"; + + qcom,sde-mixer-pair-mask = <0>; + + qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 + 0xb0 0xc8 0xe0 0xf8 0x110>; + + qcom,sde-mixer-stage-base-layer; + + qcom,sde-max-per-pipe-bw-kbps = <2600000 2600000>; + + qcom,sde-max-per-pipe-bw-high-kbps = <2600000 2600000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = + <0x2ac 0>, <0x2ac 8>; + qcom,sde-mixer-linewidth = <2048>; + qcom,sde-mixer-blendstages = <0x4>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + + qcom,sde-has-dim-layer; + qcom,sde-has-idle-pc; + + qcom,sde-max-bw-low-kbps = <3100000>; + qcom,sde-max-bw-high-kbps = <4000000>; + qcom,sde-min-core-ib-kbps = <2400000>; + qcom,sde-min-llcc-ib-kbps = <800000>; + qcom,sde-min-dram-ib-kbps = <800000>; + qcom,sde-dram-channels = <1>; + qcom,sde-num-nrt-paths = <0>; + + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-size = <0x2008>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; + + qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; + + /*Pending macrotile & macrotile-qseed has the same configs */ + + qcom,sde-danger-lut = <0x000000ff 0x0000ffff + 0x00000000 0x00000000 0x0000ffff>; + + qcom,sde-safe-lut-linear = <0 0xfff0>; + + qcom,sde-qos-lut-linear = <0 0x00112222 0x22335777>; + + qcom,sde-cdp-setting = <1 1>, <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-dma-latency = <300>; + + qcom,sde-secure-sid-mask = <0x0000421>; + qcom,sde-num-mnoc-ports = <1>; + qcom,sde-axi-bus-width = <16>; + + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 76800>, + <0 150000>, + <0 300000>; + + qcom,sde-sspp-vig-blocks { + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x0 0x00030001>; + qcom,sde-dspp-hsic = <0x800 0x00010007>; + qcom,sde-dspp-memcolor = <0x880 0x00010007>; + qcom,sde-dspp-hist = <0x800 0x00010007>; + qcom,sde-dspp-sixzone= <0x900 0x00010007>; + qcom,sde-dspp-vlut = <0xa00 0x00010008>; + qcom,sde-dspp-pcc = <0x1700 0x00040000>; + qcom,sde-dspp-gc = <0x17c0 0x00010008>; + qcom,sde-dspp-dither = <0x82c 0x00010007>; + }; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "sde-vdd"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + + /* data and reg bus scale settings */ + qcom,sde-data-bus { + qcom,msm-bus,name = "mdss_sde"; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <22 512 0 0>, + <22 512 0 4800000>, + <22 512 0 4800000>; + }; + + qcom,sde-limits { + qcom,sde-linewidth-limits { + qcom,sde-limit-name = "sspp_linewidth_usecases"; + qcom,sde-limit-cases = "vig", "dma", "scale"; + qcom,sde-limit-ids= <0x1 0x2 0x4>; + qcom,sde-limit-values = <0x1 4096>, + <0x5 2560>, + <0x2 2160>; + }; + + qcom,sde-bw-limits { + qcom,sde-limit-name = "sde_bwlimit_usecases"; + qcom,sde-limit-cases = "per_vig_pipe", + "per_dma_pipe", + "total_max_bw", + "camera_concurrency"; + qcom,sde-limit-ids = <0x1 0x2 0x4 0x8>; + qcom,sde-limit-values = <0x1 2600000>, + <0x9 2600000>, + <0x2 2600000>, + <0xa 2600000>, + <0x4 4000000>, + <0xc 3100000>; + }; + }; + }; + + mdss_dsi0: qcom,mdss_dsi_ctrl0@5e94000 { + compatible = "qcom,dsi-ctrl-hw-v2.4"; + label = "dsi-ctrl-0"; + cell-index = <0>; + frame-threshold-time-us = <800>; + reg = <0x5e94000 0x400>, + <0x5f08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1232000>; + qcom,supply-max-voltage = <1232000>; + qcom,supply-enable-load = <21800>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy0@5e94400 { + compatible = "qcom,dsi-phy-v2.0"; + label = "dsi-phy-0"; + cell-index = <0>; + #clock-cells = <1>; + reg = <0x5e94400 0x588>, + <0x5e01400 0x100>, + <0x5e94200 0x100>, + <0x5e94400 0x588>, + <0x5f03000 0x8>; + reg-names = "dsi_phy", "phy_clamp_base", + "dyn_refresh_base", "pll_base", "gdsc_base"; + pll-label = "dsi_pll_14nm"; + + qcom,platform-strength-ctrl = [ff 06 + ff 06 + ff 06 + ff 06 + ff 00]; + qcom,platform-lane-config = [00 00 10 0f + 00 00 10 0f + 00 00 10 0f + 00 00 10 0f + 00 00 10 8f]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = + ; + qcom,supply-max-voltage = + ; + qcom,supply-off-min-voltage = + ; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; +}; diff --git a/display/bengal-sde-display-common.dtsi b/display/bengal-sde-display-common.dtsi new file mode 100644 index 000000000000..9bad96b9fd90 --- /dev/null +++ b/display/bengal-sde-display-common.dtsi @@ -0,0 +1,58 @@ +#include "dsi-panel-ext-bridge-1080p.dtsi" +#include "dsi-panel-ili988c-dual-video.dtsi" +#include + +&soc { + dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + sde_dsi: qcom,dsi-display-primary { + compatible = "qcom,dsi-display"; + label = "primary"; + + qcom,dsi-ctrl = <&mdss_dsi0>; + qcom,dsi-phy = <&mdss_dsi_phy0>; + + qcom,mdp = <&mdss_mdp>; + qcom,dsi-default-panel = <&dsi_ili9881c_720p_video>; + }; +}; + +&dsi_ext_bridge_1080p { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; +}; + +&dsi_ili9881c_720p_video { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + qcom,mdss-dsi-t-clk-post = <0x0a>; + qcom,mdss-dsi-t-clk-pre = <0x21>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-timings = [ + 1F 1C 04 06 03 02 0a + 1F 1C 04 06 03 02 0a + 1F 1C 04 06 03 02 0a + 1F 1C 04 06 03 02 0a + 1F 10 04 06 03 02 0a + ]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/display/bengal-sde-display-idp.dtsi b/display/bengal-sde-display-idp.dtsi new file mode 100644 index 000000000000..20833de7e864 --- /dev/null +++ b/display/bengal-sde-display-idp.dtsi @@ -0,0 +1,9 @@ +#include "bengal-sde-display.dtsi" + +&dsi_ili9881c_720p_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 97 0>; +}; diff --git a/display/bengal-sde-display.dtsi b/display/bengal-sde-display.dtsi new file mode 100644 index 000000000000..582b8e9c125c --- /dev/null +++ b/display/bengal-sde-display.dtsi @@ -0,0 +1,27 @@ +#include "bengal-sde-display-common.dtsi" +#include + +&sde_dsi { + clocks = <&mdss_dsi_phy0 BYTE0_MUX_CLK>, + <&mdss_dsi_phy0 PIX0_MUX_CLK>, + <&mdss_dsi_phy0 BYTE0_SRC_CLK>, + <&mdss_dsi_phy0 PIX0_SRC_CLK>, + <&mdss_dsi_phy0 SHADOW_BYTE0_SRC_CLK>, + <&mdss_dsi_phy0 SHADOW_PIX0_SRC_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi_active &sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; + + qcom,platform-te-gpio = <&tlmm 40 0>; + qcom,panel-te-source = <0>; + + vddio-supply = <&L9A>; +}; + +&mdss_mdp { + connectors = <&smmu_sde_unsec &sde_dsi>; +}; diff --git a/display/bengal-sde.dtsi b/display/bengal-sde.dtsi new file mode 100644 index 000000000000..700bfc2cf3a9 --- /dev/null +++ b/display/bengal-sde.dtsi @@ -0,0 +1,57 @@ +#include "bengal-sde-common.dtsi" +#include + +&soc { + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x420 0x2>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-earlymap; /* for cont-splash */ + }; + + smmu_sde_sec: qcom,smmu_sde_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&apps_smmu 0x421 0x0>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xa>; + }; +}; + +&mdss_mdp { + clocks = + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_THROTTLE_CORE_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; + clock-names = "gcc_bus", "throttle_clk", "iface_clk", + "core_clk", "vsync_clk", "lut_clk"; + + /* data and reg bus scale settings */ + interconnects = <&mmrt_virt MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", "qcom,sde-reg-bus"; +}; + +&mdss_dsi0 { + vdda-1p2-supply = <&L18A>; + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi_phy0 { + vdda-0p9-supply = <&VDD_MX_LEVEL>; + qcom,panel-allow-phy-poweroff; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + memory-region = <&dfps_data_memory>; +}; From e1fd0b648dc6ddc5b89ca1d05942bea16d6304b2 Mon Sep 17 00:00:00 2001 From: Ke Du Date: Thu, 2 Dec 2021 15:16:00 +0530 Subject: [PATCH 4/9] ARM: dts: msm: add pll dts of display for QCS610 Add pll dts of display for QCS610. Change-Id: I91b314f6da814ae0a0e94f8a96b9115ae33ded00 --- display/sm6150-sde-pll.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 display/sm6150-sde-pll.dtsi diff --git a/display/sm6150-sde-pll.dtsi b/display/sm6150-sde-pll.dtsi new file mode 100644 index 000000000000..cfd39040a95e --- /dev/null +++ b/display/sm6150-sde-pll.dtsi @@ -0,0 +1,11 @@ +&soc { + mdss_dsi0_pll: qcom,mdss_dsi_pll@ae94400 { + status = "disabled"; + compatible = "qcom,dsi-phy-v2.0"; + }; + + mdss_dp_pll: qcom,mdss_dp_pll@88e9000 { + status = "disabled"; + compatible = "qcom,dp-display"; + }; +}; From e75791e4093aec98740eee71f451e5143a1a2d59 Mon Sep 17 00:00:00 2001 From: Sai Srujana Oruganti Date: Thu, 2 Dec 2021 20:55:32 +0530 Subject: [PATCH 5/9] ARM: dts: msm: enable dsi phy clamps Add dtsi entry to enable dsi phy clamps during 0p9 collapse Change-Id: Ib0f20ce18ad14dba00539a95f66b5b194b8e2248 --- display/monaco-sde.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/monaco-sde.dtsi b/display/monaco-sde.dtsi index 4603e6161032..2dad4e902bfc 100644 --- a/display/monaco-sde.dtsi +++ b/display/monaco-sde.dtsi @@ -309,6 +309,7 @@ 00 00 0a 0a 00 00 8a 8a]; qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,phy-clamp-enable; qcom,panel-allow-phy-poweroff; qcom,dsi-pll-ssc-en; qcom,dsi-pll-ssc-mode = "down-spread"; From d8b8b9049fb29c8529d0c042043b6a18cea9f43a Mon Sep 17 00:00:00 2001 From: BIVASH KUMAR SINGH Date: Fri, 3 Dec 2021 03:43:07 +0530 Subject: [PATCH 6/9] ARM: dts: msm: Add 120fps panel support for r66451 on Blair CDP Add 120fps panel support on Blair CDP for r66451. Change-Id: Id9fc229ace2316ce1cf364d0c419762fcaa87f34 --- display/blair-sde-display-cdp.dtsi | 32 ++++++++++++++++++++++++ display/holi-sde-display-cdp-pm6125.dtsi | 23 +++++++++++++++++ 2 files changed, 55 insertions(+) diff --git a/display/blair-sde-display-cdp.dtsi b/display/blair-sde-display-cdp.dtsi index 7ebe0dbf49b3..658b7d8ab9f9 100644 --- a/display/blair-sde-display-cdp.dtsi +++ b/display/blair-sde-display-cdp.dtsi @@ -111,6 +111,38 @@ }; }; +&dsi_r66451_amoled_cmd { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e 04 + 04 03 02 04 00 0e 09]; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06 + 06 06 02 04 00 14 0b]; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 16 07 + 07 08 02 04 00 19 0c]; + }; + }; +}; + +&dsi_r66451_amoled_video { + /delete-property/ qcom,mdss-dsi-t-clk-post; + /delete-property/ qcom,mdss-dsi-t-clk-pre; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 16 07 + 07 08 02 04 00 19 0c]; + }; + }; +}; + &dsi_rm69299_visionox_amoled_cmd { /delete-property/ qcom,mdss-dsi-t-clk-post; /delete-property/ qcom,mdss-dsi-t-clk-pre; diff --git a/display/holi-sde-display-cdp-pm6125.dtsi b/display/holi-sde-display-cdp-pm6125.dtsi index fc609eccdeb5..b79ffe749e83 100644 --- a/display/holi-sde-display-cdp-pm6125.dtsi +++ b/display/holi-sde-display-cdp-pm6125.dtsi @@ -88,3 +88,26 @@ qcom,platform-te-gpio = <&tlmm 23 0>; qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; }; + +&dsi_r66451_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,bl-update-flag = "delay_until_first_frame"; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; +}; + +&dsi_r66451_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,bl-update-flag = "delay_until_first_frame"; + qcom,platform-te-gpio = <&tlmm 23 0>; + qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>; +}; From 3d52a6ae94a9d9019580eab011e71e7aa334bf44 Mon Sep 17 00:00:00 2001 From: Vishnuvardhan Prodduturi Date: Thu, 16 Dec 2021 17:15:28 +0530 Subject: [PATCH 7/9] ARM: dts: msm: add dispcc clock reference for holi dsi-dsiplay node Currently the dsi clock handles are under the dsi controller DT node. As soon as the controller probe finishes, the dispcc sync state can get called before the dsi_display probe potentially disturbing the clock votes for cont_splash use case. dsi_display adds its component to the list of components hence controlling the bind which adds the dsi clock votes. There is no separate component for the dsi_ctrl. Hence we are no longer protected by the component model in this case against the disp cc sync state getting triggered after the dsi_ctrl probe. To protect against this incorrect sync state trigger add a dummy MDP clk vote handle to the dsi_display DT node. Since the dsi_display driver does not parse MDP clock nodes, no actual vote shall be added and this change is done just to satisfy sync state requirements. Change-Id: I18f0f89174bdf49492b5d9aef1fce3ad90801aa3 --- display/holi-sde-display.dtsi | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/display/holi-sde-display.dtsi b/display/holi-sde-display.dtsi index 19d406208854..0caafb882c4c 100644 --- a/display/holi-sde-display.dtsi +++ b/display/holi-sde-display.dtsi @@ -1,4 +1,5 @@ #include "holi-sde-display-common.dtsi" +#include &sde_dsi { clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, @@ -6,10 +7,26 @@ <&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>, <&mdss_dsi_phy0 PCLK_SRC_0_CLK>, <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, - <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>; + <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>, + /* + * Currently the dsi clock handles are under the dsi + * controller DT node. As soon as the controller probe + * finishes, the dispcc sync state can get called before + * the dsi_display probe potentially disturbing the clock + * votes for cont_splash use case. Hence we are no longer + * protected by the component model in this case against the + * disp cc sync state getting triggered after the dsi_ctrl + * probe. To protect against this incorrect sync state trigger + * add this dummy MDP clk vote handle to the dsi_display + * DT node. Since the dsi_display driver does not parse + * MDP clock nodes, no actual vote shall be added and this + * change is done just to satisfy sync state requirements. + */ + <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "mux_byte_clk0", "mux_pixel_clk0", "src_byte_clk0", "src_pixel_clk0", - "shadow_byte_clk0", "shadow_pixel_clk0"; + "shadow_byte_clk0", "shadow_pixel_clk0", + "mdp_core_clk"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_te_active &disp_pins_default>; From 7359a0c9546b3979b7a0fe3ef981d3050cd53336 Mon Sep 17 00:00:00 2001 From: Wanghao Wei Date: Sun, 12 Dec 2021 13:34:25 +0800 Subject: [PATCH 8/9] ARM: dts: msm: change target for bengal/scuba use qrd instead of idp for bengal/scuba according to cdt. Change-Id: I8966e38e5a5f3cc4e2e8c7bba86c5c1959fa2951 --- .../{bengal-sde-display-idp.dtsi => bengal-sde-display-qrd.dtsi} | 0 .../{scuba-sde-display-idp.dtsi => scuba-sde-display-qrd.dtsi} | 0 2 files changed, 0 insertions(+), 0 deletions(-) rename display/{bengal-sde-display-idp.dtsi => bengal-sde-display-qrd.dtsi} (100%) rename display/{scuba-sde-display-idp.dtsi => scuba-sde-display-qrd.dtsi} (100%) diff --git a/display/bengal-sde-display-idp.dtsi b/display/bengal-sde-display-qrd.dtsi similarity index 100% rename from display/bengal-sde-display-idp.dtsi rename to display/bengal-sde-display-qrd.dtsi diff --git a/display/scuba-sde-display-idp.dtsi b/display/scuba-sde-display-qrd.dtsi similarity index 100% rename from display/scuba-sde-display-idp.dtsi rename to display/scuba-sde-display-qrd.dtsi From 06d10749cca09775b69c78588f59d082c3f48c6b Mon Sep 17 00:00:00 2001 From: Wanghao Wei Date: Sun, 12 Dec 2021 13:38:23 +0800 Subject: [PATCH 9/9] ARM: dts: msm: add support panel ili9881c for bengal/scuba corret power supply, pwm settings and pin control. choice ili9881c as default panel. Change-Id: I526533ac76311d7f0f98cbcb92836ce7ece6c95e --- display/bengal-sde-display-qrd.dtsi | 16 +++++++++++++--- display/scuba-sde-display-qrd.dtsi | 16 +++++++++++++--- 2 files changed, 26 insertions(+), 6 deletions(-) diff --git a/display/bengal-sde-display-qrd.dtsi b/display/bengal-sde-display-qrd.dtsi index 20833de7e864..3c9f24f0a771 100644 --- a/display/bengal-sde-display-qrd.dtsi +++ b/display/bengal-sde-display-qrd.dtsi @@ -1,9 +1,19 @@ #include "bengal-sde-display.dtsi" &dsi_ili9881c_720p_video { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + pwms = <&pm6125_pwm 0 0>; + qcom,bl-pmic-pwm-period-usecs = <100>; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-reset-gpio = <&tlmm 97 0>; + qcom,platform-te-gpio = <&tlmm 40 0>; + qcom,platform-reset-gpio = <&ioexp21 2 0>; + qcom,platform-reset-gpio-always-on; + qcom,platform-bklight-en-gpio = <&ioexp21 3 0>; + qcom,platform-en-gpio = <&ioexp22 6 0>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_ili9881c_720p_video>; }; diff --git a/display/scuba-sde-display-qrd.dtsi b/display/scuba-sde-display-qrd.dtsi index af2fa18ab86f..f3b10fc36965 100644 --- a/display/scuba-sde-display-qrd.dtsi +++ b/display/scuba-sde-display-qrd.dtsi @@ -1,9 +1,19 @@ #include "scuba-sde-display.dtsi" &dsi_ili9881c_720p_video { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + pwms = <&pm2250_pwm3 0 0>; + qcom,bl-pmic-pwm-period-usecs = <100>; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-reset-gpio = <&tlmm 97 0>; + qcom,platform-te-gpio = <&tlmm 40 0>; + qcom,platform-reset-gpio = <&ioexp21 2 0>; + qcom,platform-reset-gpio-always-on; + qcom,platform-bklight-en-gpio = <&ioexp21 3 0>; + qcom,platform-en-gpio = <&ioexp22 6 0>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_ili9881c_720p_video>; };