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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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x86: cleanup tlbflush.h variants
Bring the tlbflush.h variants into sync to prepare merging and paravirt support. Signed-off-by: Thomas Gleixner <[email protected]> Signed-off-by: Ingo Molnar <[email protected]> Signed-off-by: Thomas Gleixner <[email protected]>
This commit is contained in:
Thomas Gleixner
Ingo Molnar
parent
1075cf7a95
commit
0b9c99b6f2
6 changed files with 128 additions and 100 deletions
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@ -163,6 +163,12 @@
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#define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLSH)
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#define cpu_has_bts boot_cpu_has(X86_FEATURE_BTS)
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#if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64)
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# define cpu_has_invlpg 1
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#else
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# define cpu_has_invlpg (boot_cpu_data.x86 > 3)
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#endif
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#ifdef CONFIG_X86_64
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#undef cpu_has_vme
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@ -183,6 +189,9 @@
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#undef cpu_has_centaur_mcr
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#define cpu_has_centaur_mcr 0
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#undef cpu_has_pge
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#define cpu_has_pge 1
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#endif /* CONFIG_X86_64 */
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#endif /* _ASM_X86_CPUFEATURE_H */
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@ -1,8 +1,11 @@
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#ifndef _I386_TLBFLUSH_H
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#define _I386_TLBFLUSH_H
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#ifndef _X86_TLBFLUSH_H
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#define _X86_TLBFLUSH_H
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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@ -12,62 +15,41 @@
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#define __flush_tlb_single(addr) __native_flush_tlb_single(addr)
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#endif
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#define __native_flush_tlb() \
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do { \
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unsigned int tmpreg; \
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\
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__asm__ __volatile__( \
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"movl %%cr3, %0; \n" \
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"movl %0, %%cr3; # flush TLB \n" \
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: "=r" (tmpreg) \
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:: "memory"); \
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} while (0)
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static inline void __native_flush_tlb(void)
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{
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write_cr3(read_cr3());
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}
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/*
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* Global pages have to be flushed a bit differently. Not a real
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* performance problem because this does not happen often.
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*/
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#define __native_flush_tlb_global() \
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do { \
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unsigned int tmpreg, cr4, cr4_orig; \
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\
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__asm__ __volatile__( \
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"movl %%cr4, %2; # turn off PGE \n" \
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"movl %2, %1; \n" \
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"andl %3, %1; \n" \
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"movl %1, %%cr4; \n" \
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"movl %%cr3, %0; \n" \
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"movl %0, %%cr3; # flush TLB \n" \
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"movl %2, %%cr4; # turn PGE back on \n" \
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: "=&r" (tmpreg), "=&r" (cr4), "=&r" (cr4_orig) \
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: "i" (~X86_CR4_PGE) \
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: "memory"); \
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} while (0)
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static inline void __native_flush_tlb_global(void)
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{
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unsigned long cr4 = read_cr4();
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#define __native_flush_tlb_single(addr) \
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__asm__ __volatile__("invlpg (%0)" ::"r" (addr) : "memory")
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/* clear PGE */
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write_cr4(cr4 & ~X86_CR4_PGE);
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/* write old PGE again and flush TLBs */
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write_cr4(cr4);
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}
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# define __flush_tlb_all() \
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do { \
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if (cpu_has_pge) \
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__flush_tlb_global(); \
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else \
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__flush_tlb(); \
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} while (0)
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static inline void __native_flush_tlb_single(unsigned long addr)
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{
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__asm__ __volatile__("invlpg (%0)" ::"r" (addr) : "memory");
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}
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#define cpu_has_invlpg (boot_cpu_data.x86 > 3)
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static inline void __flush_tlb_all(void)
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{
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if (cpu_has_pge)
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__flush_tlb_global();
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else
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__flush_tlb();
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}
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#ifdef CONFIG_X86_INVLPG
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# define __flush_tlb_one(addr) __flush_tlb_single(addr)
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#else
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# define __flush_tlb_one(addr) \
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do { \
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if (cpu_has_invlpg) \
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__flush_tlb_single(addr); \
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else \
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__flush_tlb(); \
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} while (0)
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#endif
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static inline void __flush_tlb_one(unsigned long addr)
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{
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if (cpu_has_invlpg)
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__flush_tlb_single(addr);
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else
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__flush_tlb();
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}
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/*
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* TLB flushing:
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@ -86,11 +68,8 @@
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#define TLB_FLUSH_ALL 0xffffffff
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#ifndef CONFIG_SMP
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#include <linux/sched.h>
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#define flush_tlb() __flush_tlb()
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#define flush_tlb_all() __flush_tlb_all()
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#define local_flush_tlb() __flush_tlb()
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@ -102,21 +81,22 @@ static inline void flush_tlb_mm(struct mm_struct *mm)
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}
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static inline void flush_tlb_page(struct vm_area_struct *vma,
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unsigned long addr)
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unsigned long addr)
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{
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if (vma->vm_mm == current->active_mm)
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__flush_tlb_one(addr);
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}
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static inline void flush_tlb_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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unsigned long start, unsigned long end)
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{
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if (vma->vm_mm == current->active_mm)
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__flush_tlb();
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}
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static inline void native_flush_tlb_others(const cpumask_t *cpumask,
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struct mm_struct *mm, unsigned long va)
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struct mm_struct *mm,
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unsigned long va)
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{
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}
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@ -124,8 +104,7 @@ static inline void native_flush_tlb_others(const cpumask_t *cpumask,
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#include <asm/smp.h>
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#define local_flush_tlb() \
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__flush_tlb()
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#define local_flush_tlb() __flush_tlb()
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extern void flush_tlb_all(void);
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extern void flush_tlb_current_task(void);
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@ -134,7 +113,8 @@ extern void flush_tlb_page(struct vm_area_struct *, unsigned long);
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#define flush_tlb() flush_tlb_current_task()
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static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long start, unsigned long end)
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static inline void flush_tlb_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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{
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flush_tlb_mm(vma->vm_mm);
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}
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@ -152,17 +132,17 @@ struct tlb_state
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char __cacheline_padding[L1_CACHE_BYTES-8];
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};
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DECLARE_PER_CPU(struct tlb_state, cpu_tlbstate);
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#endif /* SMP */
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#ifndef CONFIG_PARAVIRT
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#define flush_tlb_others(mask, mm, va) \
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native_flush_tlb_others(&mask, mm, va)
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#define flush_tlb_others(mask, mm, va) native_flush_tlb_others(&mask, mm, va)
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#endif
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static inline void flush_tlb_kernel_range(unsigned long start,
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unsigned long end)
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unsigned long end)
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{
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flush_tlb_all();
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}
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#endif /* _I386_TLBFLUSH_H */
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#endif /* _X86_TLBFLUSH_H */
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@ -1,26 +1,55 @@
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#ifndef _X8664_TLBFLUSH_H
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#define _X8664_TLBFLUSH_H
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#ifndef _X86_TLBFLUSH_H
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#define _X86_TLBFLUSH_H
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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static inline void __flush_tlb(void)
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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#else
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#define __flush_tlb() __native_flush_tlb()
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#define __flush_tlb_global() __native_flush_tlb_global()
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#define __flush_tlb_single(addr) __native_flush_tlb_single(addr)
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#endif
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static inline void __native_flush_tlb(void)
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{
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write_cr3(read_cr3());
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}
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static inline void __flush_tlb_all(void)
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static inline void __native_flush_tlb_global(void)
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{
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unsigned long cr4 = read_cr4();
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write_cr4(cr4 & ~X86_CR4_PGE); /* clear PGE */
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write_cr4(cr4); /* write old PGE again and flush TLBs */
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/* clear PGE */
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write_cr4(cr4 & ~X86_CR4_PGE);
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/* write old PGE again and flush TLBs */
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write_cr4(cr4);
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}
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#define __flush_tlb_one(addr) \
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__asm__ __volatile__("invlpg (%0)" :: "r" (addr) : "memory")
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static inline void __native_flush_tlb_single(unsigned long addr)
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{
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__asm__ __volatile__("invlpg (%0)" ::"r" (addr) : "memory");
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}
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static inline void __flush_tlb_all(void)
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{
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if (cpu_has_pge)
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__flush_tlb_global();
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else
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__flush_tlb();
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}
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static inline void __flush_tlb_one(unsigned long addr)
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{
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if (cpu_has_invlpg)
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__flush_tlb_single(addr);
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else
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__flush_tlb();
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}
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/*
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* TLB flushing:
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@ -37,6 +66,8 @@ static inline void __flush_tlb_all(void)
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* range a few INVLPGs in a row are a win.
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*/
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#define TLB_FLUSH_ALL -1ULL
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#ifndef CONFIG_SMP
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#define flush_tlb() __flush_tlb()
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@ -50,25 +81,30 @@ static inline void flush_tlb_mm(struct mm_struct *mm)
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}
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static inline void flush_tlb_page(struct vm_area_struct *vma,
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unsigned long addr)
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unsigned long addr)
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{
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if (vma->vm_mm == current->active_mm)
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__flush_tlb_one(addr);
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}
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static inline void flush_tlb_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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unsigned long start, unsigned long end)
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{
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if (vma->vm_mm == current->active_mm)
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__flush_tlb();
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}
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#else
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static inline void native_flush_tlb_others(const cpumask_t *cpumask,
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struct mm_struct *mm,
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unsigned long va)
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{
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}
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#else /* SMP */
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#include <asm/smp.h>
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#define local_flush_tlb() \
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__flush_tlb()
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#define local_flush_tlb() __flush_tlb()
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extern void flush_tlb_all(void);
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extern void flush_tlb_current_task(void);
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@ -77,24 +113,28 @@ extern void flush_tlb_page(struct vm_area_struct *, unsigned long);
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#define flush_tlb() flush_tlb_current_task()
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static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long start, unsigned long end)
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static inline void flush_tlb_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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{
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flush_tlb_mm(vma->vm_mm);
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}
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void native_flush_tlb_others(const cpumask_t *cpumask, struct mm_struct *mm,
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unsigned long va);
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#define TLBSTATE_OK 1
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#define TLBSTATE_LAZY 2
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/* Roughly an IPI every 20MB with 4k pages for freeing page table
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ranges. Cost is about 42k of memory for each CPU. */
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#define ARCH_FREE_PTE_NR 5350
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#endif /* SMP */
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#ifndef CONFIG_PARAVIRT
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#define flush_tlb_others(mask, mm, va) native_flush_tlb_others(&mask, mm, va)
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#endif
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static inline void flush_tlb_kernel_range(unsigned long start,
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unsigned long end)
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unsigned long end)
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{
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flush_tlb_all();
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}
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#endif /* _X8664_TLBFLUSH_H */
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#endif /* _X86_TLBFLUSH_H */
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