mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-29 11:11:45 -04:00
ARM: driver updates for 3.14
Updates of SoC-near drivers and other driver updates that makes more sense to
take through our tree.
The largest part of this is a conversion of device registration for some
renesas shmobile/sh devices over to use resources. This has required
coordination with the corresponding arch/sh changes, and we've agreed
to merge the arch/sh changes through our tree.
Added in this branch is support for Trusted Foundations secure firmware,
which is what is used on many of the commercial Nvidia Tegra products
that are in the market, including the Nvidia Shield. The code is local
to arch/arm at this time since it's uncertain whether it will be shared
with arm64 longer-term, if needed we will refactor later.
A couple of new RTC drivers used on ARM boards, merged through our tree
on request by the RTC maintainer.
... plus a bunch of smaller updates across the board, gpio conversions
for davinci, etc.
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Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM driver updates from Olof Johansson:
"Updates of SoC-near drivers and other driver updates that makes more
sense to take through our tree.
The largest part of this is a conversion of device registration for
some renesas shmobile/sh devices over to use resources. This has
required coordination with the corresponding arch/sh changes, and
we've agreed to merge the arch/sh changes through our tree.
Added in this branch is support for Trusted Foundations secure
firmware, which is what is used on many of the commercial Nvidia Tegra
products that are in the market, including the Nvidia Shield. The
code is local to arch/arm at this time since it's uncertain whether it
will be shared with arm64 longer-term, if needed we will refactor
later.
A couple of new RTC drivers used on ARM boards, merged through our
tree on request by the RTC maintainer.
... plus a bunch of smaller updates across the board, gpio conversions
for davinci, etc"
* tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (45 commits)
watchdog: davinci: rename platform driver to davinci-wdt
tty: serial: Limit msm_serial_hs driver to platforms that use it
mmc: msm_sdcc: Limit driver to platforms that use it
usb: phy: msm: Move mach dependent code to platform data
clk: versatile: fixup IM-PD1 clock implementation
clk: versatile: pass a name to ICST clock provider
ARM: integrator: pass parent IRQ to the SIC
irqchip: versatile FPGA: support cascaded interrupts from DT
gpio: davinci: don't create irq_domain in case of unbanked irqs
gpio: davinci: use chained_irq_enter/chained_irq_exit API
gpio: davinci: add OF support
gpio: davinci: remove unused variable intc_irq_num
gpio: davinci: convert to use irqdomain support.
gpio: introduce GPIO_DAVINCI kconfig option
gpio: davinci: get rid of DAVINCI_N_GPIO
gpio: davinci: use {readl|writel}_relaxed() instead of __raw_*
serial: sh-sci: Add OF support
serial: sh-sci: Add device tree bindings documentation
serial: sh-sci: Remove platform data mapbase and irqs fields
serial: sh-sci: Remove platform data scbrr_algo_id field
...
This commit is contained in:
Linus Torvalds
commit
0ba3307a8e
87 changed files with 2914 additions and 753 deletions
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|
@ -115,6 +115,13 @@ config GPIO_CLPS711X
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help
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Say yes here to support GPIO on CLPS711X SoCs.
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config GPIO_DAVINCI
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bool "TI Davinci/Keystone GPIO support"
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default y if ARCH_DAVINCI
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depends on ARM && (ARCH_DAVINCI || ARCH_KEYSTONE)
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help
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Say yes here to enable GPIO support for TI Davinci/Keystone SoCs.
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config GPIO_GENERIC_PLATFORM
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tristate "Generic memory-mapped GPIO controller support (MMIO platform device)"
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select GPIO_GENERIC
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|
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@ -22,7 +22,7 @@ obj-$(CONFIG_GPIO_CLPS711X) += gpio-clps711x.o
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obj-$(CONFIG_GPIO_CS5535) += gpio-cs5535.o
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obj-$(CONFIG_GPIO_DA9052) += gpio-da9052.o
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obj-$(CONFIG_GPIO_DA9055) += gpio-da9055.o
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obj-$(CONFIG_ARCH_DAVINCI) += gpio-davinci.o
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obj-$(CONFIG_GPIO_DAVINCI) += gpio-davinci.o
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obj-$(CONFIG_GPIO_EM) += gpio-em.o
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obj-$(CONFIG_GPIO_EP93XX) += gpio-ep93xx.o
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obj-$(CONFIG_GPIO_F7188X) += gpio-f7188x.o
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@ -16,8 +16,13 @@
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/platform_data/gpio-davinci.h>
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#include <linux/irqchip/chained_irq.h>
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struct davinci_gpio_regs {
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u32 dir;
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@ -82,14 +87,14 @@ static inline int __davinci_direction(struct gpio_chip *chip,
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u32 mask = 1 << offset;
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spin_lock_irqsave(&d->lock, flags);
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temp = __raw_readl(&g->dir);
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temp = readl_relaxed(&g->dir);
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if (out) {
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temp &= ~mask;
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__raw_writel(mask, value ? &g->set_data : &g->clr_data);
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writel_relaxed(mask, value ? &g->set_data : &g->clr_data);
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} else {
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temp |= mask;
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}
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__raw_writel(temp, &g->dir);
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writel_relaxed(temp, &g->dir);
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spin_unlock_irqrestore(&d->lock, flags);
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return 0;
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@ -118,7 +123,7 @@ static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
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struct davinci_gpio_controller *d = chip2controller(chip);
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struct davinci_gpio_regs __iomem *g = d->regs;
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return (1 << offset) & __raw_readl(&g->in_data);
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return (1 << offset) & readl_relaxed(&g->in_data);
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}
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/*
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@ -130,7 +135,41 @@ davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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struct davinci_gpio_controller *d = chip2controller(chip);
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struct davinci_gpio_regs __iomem *g = d->regs;
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__raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
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writel_relaxed((1 << offset), value ? &g->set_data : &g->clr_data);
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}
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static struct davinci_gpio_platform_data *
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davinci_gpio_get_pdata(struct platform_device *pdev)
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{
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struct device_node *dn = pdev->dev.of_node;
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struct davinci_gpio_platform_data *pdata;
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int ret;
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u32 val;
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if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
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return pdev->dev.platform_data;
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pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
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if (!pdata)
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return NULL;
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ret = of_property_read_u32(dn, "ti,ngpio", &val);
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if (ret)
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goto of_err;
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pdata->ngpio = val;
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ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val);
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if (ret)
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goto of_err;
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pdata->gpio_unbanked = val;
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return pdata;
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of_err:
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dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret);
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return NULL;
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}
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static int davinci_gpio_probe(struct platform_device *pdev)
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@ -143,12 +182,14 @@ static int davinci_gpio_probe(struct platform_device *pdev)
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struct device *dev = &pdev->dev;
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struct resource *res;
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pdata = dev->platform_data;
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pdata = davinci_gpio_get_pdata(pdev);
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if (!pdata) {
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dev_err(dev, "No platform data found\n");
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return -EINVAL;
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}
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dev->platform_data = pdata;
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/*
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* The gpio banks conceptually expose a segmented bitmap,
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* and "ngpio" is one more than the largest zero-based
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@ -160,8 +201,8 @@ static int davinci_gpio_probe(struct platform_device *pdev)
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return -EINVAL;
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}
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if (WARN_ON(DAVINCI_N_GPIO < ngpio))
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ngpio = DAVINCI_N_GPIO;
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if (WARN_ON(ARCH_NR_GPIOS < ngpio))
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ngpio = ARCH_NR_GPIOS;
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chips = devm_kzalloc(dev,
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ngpio * sizeof(struct davinci_gpio_controller),
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@ -194,6 +235,9 @@ static int davinci_gpio_probe(struct platform_device *pdev)
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if (chips[i].chip.ngpio > 32)
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chips[i].chip.ngpio = 32;
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#ifdef CONFIG_OF_GPIO
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chips[i].chip.of_node = dev->of_node;
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#endif
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spin_lock_init(&chips[i].lock);
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regs = gpio2regs(base);
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@ -227,8 +271,8 @@ static void gpio_irq_disable(struct irq_data *d)
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struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
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u32 mask = (u32) irq_data_get_irq_handler_data(d);
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__raw_writel(mask, &g->clr_falling);
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__raw_writel(mask, &g->clr_rising);
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writel_relaxed(mask, &g->clr_falling);
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writel_relaxed(mask, &g->clr_rising);
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}
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static void gpio_irq_enable(struct irq_data *d)
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@ -242,9 +286,9 @@ static void gpio_irq_enable(struct irq_data *d)
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status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
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if (status & IRQ_TYPE_EDGE_FALLING)
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__raw_writel(mask, &g->set_falling);
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writel_relaxed(mask, &g->set_falling);
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if (status & IRQ_TYPE_EDGE_RISING)
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__raw_writel(mask, &g->set_rising);
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writel_relaxed(mask, &g->set_rising);
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}
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static int gpio_irq_type(struct irq_data *d, unsigned trigger)
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@ -278,34 +322,28 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
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mask <<= 16;
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/* temporarily mask (level sensitive) parent IRQ */
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desc->irq_data.chip->irq_mask(&desc->irq_data);
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desc->irq_data.chip->irq_ack(&desc->irq_data);
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chained_irq_enter(irq_desc_get_chip(desc), desc);
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while (1) {
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u32 status;
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int n;
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int res;
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int bit;
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/* ack any irqs */
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status = __raw_readl(&g->intstat) & mask;
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status = readl_relaxed(&g->intstat) & mask;
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if (!status)
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break;
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__raw_writel(status, &g->intstat);
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writel_relaxed(status, &g->intstat);
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/* now demux them to the right lowlevel handler */
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n = d->irq_base;
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if (irq & 1) {
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n += 16;
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status >>= 16;
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}
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while (status) {
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res = ffs(status);
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n += res;
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generic_handle_irq(n - 1);
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status >>= res;
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bit = __ffs(status);
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status &= ~BIT(bit);
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generic_handle_irq(
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irq_find_mapping(d->irq_domain,
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d->chip.base + bit));
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}
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}
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desc->irq_data.chip->irq_unmask(&desc->irq_data);
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chained_irq_exit(irq_desc_get_chip(desc), desc);
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/* now it may re-trigger */
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}
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@ -313,10 +351,10 @@ static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
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{
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struct davinci_gpio_controller *d = chip2controller(chip);
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if (d->irq_base >= 0)
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return d->irq_base + offset;
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if (d->irq_domain)
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return irq_create_mapping(d->irq_domain, d->chip.base + offset);
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else
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return -ENODEV;
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return -ENXIO;
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}
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static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
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@ -346,14 +384,35 @@ static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
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if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
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return -EINVAL;
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__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
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writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
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? &g->set_falling : &g->clr_falling);
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__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
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writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING)
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? &g->set_rising : &g->clr_rising);
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return 0;
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}
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static int
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davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hw)
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{
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struct davinci_gpio_regs __iomem *g = gpio2regs(hw);
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irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq,
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"davinci_gpio");
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irq_set_irq_type(irq, IRQ_TYPE_NONE);
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irq_set_chip_data(irq, (__force void *)g);
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irq_set_handler_data(irq, (void *)__gpio_mask(hw));
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set_irq_flags(irq, IRQF_VALID);
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return 0;
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}
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|
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static const struct irq_domain_ops davinci_gpio_irq_ops = {
|
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.map = davinci_gpio_irq_map,
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.xlate = irq_domain_xlate_onetwocell,
|
||||
};
|
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|
||||
/*
|
||||
* NOTE: for suspend/resume, probably best to make a platform_device with
|
||||
* suspend_late/resume_resume calls hooking into results of the set_wake()
|
||||
|
|
@ -373,6 +432,7 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev)
|
|||
struct davinci_gpio_controller *chips = platform_get_drvdata(pdev);
|
||||
struct davinci_gpio_platform_data *pdata = dev->platform_data;
|
||||
struct davinci_gpio_regs __iomem *g;
|
||||
struct irq_domain *irq_domain = NULL;
|
||||
|
||||
ngpio = pdata->ngpio;
|
||||
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
||||
|
|
@ -396,6 +456,22 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev)
|
|||
}
|
||||
clk_prepare_enable(clk);
|
||||
|
||||
if (!pdata->gpio_unbanked) {
|
||||
irq = irq_alloc_descs(-1, 0, ngpio, 0);
|
||||
if (irq < 0) {
|
||||
dev_err(dev, "Couldn't allocate IRQ numbers\n");
|
||||
return irq;
|
||||
}
|
||||
|
||||
irq_domain = irq_domain_add_legacy(NULL, ngpio, irq, 0,
|
||||
&davinci_gpio_irq_ops,
|
||||
chips);
|
||||
if (!irq_domain) {
|
||||
dev_err(dev, "Couldn't register an IRQ domain\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Arrange gpio_to_irq() support, handling either direct IRQs or
|
||||
* banked IRQs. Having GPIOs in the first GPIO bank use direct
|
||||
|
|
@ -404,9 +480,7 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev)
|
|||
*/
|
||||
for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
|
||||
chips[bank].chip.to_irq = gpio_to_irq_banked;
|
||||
chips[bank].irq_base = pdata->gpio_unbanked
|
||||
? -EINVAL
|
||||
: (pdata->intc_irq_num + gpio);
|
||||
chips[bank].irq_domain = irq_domain;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -432,8 +506,8 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev)
|
|||
|
||||
/* default trigger: both edges */
|
||||
g = gpio2regs(0);
|
||||
__raw_writel(~0, &g->set_falling);
|
||||
__raw_writel(~0, &g->set_rising);
|
||||
writel_relaxed(~0, &g->set_falling);
|
||||
writel_relaxed(~0, &g->set_rising);
|
||||
|
||||
/* set the direct IRQs up to use that irqchip */
|
||||
for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++, irq++) {
|
||||
|
|
@ -449,15 +523,11 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev)
|
|||
* Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
|
||||
* then chain through our own handler.
|
||||
*/
|
||||
for (gpio = 0, irq = gpio_to_irq(0), bank = 0;
|
||||
gpio < ngpio;
|
||||
bank++, bank_irq++) {
|
||||
unsigned i;
|
||||
|
||||
for (gpio = 0, bank = 0; gpio < ngpio; bank++, bank_irq++, gpio += 16) {
|
||||
/* disabled by default, enabled only as needed */
|
||||
g = gpio2regs(gpio);
|
||||
__raw_writel(~0, &g->clr_falling);
|
||||
__raw_writel(~0, &g->clr_rising);
|
||||
writel_relaxed(~0, &g->clr_falling);
|
||||
writel_relaxed(~0, &g->clr_rising);
|
||||
|
||||
/* set up all irqs in this bank */
|
||||
irq_set_chained_handler(bank_irq, gpio_irq_handler);
|
||||
|
|
@ -469,14 +539,6 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev)
|
|||
*/
|
||||
irq_set_handler_data(bank_irq, &chips[gpio / 32]);
|
||||
|
||||
for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
|
||||
irq_set_chip(irq, &gpio_irqchip);
|
||||
irq_set_chip_data(irq, (__force void *)g);
|
||||
irq_set_handler_data(irq, (void *)__gpio_mask(gpio));
|
||||
irq_set_handler(irq, handle_simple_irq);
|
||||
set_irq_flags(irq, IRQF_VALID);
|
||||
}
|
||||
|
||||
binten |= BIT(bank);
|
||||
}
|
||||
|
||||
|
|
@ -485,18 +547,25 @@ done:
|
|||
* BINTEN -- per-bank interrupt enable. genirq would also let these
|
||||
* bits be set/cleared dynamically.
|
||||
*/
|
||||
__raw_writel(binten, gpio_base + BINTEN);
|
||||
|
||||
printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));
|
||||
writel_relaxed(binten, gpio_base + BINTEN);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if IS_ENABLED(CONFIG_OF)
|
||||
static const struct of_device_id davinci_gpio_ids[] = {
|
||||
{ .compatible = "ti,dm6441-gpio", },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, davinci_gpio_ids);
|
||||
#endif
|
||||
|
||||
static struct platform_driver davinci_gpio_driver = {
|
||||
.probe = davinci_gpio_probe,
|
||||
.driver = {
|
||||
.name = "davinci_gpio",
|
||||
.owner = THIS_MODULE,
|
||||
.name = "davinci_gpio",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = of_match_ptr(davinci_gpio_ids),
|
||||
},
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue