diff --git a/bindings/arm/msm/qcom,llcc.txt b/bindings/arm/msm/qcom,llcc.txt
index dc9c20cfec7b..2705ee9b1b5d 100644
--- a/bindings/arm/msm/qcom,llcc.txt
+++ b/bindings/arm/msm/qcom,llcc.txt
@@ -15,6 +15,7 @@ Properties:
 	            or "qcom,shima-llcc" or "qcom,sdxlemur-llcc"
 	            or "qcom,yupik-llcc" or "qcom,sm8150-llcc"
 		    or "qcom,sdmshrike-llcc" or "qcom,sm6150-llcc"
+		    or "qcom,direwolf-llcc"
 		    "qcom,llcc-v2" must be appended for V2 hardware.
 
 - reg:
diff --git a/qcom/direwolf-ion.dtsi b/qcom/direwolf-ion.dtsi
new file mode 100644
index 000000000000..fbd71987b0bc
--- /dev/null
+++ b/qcom/direwolf-ion.dtsi
@@ -0,0 +1,14 @@
+#include <dt-bindings/arm/msm/msm_ion_ids.h>
+
+&soc {
+	msm_ion: qcom,ion {
+		compatible = "qcom,msm-ion";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		system_heap: qcom,ion-heap@25 {
+			reg = <ION_SYSTEM_HEAP_ID>;
+			qcom,ion-heap-type = "MSM_SYSTEM";
+		};
+	};
+};
diff --git a/qcom/direwolf.dtsi b/qcom/direwolf.dtsi
index d2c3003d9a91..e7165829baef 100644
--- a/qcom/direwolf.dtsi
+++ b/qcom/direwolf.dtsi
@@ -1082,6 +1082,16 @@
 		#mbox-cells = <1>;
 	};
 
+	cache-controller@9200000 {
+		compatible = "qcom,direwolf-llcc", "qcom,llcc-v2";
+		reg = <0x9200000 0x1d0000> , <0x9600000 0x50000>;
+		reg-names = "llcc_base", "llcc_broadcast_base";
+		cap-based-alloc-and-pwr-collapse;
+		interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&aopcc QDSS_CLK>;
+		clock-names = "qdss_clk";
+	};
+
 	llcc_pmu: llcc-pmu@9095000 {
 		compatible = "qcom,llcc-pmu-ver2";
 		reg = <0x09095000 0x300>;
@@ -1482,6 +1492,7 @@
 #include "direwolf-regulators.dtsi"
 #include "direwolf-pm.dtsi"
 #include "direwolf-gdsc.dtsi"
+#include "direwolf-ion.dtsi"
 
 &gcc_emac0_gdsc {
 	status = "ok";