From 0bb91667f11f22ccf6fc9dd21bdbc0139520bb18 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Fri, 2 Apr 2021 17:20:48 +0530 Subject: [PATCH] regulator: qpnp-lcdb: Add support for some LCDB DT properties Add support for the following LCDB devicee tree properties: "qcom,high-p2-blank-time-ns" to control the higher clamp threshold for p2 minimum on time. "qcom,low-p2-blank-time-ns" to control the lower clamp threshold for p2 minimum on time. "qcom,mpc-current-thr-ma" to control the mpc threshold for inductor current after start up is done. Change-Id: Iabe2cc2c9913f433dd55d952a267f94ce0682f0e Signed-off-by: Jishnu Prakash --- drivers/regulator/qpnp-lcdb-regulator.c | 109 ++++++++++++++++++++++++ 1 file changed, 109 insertions(+) diff --git a/drivers/regulator/qpnp-lcdb-regulator.c b/drivers/regulator/qpnp-lcdb-regulator.c index 4c4f008c7de4..a26d59cb1246 100644 --- a/drivers/regulator/qpnp-lcdb-regulator.c +++ b/drivers/regulator/qpnp-lcdb-regulator.c @@ -99,6 +99,11 @@ #define NFET_SW_SIZE_SHIFT 2 #define PFET_SW_SIZE_MASK GENMASK(1, 0) +#define PM7325B_LCDB_P2_BLANK_TIMER_REG 0x54 +#define HIGH_P2_BLK_SEL_MASK GENMASK(6, 4) +#define HIGH_P2_BLK_SEL_SHIFT 4 +#define LOW_P2_BLK_SEL_MASK GENMASK(2, 0) + #define LCDB_BST_VREG_OK_CTL_REG 0x55 #define BST_VREG_OK_DEB_MASK GENMASK(1, 0) @@ -129,6 +134,12 @@ #define EN_TOUCH_WAKE_BIT BIT(3) #define DIS_SCP_BIT BIT(0) +#define PM7325B_LCDB_MPC_CTL_REG 0x60 +#define MPC_NCP_SD_SEL_MASK GENMASK(2, 0) +#define MPC_CURRENT_MIN 160 +#define MPC_CURRENT_MAX 440 +#define MPC_CURRENT_STEP 40 + #define LCDB_PFM_CTL_REG 0x62 #define EN_PFM_BIT BIT(7) #define BYP_BST_SOFT_START_COMP_BIT BIT(0) @@ -278,6 +289,9 @@ struct qpnp_lcdb { int min_voltage_mv; int max_voltage_mv; int pwrup_config; + int high_p2_blk_ns; + int low_p2_blk_ns; + int mpc_current_thr_ma; bool ncp_symmetry; /* TTW params */ @@ -421,6 +435,17 @@ static const u32 pm7325b_ldo_ilim_ma[] = { 840, }; +static const u32 pm7325b_p2_blk_ns[] = { + 40, + 69, + 99, + 129, + 159, + 189, + 220, + 250, +}; + #define SETTING(_id, _sec_access, _valid) \ [_id] = { \ .address = _id##_REG, \ @@ -2431,6 +2456,33 @@ static int qpnp_lcdb_hw_init(struct qpnp_lcdb *lcdb) return rc; } + if (lcdb->high_p2_blk_ns != -EINVAL) { + rc = qpnp_lcdb_masked_write(lcdb, lcdb->base + + PM7325B_LCDB_P2_BLANK_TIMER_REG, + HIGH_P2_BLK_SEL_MASK, + lcdb->high_p2_blk_ns << HIGH_P2_BLK_SEL_SHIFT); + if (rc < 0) + return rc; + } + + if (lcdb->low_p2_blk_ns != -EINVAL) { + rc = qpnp_lcdb_masked_write(lcdb, lcdb->base + + PM7325B_LCDB_P2_BLANK_TIMER_REG, + LOW_P2_BLK_SEL_MASK, + lcdb->low_p2_blk_ns); + if (rc < 0) + return rc; + } + + if (lcdb->mpc_current_thr_ma != -EINVAL) { + rc = qpnp_lcdb_masked_write(lcdb, lcdb->base + + PM7325B_LCDB_MPC_CTL_REG, + MPC_NCP_SD_SEL_MASK, + lcdb->mpc_current_thr_ma); + if (rc < 0) + return rc; + } + if (lcdb->ncp_symmetry) { rc = qpnp_lcdb_masked_write(lcdb, lcdb->base + LCDB_NCP_OUTPUT_VOLTAGE_REG, @@ -2514,6 +2566,39 @@ static int qpnp_lcdb_pwrup_dn_delay(int val, int *delay) return 0; } +static int qpnp_lcdb_p2_blk_time(int val, int *time) +{ + int i; + + if (!is_between(val, pm7325b_p2_blk_ns[0], pm7325b_p2_blk_ns[7])) { + pr_err("Invalid P2_BLK_TIME val %d (min=%d max=%d)\n", + val, pm7325b_p2_blk_ns[0], pm7325b_p2_blk_ns[7]); + return -EINVAL; + } + + for (i = 0; i < ARRAY_SIZE(pm7325b_p2_blk_ns); i++) { + if (val == pm7325b_p2_blk_ns[i]) { + *time = i; + break; + } + } + + return 0; +} + +static int qpnp_lcdb_mpc_current(int val, int *cur) +{ + if (!is_between(val, MPC_CURRENT_MIN, MPC_CURRENT_MAX)) { + pr_err("Invalid MPC_CURRENT val %d (min=%d max=%d)\n", + val, MPC_CURRENT_MIN, MPC_CURRENT_MAX); + return -EINVAL; + } + + *cur = (val - MPC_CURRENT_MIN) / MPC_CURRENT_STEP; + + return 0; +} + static int qpnp_lcdb_parse_dt(struct qpnp_lcdb *lcdb) { int rc = 0; @@ -2569,6 +2654,9 @@ static int qpnp_lcdb_parse_dt(struct qpnp_lcdb *lcdb) lcdb->pwrdn_delay_ms = -EINVAL; lcdb->pwrup_delay_ms = -EINVAL; lcdb->pwrup_config = -EINVAL; + lcdb->high_p2_blk_ns = -EINVAL; + lcdb->low_p2_blk_ns = -EINVAL; + lcdb->mpc_current_thr_ma = -EINVAL; rc = of_property_read_u32(node, "qcom,pwrdn-delay-ms", &tmp); if (!rc) { rc = qpnp_lcdb_pwrup_dn_delay(tmp, &lcdb->pwrdn_delay_ms); @@ -2590,6 +2678,27 @@ static int qpnp_lcdb_parse_dt(struct qpnp_lcdb *lcdb) return -EINVAL; } + rc = of_property_read_u32(node, "qcom,high-p2-blank-time-ns", &tmp); + if (!rc) { + rc = qpnp_lcdb_p2_blk_time(tmp, &lcdb->high_p2_blk_ns); + if (rc < 0) + return rc; + } + + rc = of_property_read_u32(node, "qcom,low-p2-blank-time-ns", &tmp); + if (!rc) { + rc = qpnp_lcdb_p2_blk_time(tmp, &lcdb->low_p2_blk_ns); + if (rc < 0) + return rc; + } + + rc = of_property_read_u32(node, "qcom,mpc-current-thr-ma", &tmp); + if (!rc) { + rc = qpnp_lcdb_mpc_current(tmp, &lcdb->mpc_current_thr_ma); + if (rc < 0) + return rc; + } + return 0; }