From 0bd22990a564dd5b7da3c8087a8f91ea663ba253 Mon Sep 17 00:00:00 2001
From: Charan Teja Kalla <charante@qti.qualcomm.com>
Date: Tue, 18 Aug 2020 17:55:30 +0530
Subject: [PATCH] ARM: dts: msm: add smmu nodes on yupik

Add SMMU device tree nodes, which is used by the clients for virtual to
physical address transaltions, on yupik.

Change-Id: Ia88dc0e18b530e364314f8468022519dd5dcf5e2
---
 qcom/msm-arm-smmu-yupik.dtsi | 246 +++++++++++++++++++++++++++++++++++
 qcom/yupik.dtsi              |   5 +
 2 files changed, 251 insertions(+)
 create mode 100644 qcom/msm-arm-smmu-yupik.dtsi

diff --git a/qcom/msm-arm-smmu-yupik.dtsi b/qcom/msm-arm-smmu-yupik.dtsi
new file mode 100644
index 000000000000..22ee8245eb6e
--- /dev/null
+++ b/qcom/msm-arm-smmu-yupik.dtsi
@@ -0,0 +1,246 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+&soc {
+	kgsl_smmu: kgsl-smmu@3da0000 {
+		status = "disabled";
+		compatible = "qcom,qsmmu-v500";
+		reg = <0x3da0000 0x20000>,
+			<0x3dd6000 0x20>;
+		reg-names = "base", "tcu-base";
+		#iommu-cells = <2>;
+		qcom,skip-init;
+		qcom,use-3-lvl-tables;
+		#global-interrupts = <2>;
+		#size-cells = <1>;
+		#address-cells = <1>;
+		ranges;
+		dma-coherent;
+		interrupts =	<GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
+
+		gfx_0_tbu: gfx_0_tbu@3dd9000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x3dd9000 0x1000>,
+				<0x3dd6200 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x0 0x400>;
+		};
+
+		gfx_1_tbu: gfx_1_tbu@3ddd000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x3ddd000 0x1000>,
+				<0x3dd6208 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x400 0x400>;
+		};
+
+	};
+
+	apps_smmu: apps-smmu@15000000 {
+		compatible = "qcom,qsmmu-v500";
+		reg = <0x15000000 0x100000>,
+			<0x151da000 0x20>;
+		reg-names = "base", "tcu-base";
+		#iommu-cells = <2>;
+		qcom,skip-init;
+		qcom,use-3-lvl-tables;
+		#global-interrupts = <2>;
+		#size-cells = <1>;
+		#address-cells = <1>;
+		ranges;
+		dma-coherent;
+		interrupts =	<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
+
+		anoc_1_tbu: anoc_1_tbu@151dd000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151dd000 0x1000>,
+				<0x151da200 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x0 0x400>;
+		};
+
+		anoc_2_tbu: anoc_2_tbu@151e1000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151e1000 0x1000>,
+				<0x151da208 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x400 0x400>;
+		};
+
+		mnoc_hf_0_tbu: mnoc_hf_0_tbu@151e5000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151e5000 0x1000>,
+				<0x151da210 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x800 0x400>;
+		};
+
+		mnoc_hf_1_tbu: mnoc_hf_1_tbu@151e9000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151e9000 0x1000>,
+				<0x151da218 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0xc00 0x400>;
+		};
+
+		compute_dsp_1_tbu: compute_dsp_1_tbu@151ed000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151ed000 0x1000>,
+				<0x151da220 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x1000 0x400>;
+		};
+
+		compute_dsp_0_tbu: compute_dsp_0_tbu@151f1000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151f1000 0x1000>,
+				<0x151da228 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x1400 0x400>;
+		};
+
+		adsp_tbu: adsp_tbu@151f5000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151f5000 0x1000>,
+				<0x151da230 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x1800 0x400>;
+		};
+
+		anoc_1_pcie_tbu: anoc_1_pcie_tbu@151f9000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151f9000 0x1000>,
+				<0x151da238 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x1c00 0x400>;
+		};
+
+		mnoc_sf_0_tbu: mnoc_sf_0_tbu@151fd000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151fd000 0x1000>,
+				<0x151da240 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x2000 0x400>;
+		};
+	};
+
+	kgsl_iommu_test_device {
+		status = "disabled";
+		compatible = "iommu-debug-test";
+		iommus = <&kgsl_smmu 0x7 0>;
+		qcom,iommu-dma = "disabled";
+	};
+
+	kgsl_iommu_coherent_test_device {
+		status = "disabled";
+		compatible = "iommu-debug-test";
+		iommus = <&kgsl_smmu 0x407 0>;
+		qcom,iommu-dma = "disabled";
+		dma-coherent;
+	};
+
+	apps_iommu_test_device {
+		compatible = "iommu-debug-test";
+		iommus = <&apps_smmu 0x0 0>;
+		qcom,iommu-dma = "disabled";
+	};
+
+	apps_iommu_coherent_test_device {
+		compatible = "iommu-debug-test";
+		iommus = <&apps_smmu 0x1 0>;
+		qcom,iommu-dma = "disabled";
+		dma-coherent;
+	};
+};
+
diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi
index c07780c7eed8..f76e4684ff16 100644
--- a/qcom/yupik.dtsi
+++ b/qcom/yupik.dtsi
@@ -1140,6 +1140,10 @@
 		mboxes = <&qmp_aop 0>;
 		mbox-names = "aop";
 	};
+
+	qcom-secure-buffer {
+		compatible = "qcom,secure-buffer";
+	};
 };
 
 #include "shima-gdsc.dtsi"
@@ -1264,3 +1268,4 @@
 };
 
 #include "yupik-usb.dtsi"
+#include "msm-arm-smmu-yupik.dtsi"