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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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Merge "iommu/arm-smmu: Add reset implementation hook"
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qctecmdr
Gerrit - the friendly Code Review server
commit
0bd47772b8
3 changed files with 91 additions and 47 deletions
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@ -4,6 +4,7 @@
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#define pr_fmt(fmt) "arm-smmu: " fmt
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#include <linux/bitfield.h>
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#include <linux/of.h>
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#include "arm-smmu.h"
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@ -47,8 +48,90 @@ const struct arm_smmu_impl calxeda_impl = {
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};
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static int cavium_cfg_probe(struct arm_smmu_device *smmu)
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{
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static atomic_t context_count = ATOMIC_INIT(0);
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/*
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* Cavium CN88xx erratum #27704.
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* Ensure ASID and VMID allocation is unique across all SMMUs in
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* the system.
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*/
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smmu->cavium_id_base = atomic_fetch_add(smmu->num_context_banks,
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&context_count);
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dev_notice(smmu->dev, "\tenabling workaround for Cavium erratum 27704\n");
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return 0;
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}
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const struct arm_smmu_impl cavium_impl = {
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.cfg_probe = cavium_cfg_probe,
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};
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#define ARM_MMU500_ACTLR_CPRE (1 << 1)
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#define ARM_MMU500_ACR_CACHE_LOCK (1 << 26)
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#define ARM_MMU500_ACR_S2CRB_TLBEN (1 << 10)
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#define ARM_MMU500_ACR_SMTNMB_TLBEN (1 << 8)
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static int arm_mmu500_reset(struct arm_smmu_device *smmu)
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{
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u32 reg, major;
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int i;
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/*
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* On MMU-500 r2p0 onwards we need to clear ACR.CACHE_LOCK before
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* writes to the context bank ACTLRs will stick. And we just hope that
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* Secure has also cleared SACR.CACHE_LOCK for this to take effect...
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*/
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reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_ID7);
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major = FIELD_GET(ID7_MAJOR, reg);
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reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sACR);
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if (major >= 2)
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reg &= ~ARM_MMU500_ACR_CACHE_LOCK;
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/*
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* Allow unmatched Stream IDs to allocate bypass
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* TLB entries for reduced latency.
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*/
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reg |= ARM_MMU500_ACR_SMTNMB_TLBEN | ARM_MMU500_ACR_S2CRB_TLBEN;
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arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sACR, reg);
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/*
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* Disable MMU-500's not-particularly-beneficial next-page
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* prefetcher for the sake of errata #841119 and #826419.
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*/
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for (i = 0; i < smmu->num_context_banks; ++i) {
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reg = arm_smmu_cb_read(smmu, i, ARM_SMMU_CB_ACTLR);
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reg &= ~ARM_MMU500_ACTLR_CPRE;
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arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_ACTLR, reg);
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}
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return 0;
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}
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const struct arm_smmu_impl arm_mmu500_impl = {
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.reset = arm_mmu500_reset,
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};
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struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu)
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{
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/*
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* We will inevitably have to combine model-specific implementation
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* quirks with platform-specific integration quirks, but everything
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* we currently support happens to work out as straightforward
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* mutually-exclusive assignments.
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*/
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switch (smmu->model) {
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case ARM_MMU500:
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smmu->impl = &arm_mmu500_impl;
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break;
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case CAVIUM_SMMUV2:
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smmu->impl = &cavium_impl;
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break;
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default:
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break;
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}
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if (of_property_read_bool(smmu->dev->of_node,
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"calxeda,smmu-secure-config-access"))
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smmu->impl = &calxeda_impl;
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@ -66,11 +66,7 @@
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*/
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#define QCOM_DUMMY_VAL -1
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#define ARM_MMU500_ACTLR_CPRE (1 << 1)
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#define ARM_MMU500_ACR_CACHE_LOCK (1 << 26)
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#define ARM_MMU500_ACR_S2CRB_TLBEN (1 << 10)
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#define ARM_MMU500_ACR_SMTNMB_TLBEN (1 << 8)
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#define TLB_LOOP_TIMEOUT 500000 /* 500ms */
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#define TLB_SPIN_COUNT 10
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@ -215,8 +211,6 @@ struct arm_smmu_domain {
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struct msm_iommu_domain domain;
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};
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static atomic_t cavium_smmu_context_count = ATOMIC_INIT(0);
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static bool using_legacy_binding, using_generic_binding;
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struct arm_smmu_option_prop {
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@ -3865,40 +3859,11 @@ static struct msm_iommu_ops arm_smmu_ops = {
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static void arm_smmu_context_bank_reset(struct arm_smmu_device *smmu)
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{
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int i;
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u32 reg, major;
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if (smmu->model == ARM_MMU500) {
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/*
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* Before clearing ARM_MMU500_ACTLR_CPRE, need to
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* clear CACHE_LOCK bit of ACR first. And, CACHE_LOCK
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* bit is only present in MMU-500r2 onwards.
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*/
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reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_ID7);
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major = FIELD_GET(ID7_MAJOR, reg);
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reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sACR);
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if (major >= 2)
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reg &= ~ARM_MMU500_ACR_CACHE_LOCK;
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/*
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* Allow unmatched Stream IDs to allocate bypass
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* TLB entries for reduced latency.
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*/
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reg |= ARM_MMU500_ACR_SMTNMB_TLBEN;
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arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sACR, reg);
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}
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/* Make sure all context banks are disabled and clear CB_FSR */
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for (i = 0; i < smmu->num_context_banks; ++i) {
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arm_smmu_write_context_bank(smmu, i, 0);
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arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_FSR, FSR_FAULT);
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/*
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* Disable MMU-500's not-particularly-beneficial next-page
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* prefetcher for the sake of errata #841119 and #826419.
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*/
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if (smmu->model == ARM_MMU500) {
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reg = arm_smmu_cb_read(smmu, i, ARM_SMMU_CB_ACTLR);
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reg &= ~ARM_MMU500_ACTLR_CPRE;
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arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_ACTLR, reg);
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}
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}
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}
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@ -3957,6 +3922,9 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
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reg &= ~(sCR0_SHCFG_MASK << sCR0_SHCFG_SHIFT);
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reg |= sCR0_SHCFG_NSH << sCR0_SHCFG_SHIFT;
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if (smmu->impl && smmu->impl->reset)
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smmu->impl->reset(smmu);
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/* Push the button */
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arm_smmu_tlb_sync_global(smmu);
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wmb();
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@ -4392,18 +4360,6 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
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}
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dev_dbg(smmu->dev, "\t%u context banks (%u stage-2 only)\n",
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smmu->num_context_banks, smmu->num_s2_context_banks);
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/*
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* Cavium CN88xx erratum #27704.
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* Ensure ASID and VMID allocation is unique across all SMMUs in
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* the system.
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*/
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if (smmu->model == CAVIUM_SMMUV2) {
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smmu->cavium_id_base =
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atomic_add_return(smmu->num_context_banks,
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&cavium_smmu_context_count);
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smmu->cavium_id_base -= smmu->num_context_banks;
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dev_notice(smmu->dev, "\tenabling workaround for Cavium erratum 27704\n");
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}
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smmu->cbs = devm_kcalloc(smmu->dev, smmu->num_context_banks,
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sizeof(*smmu->cbs), GFP_KERNEL);
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if (!smmu->cbs)
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@ -4472,6 +4428,9 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
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dev_dbg(smmu->dev, "\tStage-2: %lu-bit IPA -> %lu-bit PA\n",
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smmu->ipa_size, smmu->pa_size);
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if (smmu->impl && smmu->impl->cfg_probe)
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return smmu->impl->cfg_probe(smmu);
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return 0;
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}
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@ -373,6 +373,8 @@ struct arm_smmu_impl {
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u64 (*read_reg64)(struct arm_smmu_device *smmu, int page, int offset);
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void (*write_reg64)(struct arm_smmu_device *smmu, int page, int offset,
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u64 val);
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int (*cfg_probe)(struct arm_smmu_device *smmu);
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int (*reset)(struct arm_smmu_device *smmu);
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};
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static inline void __iomem *arm_smmu_page(struct arm_smmu_device *smmu, int n)
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