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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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ARM SoC driver specific changes
These changes are all driver specific and cross over between arm-soc contents and some other subsystem, in these cases cpufreq, crypto, dma, pinctrl, mailbox and usb, and the subsystem owners agreed to have these changes merged through arm-soc. As we proceed to untangle the dependencies between platform code and driver code, the amount of changes in this category is fortunately shrinking, for 3.11 we have 16 branches here and 101 non-merge changesets, the majority of which are for the stedma40 dma engine driver used in the ux500 platform. Cleaning up that code touches multiple subsystems, but gets rid of the dependency in the end. The mailbox code moved out from mach-omap2 to drivers/mailbox is an intermediate step and is still omap specific at the moment. Patches exist to generalize the subsystem and add other drivers with the same API, but those did not make it for 3.11. Conflicts: * In cpu-db8500.c results from the removal of the u8500_of_init_devices function in combination with the split of u8500_auxdata_lookup. * In arch/arm/mach-omap2/devices.c, the includes got reshuffled. we need to keep linux/wl12xx.h and linux/platform_data/mailbox-omap.h. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIVAwUAUdLnomCrR//JCVInAQJI/A/9FydsQa9sdnzLFgcdX5BeRRwkXLfDifCM zDTfUBo+LriKOs7QHblmDg1MnY1UMB2IfrdHD0FsjK7WbZ/91EMAGDPYcI7Fu4+u pGStxwWi2v+oCT1jjeOkCPT7hdCqogsSpybYq8itSb+zdvdOi6U35dWEKz8xGqz4 vTL9gTZbJP0kowkjIcaryk7FIj7BTIvMCW8n55JZEkDe0BuSJGYn5c3Mntut12ZK 5xM2PeNe2sd3dIdA6XbM2ye/XmYa8xY8Qu4/ijxfH1gnJLvz9Unp96nRXpEbIeMb BH2Sro8dxsMCaweIQhSRKGnUWMYO/Rh7/+5EqzJ163Ezthx9nvHXJY2ndWuD7uM1 IcGrMxLtqP22TEMtZAVEATDp/5ymxEo5GM+eayUojQDn213wOJjRs5xz5IBsH4KM 8CM/gpadWmLjWku72yEV4lryLcdS0NVQzpTnEbILEGOU4u7qJtxRAp7x7tWBtFg8 4m/eWcSVk/U2SYbXmQHsfukuWgKY0cnZbctPcdnaqXwTP7toJEAK3gxoMtWh49Jq 2M2PVFyFejaaq5b/71wAJ7ePYw56H0N/F3RsGpPE55AY15++gSoQ+3t2Si68hDw8 NtyJMkQYpTvtqJbHXWpQQ3Zfs7pDBe01WDV7i+m4JTNggxUDaO/t1Fqp+fEksm4J r+luEf5Gcgk= =mJsI -----END PGP SIGNATURE----- Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver specific changes from Arnd Bergmann: "These changes are all driver specific and cross over between arm-soc contents and some other subsystem, in these cases cpufreq, crypto, dma, pinctrl, mailbox and usb, and the subsystem owners agreed to have these changes merged through arm-soc. As we proceed to untangle the dependencies between platform code and driver code, the amount of changes in this category is fortunately shrinking, for 3.11 we have 16 branches here and 101 non-merge changesets, the majority of which are for the stedma40 dma engine driver used in the ux500 platform. Cleaning up that code touches multiple subsystems, but gets rid of the dependency in the end. The mailbox code moved out from mach-omap2 to drivers/mailbox is an intermediate step and is still omap specific at the moment. Patches exist to generalize the subsystem and add other drivers with the same API, but those did not make it for 3.11." * tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (101 commits) crypto: ux500: use dmaengine_submit API crypto: ux500: use dmaengine_prep_slave_sg API crypto: ux500: use dmaengine_device_control API crypto: ux500/crypt: add missing __iomem qualifiers crypto: ux500/hash: add missing static qualifiers crypto: ux500/hash: use readl on iomem addresses dmaengine: ste_dma40: Declare memcpy config as static ARM: ux500: Remove mop500_snowball_ethernet_clock_enable() ARM: ux500: Correct the EN_3v3 regulator's on/off GPIO ARM: ux500: Provide a AB8500 GPIO Device Tree node gpio: rcar: fix gpio_rcar_of_table gpio-rcar: Remove #ifdef CONFIG_OF around OF-specific sections gpio-rcar: Reference core gpio documentation in the DT bindings clk: exynos5250: Add enum entries for divider clock of i2s1 and i2s2 ARM: dts: Update Samsung I2S documentation ARM: dts: add clock provider information for i2s controllers in Exynos5250 ARM: dts: add Exynos audio subsystem clock controller node clk: samsung: register audio subsystem clocks using common clock framework ARM: dts: use #include for all device trees for Samsung pinctrl: s3c24xx: use correct header for chained_irq functions ...
This commit is contained in:
Linus Torvalds
commit
0bf6a210a4
112 changed files with 3168 additions and 1651 deletions
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@ -6,3 +6,4 @@ obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
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obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
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obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
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obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
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obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
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133
drivers/clk/samsung/clk-exynos-audss.c
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133
drivers/clk/samsung/clk-exynos-audss.c
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@ -0,0 +1,133 @@
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/*
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* Copyright (c) 2013 Samsung Electronics Co., Ltd.
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* Author: Padmavathi Venna <padma.v@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Common Clock Framework support for Audio Subsystem Clock Controller.
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*/
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#include <linux/clkdev.h>
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#include <linux/io.h>
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#include <linux/clk-provider.h>
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#include <linux/of_address.h>
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#include <linux/syscore_ops.h>
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#include <dt-bindings/clk/exynos-audss-clk.h>
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static DEFINE_SPINLOCK(lock);
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static struct clk **clk_table;
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static void __iomem *reg_base;
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static struct clk_onecell_data clk_data;
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#define ASS_CLK_SRC 0x0
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#define ASS_CLK_DIV 0x4
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#define ASS_CLK_GATE 0x8
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static unsigned long reg_save[][2] = {
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{ASS_CLK_SRC, 0},
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{ASS_CLK_DIV, 0},
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{ASS_CLK_GATE, 0},
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};
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/* list of all parent clock list */
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static const char *mout_audss_p[] = { "fin_pll", "fout_epll" };
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static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" };
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#ifdef CONFIG_PM_SLEEP
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static int exynos_audss_clk_suspend(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(reg_save); i++)
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reg_save[i][1] = readl(reg_base + reg_save[i][0]);
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return 0;
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}
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static void exynos_audss_clk_resume(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(reg_save); i++)
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writel(reg_save[i][1], reg_base + reg_save[i][0]);
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}
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static struct syscore_ops exynos_audss_clk_syscore_ops = {
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.suspend = exynos_audss_clk_suspend,
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.resume = exynos_audss_clk_resume,
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};
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#endif /* CONFIG_PM_SLEEP */
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/* register exynos_audss clocks */
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void __init exynos_audss_clk_init(struct device_node *np)
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{
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reg_base = of_iomap(np, 0);
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if (!reg_base) {
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pr_err("%s: failed to map audss registers\n", __func__);
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return;
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}
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clk_table = kzalloc(sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
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GFP_KERNEL);
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if (!clk_table) {
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pr_err("%s: could not allocate clk lookup table\n", __func__);
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return;
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}
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clk_data.clks = clk_table;
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clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
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of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
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clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
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mout_audss_p, ARRAY_SIZE(mout_audss_p), 0,
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reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
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clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s",
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mout_i2s_p, ARRAY_SIZE(mout_i2s_p), 0,
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reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
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clk_table[EXYNOS_DOUT_SRP] = clk_register_divider(NULL, "dout_srp",
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"mout_audss", 0, reg_base + ASS_CLK_DIV, 0, 4,
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0, &lock);
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clk_table[EXYNOS_DOUT_AUD_BUS] = clk_register_divider(NULL,
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"dout_aud_bus", "dout_srp", 0,
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reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
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clk_table[EXYNOS_DOUT_I2S] = clk_register_divider(NULL, "dout_i2s",
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"mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0,
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&lock);
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clk_table[EXYNOS_SRP_CLK] = clk_register_gate(NULL, "srp_clk",
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"dout_srp", CLK_SET_RATE_PARENT,
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reg_base + ASS_CLK_GATE, 0, 0, &lock);
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clk_table[EXYNOS_I2S_BUS] = clk_register_gate(NULL, "i2s_bus",
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"dout_aud_bus", CLK_SET_RATE_PARENT,
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reg_base + ASS_CLK_GATE, 2, 0, &lock);
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clk_table[EXYNOS_SCLK_I2S] = clk_register_gate(NULL, "sclk_i2s",
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"dout_i2s", CLK_SET_RATE_PARENT,
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reg_base + ASS_CLK_GATE, 3, 0, &lock);
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clk_table[EXYNOS_PCM_BUS] = clk_register_gate(NULL, "pcm_bus",
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"sclk_pcm", CLK_SET_RATE_PARENT,
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reg_base + ASS_CLK_GATE, 4, 0, &lock);
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clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm",
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"div_pcm0", CLK_SET_RATE_PARENT,
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reg_base + ASS_CLK_GATE, 5, 0, &lock);
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#ifdef CONFIG_PM_SLEEP
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register_syscore_ops(&exynos_audss_clk_syscore_ops);
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#endif
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pr_info("Exynos: Audss: clock setup completed\n");
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}
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CLK_OF_DECLARE(exynos4210_audss_clk, "samsung,exynos4210-audss-clock",
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exynos_audss_clk_init);
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CLK_OF_DECLARE(exynos5250_audss_clk, "samsung,exynos5250-audss-clock",
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exynos_audss_clk_init);
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@ -87,6 +87,7 @@ enum exynos5250_clks {
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sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_sata, sclk_usb3,
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sclk_jpeg, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_pwm,
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sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
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div_i2s1, div_i2s2,
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/* gate clocks */
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gscl0 = 256, gscl1, gscl2, gscl3, gscl_wa, gscl_wb, smmu_gscl0,
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@ -291,8 +292,8 @@ struct samsung_div_clock exynos5250_div_clks[] __initdata = {
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DIV(none, "div_pcm1", "sclk_audio1", DIV_PERIC4, 4, 8),
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DIV(none, "div_audio2", "mout_audio2", DIV_PERIC4, 16, 4),
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DIV(none, "div_pcm2", "sclk_audio2", DIV_PERIC4, 20, 8),
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DIV(none, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6),
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DIV(none, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6),
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DIV(div_i2s1, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6),
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DIV(div_i2s2, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6),
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DIV(sclk_pixel, "div_hdmi_pixel", "sclk_vpll", DIV_DISP1_0, 28, 4),
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DIV_A(none, "armclk", "div_arm", DIV_CPU0, 28, 3, "armclk"),
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DIV_F(none, "div_mipi1_pre", "div_mipi1",
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