mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-29 03:01:39 -04:00
Merge branches 'iommu/fixes', 'x86/vt-d', 'x86/amd', 'ppc/pamu', 'core' and 'arm/tegra' into next
This commit is contained in:
Joerg Roedel
commit
0c4513be3d
847 changed files with 9775 additions and 5651 deletions
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@ -130,7 +130,7 @@ config IRQ_REMAP
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# OMAP IOMMU support
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config OMAP_IOMMU
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bool "OMAP IOMMU Support"
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depends on ARCH_OMAP
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depends on ARCH_OMAP2PLUS
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select IOMMU_API
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config OMAP_IOVMM
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@ -46,6 +46,7 @@
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#include "amd_iommu_proto.h"
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#include "amd_iommu_types.h"
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#include "irq_remapping.h"
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#include "pci.h"
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#define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
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@ -263,12 +264,6 @@ static bool check_device(struct device *dev)
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return true;
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}
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static void swap_pci_ref(struct pci_dev **from, struct pci_dev *to)
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{
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pci_dev_put(*from);
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*from = to;
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}
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static struct pci_bus *find_hosted_bus(struct pci_bus *bus)
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{
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while (!bus->self) {
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@ -701,9 +696,6 @@ retry:
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static void iommu_poll_events(struct amd_iommu *iommu)
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{
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u32 head, tail;
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unsigned long flags;
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spin_lock_irqsave(&iommu->lock, flags);
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head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
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tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
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@ -714,8 +706,6 @@ static void iommu_poll_events(struct amd_iommu *iommu)
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}
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writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
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spin_unlock_irqrestore(&iommu->lock, flags);
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}
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static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
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@ -740,17 +730,11 @@ static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
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static void iommu_poll_ppr_log(struct amd_iommu *iommu)
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{
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unsigned long flags;
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u32 head, tail;
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if (iommu->ppr_log == NULL)
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return;
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/* enable ppr interrupts again */
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writel(MMIO_STATUS_PPR_INT_MASK, iommu->mmio_base + MMIO_STATUS_OFFSET);
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spin_lock_irqsave(&iommu->lock, flags);
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head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
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tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
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@ -786,34 +770,50 @@ static void iommu_poll_ppr_log(struct amd_iommu *iommu)
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head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
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writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
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/*
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* Release iommu->lock because ppr-handling might need to
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* re-acquire it
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*/
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spin_unlock_irqrestore(&iommu->lock, flags);
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/* Handle PPR entry */
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iommu_handle_ppr_entry(iommu, entry);
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spin_lock_irqsave(&iommu->lock, flags);
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/* Refresh ring-buffer information */
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head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
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tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
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}
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spin_unlock_irqrestore(&iommu->lock, flags);
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}
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irqreturn_t amd_iommu_int_thread(int irq, void *data)
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{
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struct amd_iommu *iommu;
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struct amd_iommu *iommu = (struct amd_iommu *) data;
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u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
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for_each_iommu(iommu) {
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iommu_poll_events(iommu);
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iommu_poll_ppr_log(iommu);
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while (status & (MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK)) {
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/* Enable EVT and PPR interrupts again */
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writel((MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK),
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iommu->mmio_base + MMIO_STATUS_OFFSET);
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if (status & MMIO_STATUS_EVT_INT_MASK) {
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pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
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iommu_poll_events(iommu);
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}
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if (status & MMIO_STATUS_PPR_INT_MASK) {
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pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
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iommu_poll_ppr_log(iommu);
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}
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/*
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* Hardware bug: ERBT1312
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* When re-enabling interrupt (by writing 1
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* to clear the bit), the hardware might also try to set
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* the interrupt bit in the event status register.
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* In this scenario, the bit will be set, and disable
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* subsequent interrupts.
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*
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* Workaround: The IOMMU driver should read back the
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* status register and check if the interrupt bits are cleared.
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* If not, driver will need to go through the interrupt handler
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* again and re-clear the bits
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*/
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status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
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}
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return IRQ_HANDLED;
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}
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@ -2466,18 +2466,16 @@ static int device_change_notifier(struct notifier_block *nb,
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/* allocate a protection domain if a device is added */
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dma_domain = find_protection_domain(devid);
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if (dma_domain)
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goto out;
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dma_domain = dma_ops_domain_alloc();
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if (!dma_domain)
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goto out;
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dma_domain->target_dev = devid;
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if (!dma_domain) {
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dma_domain = dma_ops_domain_alloc();
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if (!dma_domain)
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goto out;
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dma_domain->target_dev = devid;
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spin_lock_irqsave(&iommu_pd_list_lock, flags);
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list_add_tail(&dma_domain->list, &iommu_pd_list);
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spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
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dev_data = get_dev_data(dev);
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spin_lock_irqsave(&iommu_pd_list_lock, flags);
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list_add_tail(&dma_domain->list, &iommu_pd_list);
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spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
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}
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dev->archdata.dma_ops = &amd_iommu_dma_ops;
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@ -2840,24 +2838,6 @@ static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
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spin_unlock_irqrestore(&domain->lock, flags);
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}
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/*
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* This is a special map_sg function which is used if we should map a
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* device which is not handled by an AMD IOMMU in the system.
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*/
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static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
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int nelems, int dir)
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{
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struct scatterlist *s;
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int i;
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for_each_sg(sglist, s, nelems, i) {
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s->dma_address = (dma_addr_t)sg_phys(s);
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s->dma_length = s->length;
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}
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return nelems;
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}
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/*
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* The exported map_sg function for dma_ops (handles scatter-gather
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* lists).
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@ -2877,9 +2857,7 @@ static int map_sg(struct device *dev, struct scatterlist *sglist,
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INC_STATS_COUNTER(cnt_map_sg);
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domain = get_domain(dev);
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if (PTR_ERR(domain) == -EINVAL)
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return map_sg_no_iommu(dev, sglist, nelems, dir);
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else if (IS_ERR(domain))
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if (IS_ERR(domain))
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return 0;
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dma_mask = *dev->dma_mask;
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@ -3412,7 +3390,7 @@ static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
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}
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static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
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unsigned long iova)
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dma_addr_t iova)
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{
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struct protection_domain *domain = dom->priv;
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unsigned long offset_mask;
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@ -3949,6 +3927,9 @@ static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic)
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if (!table)
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goto out;
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/* Initialize table spin-lock */
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spin_lock_init(&table->lock);
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if (ioapic)
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/* Keep the first 32 indexes free for IOAPIC interrupts */
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table->min_index = 32;
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@ -4009,7 +3990,7 @@ static int alloc_irq_index(struct irq_cfg *cfg, u16 devid, int count)
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c = 0;
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if (c == count) {
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struct irq_2_iommu *irte_info;
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struct irq_2_irte *irte_info;
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for (; c != 0; --c)
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table->table[index - c + 1] = IRTE_ALLOCATED;
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@ -4017,9 +3998,9 @@ static int alloc_irq_index(struct irq_cfg *cfg, u16 devid, int count)
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index -= count - 1;
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cfg->remapped = 1;
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irte_info = &cfg->irq_2_iommu;
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irte_info->sub_handle = devid;
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irte_info->irte_index = index;
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irte_info = &cfg->irq_2_irte;
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irte_info->devid = devid;
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irte_info->index = index;
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goto out;
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}
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@ -4100,7 +4081,7 @@ static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
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struct io_apic_irq_attr *attr)
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{
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struct irq_remap_table *table;
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struct irq_2_iommu *irte_info;
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struct irq_2_irte *irte_info;
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struct irq_cfg *cfg;
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union irte irte;
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int ioapic_id;
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@ -4112,7 +4093,7 @@ static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
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if (!cfg)
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return -EINVAL;
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irte_info = &cfg->irq_2_iommu;
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irte_info = &cfg->irq_2_irte;
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ioapic_id = mpc_ioapic_id(attr->ioapic);
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devid = get_ioapic_devid(ioapic_id);
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@ -4127,8 +4108,8 @@ static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
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/* Setup IRQ remapping info */
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cfg->remapped = 1;
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irte_info->sub_handle = devid;
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irte_info->irte_index = index;
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irte_info->devid = devid;
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irte_info->index = index;
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/* Setup IRTE for IOMMU */
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irte.val = 0;
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@ -4162,7 +4143,7 @@ static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
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static int set_affinity(struct irq_data *data, const struct cpumask *mask,
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bool force)
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{
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struct irq_2_iommu *irte_info;
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struct irq_2_irte *irte_info;
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unsigned int dest, irq;
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struct irq_cfg *cfg;
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union irte irte;
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@ -4173,12 +4154,12 @@ static int set_affinity(struct irq_data *data, const struct cpumask *mask,
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cfg = data->chip_data;
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irq = data->irq;
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irte_info = &cfg->irq_2_iommu;
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irte_info = &cfg->irq_2_irte;
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if (!cpumask_intersects(mask, cpu_online_mask))
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return -EINVAL;
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|
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if (get_irte(irte_info->sub_handle, irte_info->irte_index, &irte))
|
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if (get_irte(irte_info->devid, irte_info->index, &irte))
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return -EBUSY;
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|
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if (assign_irq_vector(irq, cfg, mask))
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|
|
@ -4194,7 +4175,7 @@ static int set_affinity(struct irq_data *data, const struct cpumask *mask,
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irte.fields.vector = cfg->vector;
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irte.fields.destination = dest;
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modify_irte(irte_info->sub_handle, irte_info->irte_index, irte);
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modify_irte(irte_info->devid, irte_info->index, irte);
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||||
|
||||
if (cfg->move_in_progress)
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send_cleanup_vector(cfg);
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|
|
@ -4206,16 +4187,16 @@ static int set_affinity(struct irq_data *data, const struct cpumask *mask,
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||||
static int free_irq(int irq)
|
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{
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||||
struct irq_2_iommu *irte_info;
|
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struct irq_2_irte *irte_info;
|
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struct irq_cfg *cfg;
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|
||||
cfg = irq_get_chip_data(irq);
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||||
if (!cfg)
|
||||
return -EINVAL;
|
||||
|
||||
irte_info = &cfg->irq_2_iommu;
|
||||
irte_info = &cfg->irq_2_irte;
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||||
|
||||
free_irte(irte_info->sub_handle, irte_info->irte_index);
|
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free_irte(irte_info->devid, irte_info->index);
|
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|
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return 0;
|
||||
}
|
||||
|
|
@ -4224,7 +4205,7 @@ static void compose_msi_msg(struct pci_dev *pdev,
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unsigned int irq, unsigned int dest,
|
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struct msi_msg *msg, u8 hpet_id)
|
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{
|
||||
struct irq_2_iommu *irte_info;
|
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struct irq_2_irte *irte_info;
|
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struct irq_cfg *cfg;
|
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union irte irte;
|
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|
||||
|
|
@ -4232,7 +4213,7 @@ static void compose_msi_msg(struct pci_dev *pdev,
|
|||
if (!cfg)
|
||||
return;
|
||||
|
||||
irte_info = &cfg->irq_2_iommu;
|
||||
irte_info = &cfg->irq_2_irte;
|
||||
|
||||
irte.val = 0;
|
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irte.fields.vector = cfg->vector;
|
||||
|
|
@ -4241,11 +4222,11 @@ static void compose_msi_msg(struct pci_dev *pdev,
|
|||
irte.fields.dm = apic->irq_dest_mode;
|
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irte.fields.valid = 1;
|
||||
|
||||
modify_irte(irte_info->sub_handle, irte_info->irte_index, irte);
|
||||
modify_irte(irte_info->devid, irte_info->index, irte);
|
||||
|
||||
msg->address_hi = MSI_ADDR_BASE_HI;
|
||||
msg->address_lo = MSI_ADDR_BASE_LO;
|
||||
msg->data = irte_info->irte_index;
|
||||
msg->data = irte_info->index;
|
||||
}
|
||||
|
||||
static int msi_alloc_irq(struct pci_dev *pdev, int irq, int nvec)
|
||||
|
|
@ -4270,7 +4251,7 @@ static int msi_alloc_irq(struct pci_dev *pdev, int irq, int nvec)
|
|||
static int msi_setup_irq(struct pci_dev *pdev, unsigned int irq,
|
||||
int index, int offset)
|
||||
{
|
||||
struct irq_2_iommu *irte_info;
|
||||
struct irq_2_irte *irte_info;
|
||||
struct irq_cfg *cfg;
|
||||
u16 devid;
|
||||
|
||||
|
|
@ -4285,18 +4266,18 @@ static int msi_setup_irq(struct pci_dev *pdev, unsigned int irq,
|
|||
return 0;
|
||||
|
||||
devid = get_device_id(&pdev->dev);
|
||||
irte_info = &cfg->irq_2_iommu;
|
||||
irte_info = &cfg->irq_2_irte;
|
||||
|
||||
cfg->remapped = 1;
|
||||
irte_info->sub_handle = devid;
|
||||
irte_info->irte_index = index + offset;
|
||||
irte_info->devid = devid;
|
||||
irte_info->index = index + offset;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int setup_hpet_msi(unsigned int irq, unsigned int id)
|
||||
{
|
||||
struct irq_2_iommu *irte_info;
|
||||
struct irq_2_irte *irte_info;
|
||||
struct irq_cfg *cfg;
|
||||
int index, devid;
|
||||
|
||||
|
|
@ -4304,7 +4285,7 @@ static int setup_hpet_msi(unsigned int irq, unsigned int id)
|
|||
if (!cfg)
|
||||
return -EINVAL;
|
||||
|
||||
irte_info = &cfg->irq_2_iommu;
|
||||
irte_info = &cfg->irq_2_irte;
|
||||
devid = get_hpet_devid(id);
|
||||
if (devid < 0)
|
||||
return devid;
|
||||
|
|
@ -4314,8 +4295,8 @@ static int setup_hpet_msi(unsigned int irq, unsigned int id)
|
|||
return index;
|
||||
|
||||
cfg->remapped = 1;
|
||||
irte_info->sub_handle = devid;
|
||||
irte_info->irte_index = index;
|
||||
irte_info->devid = devid;
|
||||
irte_info->index = index;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -213,6 +213,14 @@ enum iommu_init_state {
|
|||
IOMMU_INIT_ERROR,
|
||||
};
|
||||
|
||||
/* Early ioapic and hpet maps from kernel command line */
|
||||
#define EARLY_MAP_SIZE 4
|
||||
static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE];
|
||||
static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE];
|
||||
static int __initdata early_ioapic_map_size;
|
||||
static int __initdata early_hpet_map_size;
|
||||
static bool __initdata cmdline_maps;
|
||||
|
||||
static enum iommu_init_state init_state = IOMMU_START_STATE;
|
||||
|
||||
static int amd_iommu_enable_interrupts(void);
|
||||
|
|
@ -703,31 +711,66 @@ static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
|
|||
set_iommu_for_device(iommu, devid);
|
||||
}
|
||||
|
||||
static int add_special_device(u8 type, u8 id, u16 devid)
|
||||
static int __init add_special_device(u8 type, u8 id, u16 devid, bool cmd_line)
|
||||
{
|
||||
struct devid_map *entry;
|
||||
struct list_head *list;
|
||||
|
||||
if (type != IVHD_SPECIAL_IOAPIC && type != IVHD_SPECIAL_HPET)
|
||||
if (type == IVHD_SPECIAL_IOAPIC)
|
||||
list = &ioapic_map;
|
||||
else if (type == IVHD_SPECIAL_HPET)
|
||||
list = &hpet_map;
|
||||
else
|
||||
return -EINVAL;
|
||||
|
||||
list_for_each_entry(entry, list, list) {
|
||||
if (!(entry->id == id && entry->cmd_line))
|
||||
continue;
|
||||
|
||||
pr_info("AMD-Vi: Command-line override present for %s id %d - ignoring\n",
|
||||
type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
entry = kzalloc(sizeof(*entry), GFP_KERNEL);
|
||||
if (!entry)
|
||||
return -ENOMEM;
|
||||
|
||||
entry->id = id;
|
||||
entry->devid = devid;
|
||||
|
||||
if (type == IVHD_SPECIAL_IOAPIC)
|
||||
list = &ioapic_map;
|
||||
else
|
||||
list = &hpet_map;
|
||||
entry->id = id;
|
||||
entry->devid = devid;
|
||||
entry->cmd_line = cmd_line;
|
||||
|
||||
list_add_tail(&entry->list, list);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init add_early_maps(void)
|
||||
{
|
||||
int i, ret;
|
||||
|
||||
for (i = 0; i < early_ioapic_map_size; ++i) {
|
||||
ret = add_special_device(IVHD_SPECIAL_IOAPIC,
|
||||
early_ioapic_map[i].id,
|
||||
early_ioapic_map[i].devid,
|
||||
early_ioapic_map[i].cmd_line);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
for (i = 0; i < early_hpet_map_size; ++i) {
|
||||
ret = add_special_device(IVHD_SPECIAL_HPET,
|
||||
early_hpet_map[i].id,
|
||||
early_hpet_map[i].devid,
|
||||
early_hpet_map[i].cmd_line);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Reads the device exclusion range from ACPI and initializes the IOMMU with
|
||||
* it
|
||||
|
|
@ -764,6 +807,12 @@ static int __init init_iommu_from_acpi(struct amd_iommu *iommu,
|
|||
u32 dev_i, ext_flags = 0;
|
||||
bool alias = false;
|
||||
struct ivhd_entry *e;
|
||||
int ret;
|
||||
|
||||
|
||||
ret = add_early_maps();
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/*
|
||||
* First save the recommended feature enable bits from ACPI
|
||||
|
|
@ -929,7 +978,7 @@ static int __init init_iommu_from_acpi(struct amd_iommu *iommu,
|
|||
PCI_FUNC(devid));
|
||||
|
||||
set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
|
||||
ret = add_special_device(type, handle, devid);
|
||||
ret = add_special_device(type, handle, devid, false);
|
||||
if (ret)
|
||||
return ret;
|
||||
break;
|
||||
|
|
@ -980,7 +1029,7 @@ static void __init free_iommu_all(void)
|
|||
* BIOS should disable L2B micellaneous clock gating by setting
|
||||
* L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b
|
||||
*/
|
||||
static void __init amd_iommu_erratum_746_workaround(struct amd_iommu *iommu)
|
||||
static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu)
|
||||
{
|
||||
u32 value;
|
||||
|
||||
|
|
@ -1275,7 +1324,7 @@ static int iommu_setup_msi(struct amd_iommu *iommu)
|
|||
amd_iommu_int_handler,
|
||||
amd_iommu_int_thread,
|
||||
0, "AMD-Vi",
|
||||
iommu->dev);
|
||||
iommu);
|
||||
|
||||
if (r) {
|
||||
pci_disable_msi(iommu->dev);
|
||||
|
|
@ -1638,18 +1687,28 @@ static void __init free_on_init_error(void)
|
|||
|
||||
static bool __init check_ioapic_information(void)
|
||||
{
|
||||
const char *fw_bug = FW_BUG;
|
||||
bool ret, has_sb_ioapic;
|
||||
int idx;
|
||||
|
||||
has_sb_ioapic = false;
|
||||
ret = false;
|
||||
|
||||
/*
|
||||
* If we have map overrides on the kernel command line the
|
||||
* messages in this function might not describe firmware bugs
|
||||
* anymore - so be careful
|
||||
*/
|
||||
if (cmdline_maps)
|
||||
fw_bug = "";
|
||||
|
||||
for (idx = 0; idx < nr_ioapics; idx++) {
|
||||
int devid, id = mpc_ioapic_id(idx);
|
||||
|
||||
devid = get_ioapic_devid(id);
|
||||
if (devid < 0) {
|
||||
pr_err(FW_BUG "AMD-Vi: IOAPIC[%d] not in IVRS table\n", id);
|
||||
pr_err("%sAMD-Vi: IOAPIC[%d] not in IVRS table\n",
|
||||
fw_bug, id);
|
||||
ret = false;
|
||||
} else if (devid == IOAPIC_SB_DEVID) {
|
||||
has_sb_ioapic = true;
|
||||
|
|
@ -1666,11 +1725,11 @@ static bool __init check_ioapic_information(void)
|
|||
* when the BIOS is buggy and provides us the wrong
|
||||
* device id for the IOAPIC in the system.
|
||||
*/
|
||||
pr_err(FW_BUG "AMD-Vi: No southbridge IOAPIC found in IVRS table\n");
|
||||
pr_err("%sAMD-Vi: No southbridge IOAPIC found\n", fw_bug);
|
||||
}
|
||||
|
||||
if (!ret)
|
||||
pr_err("AMD-Vi: Disabling interrupt remapping due to BIOS Bug(s)\n");
|
||||
pr_err("AMD-Vi: Disabling interrupt remapping\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -1801,6 +1860,7 @@ static int __init early_amd_iommu_init(void)
|
|||
* Interrupt remapping enabled, create kmem_cache for the
|
||||
* remapping tables.
|
||||
*/
|
||||
ret = -ENOMEM;
|
||||
amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache",
|
||||
MAX_IRQS_PER_TABLE * sizeof(u32),
|
||||
IRQ_TABLE_ALIGNMENT,
|
||||
|
|
@ -2097,8 +2157,70 @@ static int __init parse_amd_iommu_options(char *str)
|
|||
return 1;
|
||||
}
|
||||
|
||||
__setup("amd_iommu_dump", parse_amd_iommu_dump);
|
||||
__setup("amd_iommu=", parse_amd_iommu_options);
|
||||
static int __init parse_ivrs_ioapic(char *str)
|
||||
{
|
||||
unsigned int bus, dev, fn;
|
||||
int ret, id, i;
|
||||
u16 devid;
|
||||
|
||||
ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
|
||||
|
||||
if (ret != 4) {
|
||||
pr_err("AMD-Vi: Invalid command line: ivrs_ioapic%s\n", str);
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (early_ioapic_map_size == EARLY_MAP_SIZE) {
|
||||
pr_err("AMD-Vi: Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n",
|
||||
str);
|
||||
return 1;
|
||||
}
|
||||
|
||||
devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
|
||||
|
||||
cmdline_maps = true;
|
||||
i = early_ioapic_map_size++;
|
||||
early_ioapic_map[i].id = id;
|
||||
early_ioapic_map[i].devid = devid;
|
||||
early_ioapic_map[i].cmd_line = true;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int __init parse_ivrs_hpet(char *str)
|
||||
{
|
||||
unsigned int bus, dev, fn;
|
||||
int ret, id, i;
|
||||
u16 devid;
|
||||
|
||||
ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
|
||||
|
||||
if (ret != 4) {
|
||||
pr_err("AMD-Vi: Invalid command line: ivrs_hpet%s\n", str);
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (early_hpet_map_size == EARLY_MAP_SIZE) {
|
||||
pr_err("AMD-Vi: Early HPET map overflow - ignoring ivrs_hpet%s\n",
|
||||
str);
|
||||
return 1;
|
||||
}
|
||||
|
||||
devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
|
||||
|
||||
cmdline_maps = true;
|
||||
i = early_hpet_map_size++;
|
||||
early_hpet_map[i].id = id;
|
||||
early_hpet_map[i].devid = devid;
|
||||
early_hpet_map[i].cmd_line = true;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
__setup("amd_iommu_dump", parse_amd_iommu_dump);
|
||||
__setup("amd_iommu=", parse_amd_iommu_options);
|
||||
__setup("ivrs_ioapic", parse_ivrs_ioapic);
|
||||
__setup("ivrs_hpet", parse_ivrs_hpet);
|
||||
|
||||
IOMMU_INIT_FINISH(amd_iommu_detect,
|
||||
gart_iommu_hole_init,
|
||||
|
|
|
|||
|
|
@ -99,6 +99,7 @@
|
|||
#define PASID_MASK 0x000fffff
|
||||
|
||||
/* MMIO status bits */
|
||||
#define MMIO_STATUS_EVT_INT_MASK (1 << 1)
|
||||
#define MMIO_STATUS_COM_WAIT_INT_MASK (1 << 2)
|
||||
#define MMIO_STATUS_PPR_INT_MASK (1 << 6)
|
||||
|
||||
|
|
@ -591,6 +592,7 @@ struct devid_map {
|
|||
struct list_head list;
|
||||
u8 id;
|
||||
u16 devid;
|
||||
bool cmd_line;
|
||||
};
|
||||
|
||||
/* Map HPET and IOAPIC ids to the devid used by the IOMMU */
|
||||
|
|
|
|||
|
|
@ -1027,7 +1027,7 @@ done:
|
|||
}
|
||||
|
||||
static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *domain,
|
||||
unsigned long iova)
|
||||
dma_addr_t iova)
|
||||
{
|
||||
struct exynos_iommu_domain *priv = domain->priv;
|
||||
unsigned long *entry;
|
||||
|
|
|
|||
|
|
@ -47,6 +47,7 @@
|
|||
#include <asm/iommu.h>
|
||||
|
||||
#include "irq_remapping.h"
|
||||
#include "pci.h"
|
||||
|
||||
#define ROOT_SIZE VTD_PAGE_SIZE
|
||||
#define CONTEXT_SIZE VTD_PAGE_SIZE
|
||||
|
|
@ -4126,7 +4127,7 @@ static size_t intel_iommu_unmap(struct iommu_domain *domain,
|
|||
}
|
||||
|
||||
static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
|
||||
unsigned long iova)
|
||||
dma_addr_t iova)
|
||||
{
|
||||
struct dmar_domain *dmar_domain = domain->priv;
|
||||
struct dma_pte *pte;
|
||||
|
|
@ -4152,12 +4153,6 @@ static int intel_iommu_domain_has_cap(struct iommu_domain *domain,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void swap_pci_ref(struct pci_dev **from, struct pci_dev *to)
|
||||
{
|
||||
pci_dev_put(*from);
|
||||
*from = to;
|
||||
}
|
||||
|
||||
#define REQ_ACS_FLAGS (PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF)
|
||||
|
||||
static int intel_iommu_add_device(struct device *dev)
|
||||
|
|
|
|||
|
|
@ -204,6 +204,35 @@ again:
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(iommu_group_alloc);
|
||||
|
||||
struct iommu_group *iommu_group_get_by_id(int id)
|
||||
{
|
||||
struct kobject *group_kobj;
|
||||
struct iommu_group *group;
|
||||
const char *name;
|
||||
|
||||
if (!iommu_group_kset)
|
||||
return NULL;
|
||||
|
||||
name = kasprintf(GFP_KERNEL, "%d", id);
|
||||
if (!name)
|
||||
return NULL;
|
||||
|
||||
group_kobj = kset_find_obj(iommu_group_kset, name);
|
||||
kfree(name);
|
||||
|
||||
if (!group_kobj)
|
||||
return NULL;
|
||||
|
||||
group = container_of(group_kobj, struct iommu_group, kobj);
|
||||
BUG_ON(group->id != id);
|
||||
|
||||
kobject_get(group->devices_kobj);
|
||||
kobject_put(&group->kobj);
|
||||
|
||||
return group;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(iommu_group_get_by_id);
|
||||
|
||||
/**
|
||||
* iommu_group_get_iommudata - retrieve iommu_data registered for a group
|
||||
* @group: the group
|
||||
|
|
@ -706,8 +735,7 @@ void iommu_detach_group(struct iommu_domain *domain, struct iommu_group *group)
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(iommu_detach_group);
|
||||
|
||||
phys_addr_t iommu_iova_to_phys(struct iommu_domain *domain,
|
||||
unsigned long iova)
|
||||
phys_addr_t iommu_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova)
|
||||
{
|
||||
if (unlikely(domain->ops->iova_to_phys == NULL))
|
||||
return 0;
|
||||
|
|
@ -854,12 +882,13 @@ EXPORT_SYMBOL_GPL(iommu_unmap);
|
|||
|
||||
|
||||
int iommu_domain_window_enable(struct iommu_domain *domain, u32 wnd_nr,
|
||||
phys_addr_t paddr, u64 size)
|
||||
phys_addr_t paddr, u64 size, int prot)
|
||||
{
|
||||
if (unlikely(domain->ops->domain_window_enable == NULL))
|
||||
return -ENODEV;
|
||||
|
||||
return domain->ops->domain_window_enable(domain, wnd_nr, paddr, size);
|
||||
return domain->ops->domain_window_enable(domain, wnd_nr, paddr, size,
|
||||
prot);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(iommu_domain_window_enable);
|
||||
|
||||
|
|
|
|||
|
|
@ -2,7 +2,6 @@
|
|||
#include <linux/cpumask.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/cpumask.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/msi.h>
|
||||
#include <linux/irq.h>
|
||||
|
|
|
|||
|
|
@ -554,7 +554,7 @@ fail:
|
|||
}
|
||||
|
||||
static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain,
|
||||
unsigned long va)
|
||||
dma_addr_t va)
|
||||
{
|
||||
struct msm_priv *priv;
|
||||
struct msm_iommu_drvdata *iommu_drvdata;
|
||||
|
|
|
|||
|
|
@ -1219,7 +1219,7 @@ static void omap_iommu_domain_destroy(struct iommu_domain *domain)
|
|||
}
|
||||
|
||||
static phys_addr_t omap_iommu_iova_to_phys(struct iommu_domain *domain,
|
||||
unsigned long da)
|
||||
dma_addr_t da)
|
||||
{
|
||||
struct omap_iommu_domain *omap_domain = domain->priv;
|
||||
struct omap_iommu *oiommu = omap_domain->iommu_dev;
|
||||
|
|
|
|||
29
drivers/iommu/pci.h
Normal file
29
drivers/iommu/pci.h
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
/*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License, version 2, as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*
|
||||
* Copyright (C) 2013 Red Hat, Inc.
|
||||
* Copyright (C) 2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
*/
|
||||
#ifndef __IOMMU_PCI_H
|
||||
#define __IOMMU_PCI_H
|
||||
|
||||
/* Helper function for swapping pci device reference */
|
||||
static inline void swap_pci_ref(struct pci_dev **from, struct pci_dev *to)
|
||||
{
|
||||
pci_dev_put(*from);
|
||||
*from = to;
|
||||
}
|
||||
|
||||
#endif /* __IOMMU_PCI_H */
|
||||
|
|
@ -296,7 +296,7 @@ done:
|
|||
}
|
||||
|
||||
static phys_addr_t shmobile_iommu_iova_to_phys(struct iommu_domain *domain,
|
||||
unsigned long iova)
|
||||
dma_addr_t iova)
|
||||
{
|
||||
struct shmobile_iommu_domain *sh_domain = domain->priv;
|
||||
uint32_t l1entry = 0, l2entry = 0;
|
||||
|
|
|
|||
|
|
@ -279,7 +279,7 @@ static size_t gart_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
|
|||
}
|
||||
|
||||
static phys_addr_t gart_iommu_iova_to_phys(struct iommu_domain *domain,
|
||||
unsigned long iova)
|
||||
dma_addr_t iova)
|
||||
{
|
||||
struct gart_device *gart = domain->priv;
|
||||
unsigned long pte;
|
||||
|
|
@ -295,7 +295,8 @@ static phys_addr_t gart_iommu_iova_to_phys(struct iommu_domain *domain,
|
|||
|
||||
pa = (pte & GART_PAGE_MASK);
|
||||
if (!pfn_valid(__phys_to_pfn(pa))) {
|
||||
dev_err(gart->dev, "No entry for %08lx:%08x\n", iova, pa);
|
||||
dev_err(gart->dev, "No entry for %08llx:%08x\n",
|
||||
(unsigned long long)iova, pa);
|
||||
gart_dump_table(gart);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -757,7 +757,7 @@ static size_t smmu_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
|
|||
}
|
||||
|
||||
static phys_addr_t smmu_iommu_iova_to_phys(struct iommu_domain *domain,
|
||||
unsigned long iova)
|
||||
dma_addr_t iova)
|
||||
{
|
||||
struct smmu_as *as = domain->priv;
|
||||
unsigned long *pte;
|
||||
|
|
@ -772,7 +772,8 @@ static phys_addr_t smmu_iommu_iova_to_phys(struct iommu_domain *domain,
|
|||
pfn = *pte & SMMU_PFN_MASK;
|
||||
WARN_ON(!pfn_valid(pfn));
|
||||
dev_dbg(as->smmu->dev,
|
||||
"iova:%08lx pfn:%08lx asid:%d\n", iova, pfn, as->asid);
|
||||
"iova:%08llx pfn:%08lx asid:%d\n", (unsigned long long)iova,
|
||||
pfn, as->asid);
|
||||
|
||||
spin_unlock_irqrestore(&as->lock, flags);
|
||||
return PFN_PHYS(pfn);
|
||||
|
|
|
|||
Loading…
Reference in a new issue