From 0c5f471d1ca93da7b627ef0c9ea7740e0b242bb6 Mon Sep 17 00:00:00 2001 From: Sai Chaitanya Kaveti Date: Thu, 6 Jul 2023 16:11:30 +0530 Subject: [PATCH] msm: ep_pcie: Set clock power management bit for EP According to PCIe spec, PCIE_CAP_CLOCK_POWER_MAN bit in LINK_CAPABILITIES_REG register should be set for EP. But it is seen as cleared after core reset. In the current driver this bit is being set but it is not taking effect. Enabling CLK_PM_EN in PCIE_ELBI_SYS_CTRL register, so that PCIE_CAP_CLOCK_POWER_MAN is set. Change-Id: I16654d5a477fa8eeaad61d6ec1dd32757627e2f9 Signed-off-by: Sai Chaitanya Kaveti --- drivers/platform/msm/ep_pcie/ep_pcie_core.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/platform/msm/ep_pcie/ep_pcie_core.c b/drivers/platform/msm/ep_pcie/ep_pcie_core.c index 7e81a80905b9..dcbee0bd18f7 100644 --- a/drivers/platform/msm/ep_pcie/ep_pcie_core.c +++ b/drivers/platform/msm/ep_pcie/ep_pcie_core.c @@ -828,6 +828,9 @@ static void ep_pcie_core_init(struct ep_pcie_dev_t *dev, bool configured) ep_pcie_write_mask(dev->dm_core + PCIE20_L1SUB_CAPABILITY, 0, 0x1f); + /* Set CLK_PM_EN which allows to configure the clock-power-man bit below for EP */ + ep_pcie_write_mask(dev->elbi + PCIE20_ELBI_SYS_CTRL, 1, BIT(7)); + /* Enable Clock Power Management */ ep_pcie_write_reg_field(dev->dm_core, PCIE20_LINK_CAPABILITIES, PCIE20_MASK_CLOCK_POWER_MAN, 0x1);