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VFIO updates for v4.20
- EDID interfaces for vfio devices supporting display extensions
(Gerd Hoffmann)
- Generically select Type-1 IOMMU model support on ARM/ARM64
(Geert Uytterhoeven)
- Quirk for VFs reporting INTx pin (Alex Williamson)
- Fix error path memory leak in MSI support (Li Qiang)
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Merge tag 'vfio-v4.20-rc1.v2' of git://github.com/awilliam/linux-vfio
Pull VFIO updates from Alex Williamson:
- EDID interfaces for vfio devices supporting display extensions (Gerd
Hoffmann)
- Generically select Type-1 IOMMU model support on ARM/ARM64 (Geert
Uytterhoeven)
- Quirk for VFs reporting INTx pin (Alex Williamson)
- Fix error path memory leak in MSI support (Li Qiang)
* tag 'vfio-v4.20-rc1.v2' of git://github.com/awilliam/linux-vfio:
vfio: add edid support to mbochs sample driver
vfio: add edid api for display (vgpu) devices.
drivers/vfio: Allow type-1 IOMMU instantiation with all ARM/ARM64 IOMMUs
vfio/pci: Mask buggy SR-IOV VF INTx support
vfio/pci: Fix potential memory leak in vfio_msi_cap_len
This commit is contained in:
commit
0c86e761b9
5 changed files with 204 additions and 23 deletions
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@ -21,7 +21,7 @@ config VFIO_VIRQFD
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menuconfig VFIO
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tristate "VFIO Non-Privileged userspace driver framework"
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depends on IOMMU_API
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select VFIO_IOMMU_TYPE1 if (X86 || S390 || ARM_SMMU || ARM_SMMU_V3)
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select VFIO_IOMMU_TYPE1 if (X86 || S390 || ARM || ARM64)
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select ANON_INODES
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help
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VFIO provides a framework for secure userspace device drivers.
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@ -434,10 +434,14 @@ static int vfio_pci_get_irq_count(struct vfio_pci_device *vdev, int irq_type)
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{
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if (irq_type == VFIO_PCI_INTX_IRQ_INDEX) {
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u8 pin;
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pci_read_config_byte(vdev->pdev, PCI_INTERRUPT_PIN, &pin);
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if (IS_ENABLED(CONFIG_VFIO_PCI_INTX) && !vdev->nointx && pin)
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return 1;
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if (!IS_ENABLED(CONFIG_VFIO_PCI_INTX) ||
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vdev->nointx || vdev->pdev->is_virtfn)
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return 0;
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pci_read_config_byte(vdev->pdev, PCI_INTERRUPT_PIN, &pin);
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return pin ? 1 : 0;
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} else if (irq_type == VFIO_PCI_MSI_IRQ_INDEX) {
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u8 pos;
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u16 flags;
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@ -1180,8 +1180,10 @@ static int vfio_msi_cap_len(struct vfio_pci_device *vdev, u8 pos)
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return -ENOMEM;
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ret = init_pci_cap_msi_perm(vdev->msi_perm, len, flags);
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if (ret)
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if (ret) {
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kfree(vdev->msi_perm);
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return ret;
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}
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return len;
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}
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@ -1609,6 +1611,15 @@ static int vfio_ecap_init(struct vfio_pci_device *vdev)
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return 0;
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}
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/*
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* Nag about hardware bugs, hopefully to have vendors fix them, but at least
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* to collect a list of dependencies for the VF INTx pin quirk below.
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*/
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static const struct pci_device_id known_bogus_vf_intx_pin[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x270c) },
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{}
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};
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/*
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* For each device we allocate a pci_config_map that indicates the
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* capability occupying each dword and thus the struct perm_bits we
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@ -1674,6 +1685,24 @@ int vfio_config_init(struct vfio_pci_device *vdev)
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if (pdev->is_virtfn) {
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*(__le16 *)&vconfig[PCI_VENDOR_ID] = cpu_to_le16(pdev->vendor);
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*(__le16 *)&vconfig[PCI_DEVICE_ID] = cpu_to_le16(pdev->device);
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/*
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* Per SR-IOV spec rev 1.1, 3.4.1.18 the interrupt pin register
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* does not apply to VFs and VFs must implement this register
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* as read-only with value zero. Userspace is not readily able
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* to identify whether a device is a VF and thus that the pin
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* definition on the device is bogus should it violate this
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* requirement. We already virtualize the pin register for
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* other purposes, so we simply need to replace the bogus value
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* and consider VFs when we determine INTx IRQ count.
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*/
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if (vconfig[PCI_INTERRUPT_PIN] &&
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!pci_match_id(known_bogus_vf_intx_pin, pdev))
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pci_warn(pdev,
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"Hardware bug: VF reports bogus INTx pin %d\n",
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vconfig[PCI_INTERRUPT_PIN]);
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vconfig[PCI_INTERRUPT_PIN] = 0; /* Gratuitous for good VFs */
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}
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if (!IS_ENABLED(CONFIG_VFIO_PCI_INTX) || vdev->nointx)
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