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bindings: Add USB PHY drivers related documentation
This change adds USB hig-speed and super-speed PHY drivers related documentation. Change-Id: I525315178e32d2505680b0c5fe6304a52780f81d
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Mayank Rana
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153
bindings/usb/qcom,msm-phy.txt
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153
bindings/usb/qcom,msm-phy.txt
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QCOM USB PHY transceivers
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HSUSB PHY
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Required properties:
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- compatible: Should be "qcom,usb-hsphy-snps-femto"
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- reg: Address and length of the register set for the device
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Required regs are:
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"hsusb_phy_base" : the base register for the PHY
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- <supply-name>-supply: phandle to the regulator device tree node
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Required "supply-name" examples are:
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"vdd" : vdd supply for HSPHY digital circuit operation
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"vdda18" : 1.8v supply for HSPHY
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"vdda33" : 3.3v supply for HSPHY
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- clocks: a list of phandles to the PHY clocks. Use as per
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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- clock-names: Names of the clocks in 1-1 correspondence with the "clocks"
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property. "ref_clk_src" is a mandatory clock.
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- qcom,vdd-voltage-level: This property must be a list of three integer
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values (no, min, max) where each value represents either a voltage in
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microvolts or a value corresponding to voltage corner
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- resets: reset specifier pair consists of phandle for the reset controller
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and reset lines used by this controller.
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- reset-names: reset signal name strings sorted in the same order as the resets
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property.
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Optional properties:
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- qcom,param-override-seq: parameter override sequence with value, reg offset
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pair.
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- qcom,rcal-mask: efuse calibration mask.
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- reg: Address and length of the register set for the device
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Optional regs are:
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"phy_rcal_reg": register address for efuse used for rext calibration
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"eud_enable_reg" : register address to read eud enable/disable status.
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Example:
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hsphy@f9200000 {
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compatible = "qcom,usb-hsphy-snps-femto";
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reg = <0xff1000 0x400>;
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vdd-supply = <&pm8841_s2_corner>;
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vdda18-supply = <&pm8941_l6>;
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vdda33-supply = <&pm8941_l24>;
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qcom,vdd-voltage-level = <0 872000 872000>;
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qcom,param-override-seq = <0x43 0x70>;
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};
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SSUSB-QMP PHY
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Required properties:
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- compatible: Should be "qcom,usb-ssphy-qmp", "qcom,usb-ssphy-qmp-v1" or
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"qcom,usb-ssphy-qmp-v2" or "qcom,usb-ssphy-qmp-usb3-or-dp" or
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"qcom,usb-ssphy-qmp-dp-combo"
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- reg: Address and length of the register set for the device
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Required reg-names entry must contain:
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"qmp_phy_base" : QMP PHY Base register set.
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- <supply-name>-supply: phandle to the regulator device tree node
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Required "supply-name" examples are:
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"vdd" : vdd supply for SSPHY digital circuit operation
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"core" : high-voltage analog supply for SSPHY
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- clocks: a list of phandles to the PHY clocks. Use as per
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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- clock-names: Names of the clocks in 1-1 correspondence with the "clocks"
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property. Required clocks are "aux_clk" and "pipe_clk".
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- qcom,vdd-voltage-level: This property must be a list of three integer
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values (no, min, max) where each value represents either a voltage in
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microvolts or a value corresponding to voltage corner
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- qcom,qmp-phy-init-seq: QMP PHY initialization sequence with reg offset, its
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value, delay after register write.
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- qcom,qmp-phy-reg-offset: Provides important phy register offsets in an order
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defined in the phy driver.
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Provide below mentioned register offsets in order for non USB DP combo PHY:
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USB3_PHY_PCS_STATUS,
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USB3_PHY_AUTONOMOUS_MODE_CTRL,
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USB3_PHY_LFPS_RXTERM_IRQ_CLEAR,
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USB3_PHY_POWER_DOWN_CONTROL,
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USB3_PHY_SW_RESET,
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USB3_PHY_START
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In addion to above following set of registers offset needed for USB DP combo PHY in mentioned order:
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USB3_DP_DP_PHY_PD_CTL,
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USB3_DP_COM_POWER_DOWN_CTRL,
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USB3_DP_COM_SW_RESET,
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USB3_DP_COM_RESET_OVRD_CTRL,
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USB3_DP_COM_PHY_MODE_CTRL,
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USB3_DP_COM_TYPEC_CTRL,
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USB3_DP_COM_SWI_CTRL,
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Optional register for enabling/disabling VLS clamp if available:
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USB3_PCS_MISC_CLAMP_ENABLE
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Optional register for configuring USB Type-C port select if available:
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USB3_PHY_PCS_MISC_TYPEC_CTRL
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- resets: reset specifier pair consists of phandle for the reset controller
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and reset lines used by this controller.
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- reset-names: reset signal name strings sorted in the same order as the resets
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property.
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Optional properties:
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- reg: Additional register set of address and length to control QMP PHY are:
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"tcsr_usb3_dp_phymode" : top-level CSR register to be written to select
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super speed usb qmp phy.
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"pcs_clamp_enable_reg" : Clamps the phy data inputs and enables USB3
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autonomous mode.
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"vls_clamp_reg" : top-level CSR register to be written to enable phy vls
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clamp which allows phy to detect autonomous mode.
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- clocks: a list of phandles to the PHY clocks. Use as per
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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- clock-names: Names of the clocks in 1-1 correspondence with the "clocks"
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property. "cfg_ahb_clk" and "com_aux_clk" are an optional clocks.
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- qcom,vbus-valid-override: If present, indicates VBUS pin is not connected to
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the USB PHY and the controller must rely on external VBUS notification in
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order to manually relay the notification to the SSPHY.
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- qcom,vdd-max-load-uA: If present, indicates the maximum current (in uA) the
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PHY is expected to draw from the vdd power supply.
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- qcom,core-voltage-level: This property must be a list of three integer
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values (no, min, max) where each value represents either a voltage in
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- qcom,core-max-load-uA: If present, indicates the maximum current (in uA) the
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PHY is expected to draw from the core power supply.
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microvolts or a value corresponding to voltage corner.
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- qcom,link-training-reset: This property indicates to start link training
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timer to reset the elastic buffer based on rx equalization value.
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- extcon : phandle to external connector devices which provide type-C based
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"USB-HOST" cable events. This phandle is used for notifying number
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of lanes used in case of USB+DP concurrent mode to driver.
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Example:
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ssphy0: ssphy@f9b38000 {
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compatible = "qcom,usb-ssphy-qmp";
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reg = <0xf9b38000 0x16c>,
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<0x01947244 0x4>;
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reg-names = "qmp_phy_base",
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"vls_clamp_reg";
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vdd-supply = <&pmd9635_l4>;
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vdda18-supply = <&pmd9635_l8>;
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qcom,vdd-voltage-level = <0 900000 1050000>;
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qcom,vbus-valid-override;
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clocks = <&clock_gcc clk_gcc_usb3_phy_aux_clk>,
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<&clock_gcc clk_gcc_usb3_phy_pipe_clk>,
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<&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>,
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<&clock_gcc clk_ln_bb_clk1>,
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<&clock_gcc clk_gcc_usb3_clkref_clk>;
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clock-names = "aux_clk", "pipe_clk", "cfg_ahb_clk",
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"ref_clk_src", "ref_clk";
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resets = <&clock_gcc GCC_USB3_PHY_BCR>,
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<&clock_gcc GCC_USB3PHY_PHY_BCR>;
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reset-names = "phy_reset",
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"phy_phy_reset";
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};
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