From 0d075161e772986e987665beb4348591c05b3e4b Mon Sep 17 00:00:00 2001
From: Jagadeesh Kona <jkona@qti.qualcomm.com>
Date: Tue, 19 Jan 2021 11:54:59 +0530
Subject: [PATCH] ARM: dts: msm: Mark GCC USB30 secondary clocks as protected
 on YUPIK

GCC USB30 secondary clocks are not required on YUPIK, hence mark them
as protected and remove support for USB30 secondary GDSC.

Change-Id: I80abe0f3c10fee6e63a15027f4bd13208e59a795
---
 qcom/yupik.dtsi | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi
index df4341dc8f48..95bcc886b2e4 100644
--- a/qcom/yupik.dtsi
+++ b/qcom/yupik.dtsi
@@ -942,7 +942,14 @@
 		<GCC_PCIE_1_MSTR_AXI_CLK>, <GCC_PCIE_1_PHY_RCHNG_CLK_SRC>,
 		<GCC_PCIE_1_PIPE_CLK>, <GCC_PCIE_1_PIPE_CLK_SRC>,
 		<GCC_PCIE_1_SLV_AXI_CLK>, <GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
-		<GCC_PCIE_THROTTLE_CORE_CLK>, <GCC_THROTTLE_PCIE_AHB_CLK>;
+		<GCC_PCIE_THROTTLE_CORE_CLK>, <GCC_THROTTLE_PCIE_AHB_CLK>,
+		<GCC_AGGRE_USB3_SEC_AXI_CLK>, <GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
+		<GCC_USB30_SEC_MASTER_CLK>, <GCC_USB30_SEC_MASTER_CLK_SRC>,
+		<GCC_USB30_SEC_MOCK_UTMI_CLK>, <GCC_USB30_SEC_MOCK_UTMI_CLK_SRC>,
+		<GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC>, <GCC_USB30_SEC_SLEEP_CLK>,
+		<GCC_USB3_SEC_PHY_AUX_CLK>, <GCC_USB3_SEC_PHY_AUX_CLK_SRC>,
+		<GCC_USB3_SEC_PHY_COM_AUX_CLK>, <GCC_USB3_SEC_PHY_PIPE_CLK>,
+		<GCC_USB3_SEC_PHY_PIPE_CLK_SRC>;
 
 		#clock-cells = <1>;
 		#reset-cells = <1>;
@@ -3739,11 +3746,6 @@
 	status = "ok";
 };
 
-&gcc_usb30_sec_gdsc {
-	qcom,support-hw-trigger;
-	status = "ok";
-};
-
 &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {
 	status = "ok";
 };