From 432ca21d5097214edc565acc6ff0ff11130588a4 Mon Sep 17 00:00:00 2001
From: Rajeev Nandan <RAJEEVNY@qti.qualcomm.com>
Date: Thu, 16 Jul 2020 15:14:11 +0530
Subject: [PATCH] ARM: dts: msm: add pinctrl information for shima target

Add pinctrl information for reset and tear check(TE) GPIO.

Change-Id: I139ec21379720032466bcbaa78b3c5e046cd10c4
---
 qcom/shima-pinctrl.dtsi | 108 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 108 insertions(+)

diff --git a/qcom/shima-pinctrl.dtsi b/qcom/shima-pinctrl.dtsi
index 016c725063c1..3b652bc32028 100644
--- a/qcom/shima-pinctrl.dtsi
+++ b/qcom/shima-pinctrl.dtsi
@@ -2808,6 +2808,114 @@
 				};
 			};
 		};
+
+		pmx_sde: pmx_sde {
+			sde_dsi_active: sde_dsi_active {
+				mux {
+					pins = "gpio24";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio24";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable = <0>;     /* no pull */
+				};
+			};
+
+			sde_dsi_suspend: sde_dsi_suspend {
+				mux {
+					pins = "gpio24";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio24";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+				};
+			};
+
+			sde_dsi1_active: sde_dsi1_active {
+				mux {
+					pins = "gpio25";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio25";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable = <0>;     /* no pull */
+				};
+			};
+
+			sde_dsi1_suspend: sde_dsi1_suspend {
+				mux {
+					pins = "gpio25";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio25";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+				};
+			};
+		};
+
+		pmx_sde_te: pmx_sde_te {
+			sde_te_active: sde_te_active {
+				mux {
+					pins = "gpio82";
+					function = "mdp_vsync";
+				};
+
+				config {
+					pins = "gpio82";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+				};
+			};
+
+			sde_te_suspend: sde_te_suspend {
+				mux {
+					pins = "gpio82";
+					function = "mdp_vsync";
+				};
+
+				config {
+					pins = "gpio82";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+				};
+			};
+
+			sde_te1_active: sde_te1_active {
+				mux {
+					pins = "gpio83";
+					function = "mdp_vsync";
+				};
+
+				config {
+					pins = "gpio83";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+				};
+			};
+
+			sde_te1_suspend: sde_te1_suspend {
+				mux {
+					pins = "gpio83";
+					function = "mdp_vsync";
+				};
+
+				config {
+					pins = "gpio83";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+				};
+			};
+		};
 	};
 };