From 20dd5297cafa2de341a269aaaced3661cac5c1e7 Mon Sep 17 00:00:00 2001
From: Rishabh Bhatnagar <rishabhb@quicinc.com>
Date: Tue, 8 Sep 2020 10:16:31 -0700
Subject: [PATCH] ARM: dts: msm: Add scm dt nodes for Olympic

Add scm and scm pas device tree nodes for Olympic target.
These are required for pil image authentication.

Change-Id: I4fd67c5a6861e83679178cd3fa0b0f221f5142e8
---
 qcom/sdxlemur.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi
index ba69d5c837c6..bd63804405d3 100644
--- a/qcom/sdxlemur.dtsi
+++ b/qcom/sdxlemur.dtsi
@@ -103,6 +103,13 @@
 	};
 
 	soc: soc { };
+
+	firmware: firmware {
+		scm {
+			compatible = "qcom,scm";
+			qcom,dload-mode = <&tcsr 0x13000>;
+		};
+	};
 };
 
 &soc {
@@ -226,6 +233,11 @@
 		qcom,wakeup-enable;
 	};
 
+	pil_scm_pas {
+		compatible = "qcom,pil-tz-scm-pas";
+		interconnects = <&system_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
+	};
+
 	qcom,msm-rtb {
 		compatible = "qcom,msm-rtb";
 		qcom,rtb-size = <0x100000>;
@@ -477,6 +489,11 @@
 		#hwlock-cells = <1>;
 	};
 
+	tcsr: syscon@1fc0000 {
+		compatible = "syscon";
+		reg = <0x1fc0000 0x30000>;
+	};
+
 	cache-controller@9200000 {
 		compatible = "qcom,sdxlemur-llcc", "qcom,llcc-v2";
 		reg = <0x9200000 0x50000>;