From 0e2951923919636e4cd70f786918af0a41d1baee Mon Sep 17 00:00:00 2001
From: gururaj chalgeri <gchalger@qti.qualcomm.com>
Date: Tue, 21 Jul 2020 20:04:54 +0530
Subject: [PATCH] ARM: dts: msm: use 'dma-coherent-hint-cached' for fastrpc
 nodes

Use 'dma-coherent-hint-cached' instead of 'dma-coherent' for the
fastrpc iommu context banks.Now, on a QGKI kernel, cached ION
buffers will be DMA mapped as IOMMU cached for the fastrpc
devices, all other buffers will be DMA mapped as IOMMU uncached
and dma_alloc_attrs will always return memory with a cached CPU
mapping as well as DMA mapping its memory as IOMMU cached.

Change-Id: Ic2bc830f231121a2351b0dcb5206e0e7d962bc41
---
 qcom/shima.dtsi | 32 ++++++++++++++++----------------
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi
index 9f55f95df385..9d8d1697306f 100644
--- a/qcom/shima.dtsi
+++ b/qcom/shima.dtsi
@@ -1794,7 +1794,7 @@
 					 <&apps_smmu 0x1981 0x0420>;
 			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
 			qcom,iommu-faults = "stall-disable", "HUPCF";
-			dma-coherent;
+			dma-coherent-hint-cached;
 		};
 
 		qcom,msm_fastrpc_compute_cb2 {
@@ -1804,7 +1804,7 @@
 					 <&apps_smmu 0x1982 0x0420>;
 			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
 			qcom,iommu-faults = "stall-disable", "HUPCF";
-			dma-coherent;
+			dma-coherent-hint-cached;
 		};
 
 		qcom,msm_fastrpc_compute_cb3 {
@@ -1814,7 +1814,7 @@
 					 <&apps_smmu 0x1983 0x0420>;
 			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
 			qcom,iommu-faults = "stall-disable", "HUPCF";
-			dma-coherent;
+			dma-coherent-hint-cached;
 		};
 
 		qcom,msm_fastrpc_compute_cb4 {
@@ -1824,7 +1824,7 @@
 					 <&apps_smmu 0x1984 0x0420>;
 			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
 			qcom,iommu-faults = "stall-disable", "HUPCF";
-			dma-coherent;
+			dma-coherent-hint-cached;
 		};
 
 		qcom,msm_fastrpc_compute_cb5 {
@@ -1834,7 +1834,7 @@
 					 <&apps_smmu 0x1985 0x0420>;
 			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
 			qcom,iommu-faults = "stall-disable", "HUPCF";
-			dma-coherent;
+			dma-coherent-hint-cached;
 		};
 
 		qcom,msm_fastrpc_compute_cb6 {
@@ -1844,7 +1844,7 @@
 					 <&apps_smmu 0x1986 0x0420>;
 			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
 			qcom,iommu-faults = "stall-disable", "HUPCF";
-			dma-coherent;
+			dma-coherent-hint-cached;
 		};
 
 		qcom,msm_fastrpc_compute_cb7 {
@@ -1854,7 +1854,7 @@
 					 <&apps_smmu 0x1987 0x0420>;
 			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
 			qcom,iommu-faults = "stall-disable", "HUPCF";
-			dma-coherent;
+			dma-coherent-hint-cached;
 		};
 
 		qcom,msm_fastrpc_compute_cb8 {
@@ -1864,7 +1864,7 @@
 					 <&apps_smmu 0x1988 0x0420>;
 			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
 			qcom,iommu-faults = "stall-disable", "HUPCF";
-			dma-coherent;
+			dma-coherent-hint-cached;
 		};
 
 		qcom,msm_fastrpc_compute_cb9 {
@@ -1876,7 +1876,7 @@
 			qcom,iommu-dma-addr-pool = <0x60000000 0x78000000>;
 			qcom,iommu-faults = "stall-disable", "HUPCF";
 			qcom,iommu-vmid = <0xA>;	/* VMID_CP_PIXEL */
-			dma-coherent;
+			dma-coherent-hint-cached;
 		};
 
 		qcom,msm_fastrpc_compute_cb10 {
@@ -1885,7 +1885,7 @@
 			iommus = <&apps_smmu 0x2003 0x0>;
 			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
 			qcom,iommu-faults = "stall-disable", "HUPCF";
-			dma-coherent;
+			dma-coherent-hint-cached;
 		};
 
 		qcom,msm_fastrpc_compute_cb11 {
@@ -1894,7 +1894,7 @@
 			iommus = <&apps_smmu 0x2004 0x0>;
 			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
 			qcom,iommu-faults = "stall-disable", "HUPCF";
-			dma-coherent;
+			dma-coherent-hint-cached;
 		};
 
 		qcom,msm_fastrpc_compute_cb12 {
@@ -1903,7 +1903,7 @@
 			iommus = <&apps_smmu 0x2005 0x0>;
 			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
 			qcom,iommu-faults = "stall-disable", "HUPCF";
-			dma-coherent;
+			dma-coherent-hint-cached;
 			shared-cb = <5>;
 		};
 
@@ -1914,7 +1914,7 @@
 					 <&apps_smmu 0x296B 0x0400>;
 			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
 			qcom,iommu-faults = "stall-disable", "HUPCF";
-			dma-coherent;
+			dma-coherent-hint-cached;
 		};
 
 		qcom,msm_fastrpc_compute_cb14 {
@@ -1924,7 +1924,7 @@
 					 <&apps_smmu 0x296C 0x0400>;
 			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
 			qcom,iommu-faults = "stall-disable", "HUPCF";
-			dma-coherent;
+			dma-coherent-hint-cached;
 		};
 
 		qcom,msm_fastrpc_compute_cb15 {
@@ -1934,7 +1934,7 @@
 					 <&apps_smmu 0x296D 0x0400>;
 			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
 			qcom,iommu-faults = "stall-disable", "HUPCF";
-			dma-coherent;
+			dma-coherent-hint-cached;
 		};
 
 		qcom,msm_fastrpc_compute_cb16 {
@@ -1944,7 +1944,7 @@
 					 <&apps_smmu 0x296E 0x0400>;
 			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
 			qcom,iommu-faults = "stall-disable", "HUPCF";
-			dma-coherent;
+			dma-coherent-hint-cached;
 		};
 	};