mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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MTD updates for 3.14:
- Add me (Brian Norris) as an additional MTD maintainer (it'd be nice to get
David's "ack" for this; I'm sure he approves, but he's been pretty silent
lately)
- Add Ezequiel Garcie as maintainer for the pxa3xx NAND driver
- Last (?) round of pxa3xx improvements for supporting Armada 370/XP
- Typical churn in driver boilerplate (OOM messages, printk()'s, devm_*, etc.)
- Quad read mode support for SPI NOR driver (m25p80)
- Update Davinci NAND driver to prepare for use on new platforms
- Begin to kill off NAND_MAX_{PAGE,OOB}SIZE macros; more work is pending
- Miscellaneous NAND device support (new IDs)
- Add READ RETRY support for Micron MLC NAND
- Support new GPMI NAND ECC layout device-tree binding
- Avoid mapping stack/vmalloc() memory for GPMI NAND DMA
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Merge tag 'for-linus-20140127' of git://git.infradead.org/linux-mtd
Pull MTD updates from Brian Norris:
- Add me (Brian Norris) as an additional MTD maintainer (it'd be nice to get
David's "ack" for this; I'm sure he approves, but he's been pretty silent
lately)
- Add Ezequiel Garcie as maintainer for the pxa3xx NAND driver
- Last (?) round of pxa3xx improvements for supporting Armada 370/XP
- Typical churn in driver boilerplate (OOM messages, printk()'s, devm_*, etc.)
- Quad read mode support for SPI NOR driver (m25p80)
- Update Davinci NAND driver to prepare for use on new platforms
- Begin to kill off NAND_MAX_{PAGE,OOB}SIZE macros; more work is pending
- Miscellaneous NAND device support (new IDs)
- Add READ RETRY support for Micron MLC NAND
- Support new GPMI NAND ECC layout device-tree binding
- Avoid mapping stack/vmalloc() memory for GPMI NAND DMA
* tag 'for-linus-20140127' of git://git.infradead.org/linux-mtd: (151 commits)
mtd: gpmi: add sanity check when mapping DMA for read_buf/write_buf
mtd: gpmi: allocate a proper buffer for non ECC read/write
mtd: m25p80: Set rx_nbits for Quad SPI transfers
mtd: m25p80: Enable Quad SPI read transfers for s25fl512s
mtd: s3c2410: Merge plat/regs-nand.h into s3c2410.c
mtd: mtdram: add missing 'const'
mtd: m25p80: assign default read command
mtd: nuc900_nand: remove redundant return value check of platform_get_resource()
mtd: plat_nand: remove redundant return value check of platform_get_resource()
mtd: nand: add Intel manufacturer ID
mtd: nand: add SanDisk manufacturer ID
mtd: nand: add support for Samsung K9LCG08U0B
mtd: nand: pxa3xx: Add support for 2048 bytes page size devices
mtd: m25p80: Use OPCODE_QUAD_READ_4B for 4-byte addressing
mtd: nand: don't use {read,write}_buf for 8-bit transfers
mtd: nand: use __packed shorthand
mtd: nand: support Micron READ RETRY
mtd: nand: add generic READ RETRY support
mtd: nand: add ONFI vendor block for Micron
mtd: nand: localize ECC failures per page
...
This commit is contained in:
Linus Torvalds
commit
0e47c969c6
76 changed files with 1688 additions and 1043 deletions
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@ -1,46 +0,0 @@
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* Texas Instruments Davinci NAND
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This file provides information, what the device node for the
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davinci nand interface contain.
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Required properties:
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- compatible: "ti,davinci-nand";
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- reg : contain 2 offset/length values:
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- offset and length for the access window
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- offset and length for accessing the aemif control registers
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- ti,davinci-chipselect: Indicates on the davinci_nand driver which
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chipselect is used for accessing the nand.
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Recommended properties :
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- ti,davinci-mask-ale: mask for ale
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- ti,davinci-mask-cle: mask for cle
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- ti,davinci-mask-chipsel: mask for chipselect
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- ti,davinci-ecc-mode: ECC mode valid values for davinci driver:
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- "none"
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- "soft"
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- "hw"
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- ti,davinci-ecc-bits: used ECC bits, currently supported 1 or 4.
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- ti,davinci-nand-buswidth: buswidth 8 or 16
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- ti,davinci-nand-use-bbt: use flash based bad block table support.
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nand device bindings may contain additional sub-nodes describing
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partitions of the address space. See partition.txt for more detail.
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Example(da850 EVM ):
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nand_cs3@62000000 {
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compatible = "ti,davinci-nand";
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reg = <0x62000000 0x807ff
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0x68000000 0x8000>;
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ti,davinci-chipselect = <1>;
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ti,davinci-mask-ale = <0>;
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ti,davinci-mask-cle = <0>;
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ti,davinci-mask-chipsel = <0>;
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ti,davinci-ecc-mode = "hw";
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ti,davinci-ecc-bits = <4>;
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ti,davinci-nand-use-bbt;
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partition@180000 {
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label = "ubifs";
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reg = <0x180000 0x7e80000>;
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};
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};
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94
Documentation/devicetree/bindings/mtd/davinci-nand.txt
Normal file
94
Documentation/devicetree/bindings/mtd/davinci-nand.txt
Normal file
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@ -0,0 +1,94 @@
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Device tree bindings for Texas instruments Davinci/Keystone NAND controller
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This file provides information, what the device node for the davinci/keystone
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NAND interface contains.
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Documentation:
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Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
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Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
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Required properties:
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- compatible: "ti,davinci-nand"
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"ti,keystone-nand"
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- reg: Contains 2 offset/length values:
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- offset and length for the access window.
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- offset and length for accessing the AEMIF
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control registers.
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- ti,davinci-chipselect: number of chipselect. Indicates on the
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davinci_nand driver which chipselect is used
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for accessing the nand.
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Can be in the range [0-3].
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Recommended properties :
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- ti,davinci-mask-ale: mask for ALE. Needed for executing address
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phase. These offset will be added to the base
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address for the chip select space the NAND Flash
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device is connected to.
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If not set equal to 0x08.
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- ti,davinci-mask-cle: mask for CLE. Needed for executing command
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phase. These offset will be added to the base
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address for the chip select space the NAND Flash
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device is connected to.
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If not set equal to 0x10.
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- ti,davinci-mask-chipsel: mask for chipselect address. Needed to mask
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addresses for given chipselect.
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- nand-ecc-mode: operation mode of the NAND ecc mode. ECC mode
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valid values for davinci driver:
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- "none"
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- "soft"
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- "hw"
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- ti,davinci-ecc-bits: used ECC bits, currently supported 1 or 4.
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- nand-bus-width: buswidth 8 or 16. If not present 8.
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- nand-on-flash-bbt: use flash based bad block table support. OOB
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identifier is saved in OOB area. If not present
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false.
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Deprecated properties:
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- ti,davinci-ecc-mode: operation mode of the NAND ecc mode. ECC mode
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valid values for davinci driver:
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- "none"
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- "soft"
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- "hw"
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- ti,davinci-nand-buswidth: buswidth 8 or 16. If not present 8.
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- ti,davinci-nand-use-bbt: use flash based bad block table support. OOB
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identifier is saved in OOB area. If not present
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false.
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Nand device bindings may contain additional sub-nodes describing partitions of
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the address space. See partition.txt for more detail. The NAND Flash timing
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values must be programmed in the chip select’s node of AEMIF
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memory-controller (see Documentation/devicetree/bindings/memory-controllers/
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davinci-aemif.txt).
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Example(da850 EVM ):
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nand_cs3@62000000 {
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compatible = "ti,davinci-nand";
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reg = <0x62000000 0x807ff
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0x68000000 0x8000>;
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ti,davinci-chipselect = <1>;
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ti,davinci-mask-ale = <0>;
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ti,davinci-mask-cle = <0>;
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ti,davinci-mask-chipsel = <0>;
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nand-ecc-mode = "hw";
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ti,davinci-ecc-bits = <4>;
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nand-on-flash-bbt;
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partition@180000 {
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label = "ubifs";
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reg = <0x180000 0x7e80000>;
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};
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};
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@ -17,6 +17,14 @@ Required properties:
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Optional properties:
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- nand-on-flash-bbt: boolean to enable on flash bbt option if not
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present false
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- fsl,use-minimum-ecc: Protect this NAND flash with the minimum ECC
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strength required. The required ECC strength is
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automatically discoverable for some flash
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(e.g., according to the ONFI standard).
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However, note that if this strength is not
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discoverable or this property is not enabled,
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the software may chooses an implementation-defined
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ECC scheme.
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The device tree may optionally contain sub-nodes describing partitions of the
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address space. See partition.txt for more detail.
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@ -2,7 +2,9 @@ PXA3xx NAND DT bindings
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Required properties:
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- compatible: Should be "marvell,pxa3xx-nand"
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- compatible: Should be set to one of the following:
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marvell,pxa3xx-nand
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marvell,armada370-nand
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- reg: The register base for the controller
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- interrupts: The interrupt to map
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- #address-cells: Set to <1> if the node includes partitions
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@ -13,6 +15,8 @@ Optional properties:
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- marvell,nand-keep-config: Set to keep the NAND controller config as set
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by the bootloader
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- num-cs: Number of chipselect lines to usw
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- nand-on-flash-bbt: boolean to enable on flash bbt option if
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not present false
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Example:
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