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msm: kgsl: Modify the a6xx interrupt mask for hwsched

Browse source 
With hardware scheduling, we only need to enable a subset
of interrupts as the rest of them are completely owned by
GMU.

Change-Id: I32afc4420299688b9a4322804ce972c79f1a7a22
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
This commit is contained in:
Harshdeep Dhatt 2020-07-23 13:19:24 -06:00
commit 0eb8eb4dcc
5 changed files with 33 additions and 18 deletions
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20
drivers/gpu/msm/adreno_a6xx.c
View file

@ -17,22 +17,6 @@
#include "adreno_trace.h"
#include "kgsl_trace.h"
#define A6XX_INT_MASK \
((1 << A6XX_INT_CP_AHB_ERROR) | \
(1 << A6XX_INT_ATB_ASYNCFIFO_OVERFLOW) | \
(1 << A6XX_INT_RBBM_GPC_ERROR) | \
(1 << A6XX_INT_CP_SW) | \
(1 << A6XX_INT_CP_HW_ERROR) | \
(1 << A6XX_INT_CP_IB2) | \
(1 << A6XX_INT_CP_IB1) | \
(1 << A6XX_INT_CP_RB) | \
(1 << A6XX_INT_CP_CACHE_FLUSH_TS) | \
(1 << A6XX_INT_RBBM_ATB_BUS_OVERFLOW) | \
(1 << A6XX_INT_RBBM_HANG_DETECT) | \
(1 << A6XX_INT_UCHE_OOB_ACCESS) | \
(1 << A6XX_INT_UCHE_TRAP_INTR) | \
(1 << A6XX_INT_TSB_WRITE_ERROR))
/* IFPC & Preemption static powerup restore list */
static u32 a6xx_pwrup_reglist[] = {
A6XX_VSC_ADDR_MODE_CNTL,
@ -439,8 +423,6 @@ void a6xx_start(struct adreno_device *adreno_dev)
unsigned int rgb565_predicator = 0;
static bool patch_reglist;
adreno_dev->irq_mask = A6XX_INT_MASK;
/* enable hardware clockgating */
a6xx_hwcg_set(adreno_dev, true);
@ -2532,6 +2514,8 @@ static int a6xx_probe(struct platform_device *pdev,
INIT_WORK(&device->idle_check_ws, kgsl_idle_check);
adreno_dev->irq_mask = A6XX_INT_MASK;
return 0;
}

25
drivers/gpu/msm/adreno_a6xx.h
View file

@ -186,6 +186,31 @@ struct cpu_gpu_lock {
/* Size of the CP_INIT pm4 stream in dwords */
#define A6XX_CP_INIT_DWORDS 12
#define A6XX_INT_MASK \
((1 << A6XX_INT_CP_AHB_ERROR) | \
(1 << A6XX_INT_ATB_ASYNCFIFO_OVERFLOW) | \
(1 << A6XX_INT_RBBM_GPC_ERROR) | \
(1 << A6XX_INT_CP_SW) | \
(1 << A6XX_INT_CP_HW_ERROR) | \
(1 << A6XX_INT_CP_IB2) | \
(1 << A6XX_INT_CP_IB1) | \
(1 << A6XX_INT_CP_RB) | \
(1 << A6XX_INT_CP_CACHE_FLUSH_TS) | \
(1 << A6XX_INT_RBBM_ATB_BUS_OVERFLOW) | \
(1 << A6XX_INT_RBBM_HANG_DETECT) | \
(1 << A6XX_INT_UCHE_OOB_ACCESS) | \
(1 << A6XX_INT_UCHE_TRAP_INTR) | \
(1 << A6XX_INT_TSB_WRITE_ERROR))
#define A6XX_HWSCHED_INT_MASK \
((1 << A6XX_INT_CP_AHB_ERROR) | \
(1 << A6XX_INT_ATB_ASYNCFIFO_OVERFLOW) | \
(1 << A6XX_INT_RBBM_GPC_ERROR) | \
(1 << A6XX_INT_RBBM_ATB_BUS_OVERFLOW) | \
(1 << A6XX_INT_UCHE_OOB_ACCESS) | \
(1 << A6XX_INT_UCHE_TRAP_INTR) | \
(1 << A6XX_INT_TSB_WRITE_ERROR))
/**
* to_a6xx_core - return the a6xx specific GPU core struct
* @adreno_dev: An Adreno GPU device handle

2
drivers/gpu/msm/adreno_a6xx_gmu.c
View file

@ -3333,6 +3333,8 @@ int a6xx_gmu_device_probe(struct platform_device *pdev,
timer_setup(&device->idle_timer, gmu_idle_timer, 0);
adreno_dev->irq_mask = A6XX_INT_MASK;
return 0;
}

2
drivers/gpu/msm/adreno_a6xx_hwsched.c
View file

@ -705,6 +705,8 @@ int a6xx_hwsched_probe(struct platform_device *pdev,
timer_setup(&device->idle_timer, hwsched_idle_timer, 0);
adreno_dev->irq_mask = A6XX_HWSCHED_INT_MASK;
return 0;
}

2
drivers/gpu/msm/adreno_a6xx_rgmu.c
View file

@ -1310,6 +1310,8 @@ int a6xx_rgmu_device_probe(struct platform_device *pdev,
timer_setup(&device->idle_timer, rgmu_idle_timer, 0);
adreno_dev->irq_mask = A6XX_INT_MASK;
return 0;
}