From d56d530e20ffbcdc47b7ecd24087a36dec59bd0b Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Wed, 17 Feb 2021 17:21:41 +0530 Subject: [PATCH 1/2] clk: qcom: clk-rcg2: Add enable & disable callbacks for RCG floor ops If enable safe config is true and a rate scaling request comes while RCG is in disabled state, RCG's new configuration update would be done as part of enabling the RCG. Hence add the enable and disable callbacks for floor ops to properly configure the RCG in all cases. Change-Id: I3621e0dd2cb948cb523cd85659d0de0359ba5829 Signed-off-by: Jagadeesh Kona --- drivers/clk/qcom/clk-rcg2.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index b1fb68752b5e..d1148af5eeb2 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -811,6 +811,8 @@ const struct clk_ops clk_rcg2_floor_ops = { .pre_rate_change = clk_pre_change_regmap, .post_rate_change = clk_post_change_regmap, .is_enabled = clk_rcg2_is_enabled, + .enable = clk_rcg2_enable, + .disable = clk_rcg2_disable, .get_parent = clk_rcg2_get_parent, .set_parent = clk_rcg2_set_parent, .recalc_rate = clk_rcg2_recalc_rate, From 441450beb0f2b73e740713391f3edee3886e4ecf Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Mon, 15 Feb 2021 14:53:11 +0530 Subject: [PATCH 2/2] clk: qcom: gcc-yupik: Use floor ops for SDCC clocks To avoid overclocking issues observed on few parts, use floor ops for SDCC clocks. Change-Id: Ib2aaf634e569a3550b0dcbae485caf13241d1210 Signed-off-by: Jagadeesh Kona --- drivers/clk/qcom/gcc-yupik.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/clk/qcom/gcc-yupik.c b/drivers/clk/qcom/gcc-yupik.c index 8f581e6ec90e..156cec510607 100644 --- a/drivers/clk/qcom/gcc-yupik.c +++ b/drivers/clk/qcom/gcc-yupik.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. */ #include @@ -1139,7 +1139,7 @@ static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { .name = "gcc_sdcc1_apps_clk_src", .parent_data = gcc_parent_data_8, .num_parents = ARRAY_SIZE(gcc_parent_data_8), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_floor_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_cx, @@ -1168,7 +1168,7 @@ static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { .name = "gcc_sdcc1_ice_core_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_floor_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_cx, @@ -1201,7 +1201,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { .name = "gcc_sdcc2_apps_clk_src", .parent_data = gcc_parent_data_9, .num_parents = ARRAY_SIZE(gcc_parent_data_9), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_floor_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_cx, @@ -1232,7 +1232,7 @@ static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { .name = "gcc_sdcc4_apps_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_floor_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_cx,