From 0f113bdb93b7cf2276e85037b138523338ff476b Mon Sep 17 00:00:00 2001 From: Narendra Muppalla Date: Thu, 5 Dec 2019 19:16:47 -0800 Subject: [PATCH] ARM: dts: msm: fix device tree for validating wb on lahaina This change adds gdsc voting from mdss_mdp until display rscc is enabled and also removes interface clocks until the dsi interface validation is completed. Change-Id: Ia2841b147fc9b71c2c20d6266b48f7f5ca5d4667 --- display/lahaina-sde-display-rumi.dtsi | 2 +- display/lahaina-sde-display.dtsi | 43 +-------------------------- display/lahaina-sde.dtsi | 36 +++++++++++----------- 3 files changed, 20 insertions(+), 61 deletions(-) diff --git a/display/lahaina-sde-display-rumi.dtsi b/display/lahaina-sde-display-rumi.dtsi index 3eb83e40a9c0..01d0c4119d6c 100644 --- a/display/lahaina-sde-display-rumi.dtsi +++ b/display/lahaina-sde-display-rumi.dtsi @@ -1 +1 @@ -#include "kona-sde-display.dtsi" +#include "lahaina-sde-display.dtsi" diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index a477f44fffc0..b2111479ca12 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -168,38 +168,12 @@ qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; - clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, - <&mdss_dsi0_pll PCLK_MUX_0_CLK>, - <&mdss_dsi0_pll BYTECLK_SRC_0_CLK>, - <&mdss_dsi0_pll PCLK_SRC_0_CLK>, - <&mdss_dsi0_pll SHADOW_BYTECLK_SRC_0_CLK>, - <&mdss_dsi0_pll SHADOW_PCLK_SRC_0_CLK>, - <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, - <&mdss_dsi1_pll PCLK_MUX_1_CLK>, - <&mdss_dsi1_pll BYTECLK_SRC_1_CLK>, - <&mdss_dsi1_pll PCLK_SRC_1_CLK>, - <&mdss_dsi1_pll SHADOW_BYTECLK_SRC_1_CLK>, - <&mdss_dsi1_pll SHADOW_PCLK_SRC_1_CLK>; - - clock-names = "mux_byte_clk0", "mux_pixel_clk0", - "src_byte_clk0", "src_pixel_clk0", - "shadow_byte_clk0", "shadow_pixel_clk0", - "mux_byte_clk1", "mux_pixel_clk1", - "src_byte_clk1", "src_pixel_clk1", - "shadow_byte_clk1", "shadow_pixel_clk1"; - pinctrl-names = "panel_active", "panel_suspend"; - pinctrl-0 = <&sde_dsi_active &sde_te_active>; - pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; qcom,platform-te-gpio = <&tlmm 66 0>; qcom,panel-te-source = <0>; - vddio-supply = <&pm8150_l14>; - vdd-supply = <&pm8150a_l11>; avdd-supply = <&display_panel_avdd>; - lab-supply = <&ab_vreg>; - ibb-supply = <&ibb_vreg>; qcom,mdp = <&mdss_mdp>; qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; @@ -212,22 +186,11 @@ qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; - clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, - <&mdss_dsi0_pll PCLK_MUX_0_CLK>, - <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, - <&mdss_dsi1_pll PCLK_MUX_1_CLK>; - clock-names = "mux_byte_clk0", "mux_pixel_clk0", - "mux_byte_clk1", "mux_pixel_clk1"; - pinctrl-names = "panel_active", "panel_suspend"; - pinctrl-0 = <&sde_dsi1_active &sde_te1_active>; - pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>; qcom,platform-te-gpio = <&tlmm 67 0>; qcom,panel-te-source = <1>; - vddio-supply = <&pm8150_l14>; - vdd-supply = <&pm8150a_l11>; avdd-supply = <&display_panel_avdd>; qcom,mdp = <&mdss_mdp>; @@ -241,19 +204,15 @@ }; &sde_dp { - qcom,dp-usbpd-detection = <&pm8150b_pdphy>; qcom,ext-disp = <&ext_disp>; - qcom,dp-aux-switch = <&fsa4480>; qcom,usbplug-cc-gpio = <&tlmm 65 0>; pinctrl-names = "mdss_dp_active", "mdss_dp_sleep"; - pinctrl-0 = <&sde_dp_usbplug_cc_active>; - pinctrl-1 = <&sde_dp_usbplug_cc_suspend>; }; &mdss_mdp { - connectors = <&sde_dp &sde_wb &sde_dsi &sde_dsi1 &sde_rscc>; + connectors = <&sde_wb>; }; /* PHY TIMINGS REVISION W */ diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index 095154242c23..064acfdf25bd 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -31,14 +31,13 @@ 460000000>; mmcx-supply = <&VDD_MMCX_LEVEL>; + vdd-supply = <&disp_cc_mdss_core_gdsc>; /* interrupt config */ interrupts = ; interrupt-controller; #interrupt-cells = <1>; - #power-domain-cells = <0>; - /* hw blocks */ qcom,sde-off = <0x1000>; qcom,sde-len = <0x494>; @@ -265,6 +264,15 @@ qcom,supply-enable-load = <0>; qcom,supply-disable-load = <0>; }; + + qcom,platform-supply-entry@1 { + reg = <0>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; }; smmu_sde_unsec: qcom,smmu_sde_unsec_cb { @@ -309,10 +317,7 @@ sde_dp: qcom,dp_display@ae90000 { cell-index = <0>; compatible = "qcom,dp-display"; - - vdda-1p2-supply = <&pm8150_l9>; - vdda-0p9-supply = <&pm8150_l18>; - + status = "disabled"; reg = <0xae90000 0x0dc>, <0xae90200 0x0c0>, @@ -341,15 +346,12 @@ <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>, <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, - <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>, <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>, - <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>, <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; clock-names = "core_aux_clk", "core_usb_ref_clk_src", "core_usb_pipe_clk", "link_clk", "link_iface_clk", - "pixel_clk_rcg", "pixel_parent", - "pixel1_clk_rcg", "pixel1_parent", + "pixel_clk_rcg", "pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk"; qcom,phy-version = <0x420>; @@ -419,6 +421,7 @@ sde_rscc: qcom,sde_rscc@af20000 { cell-index = <0>; compatible = "qcom,sde-rsc"; + status = "disabled"; reg = <0xaf20000 0x3c50>, <0xaf30000 0x3fd4>; reg-names = "drv", "wrapper"; @@ -426,7 +429,7 @@ qcom,sde-dram-channels = <2>; - vdd-supply = <&mdss_core_gdsc>; + vdd-supply = <&disp_cc_mdss_core_gdsc>; clocks = <&clock_dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>, <&clock_dispcc DISP_CC_MDSS_NON_GDSC_AHB_CLK>, @@ -490,7 +493,6 @@ <25 512 0 6400000>, <25 512 0 6400000>; - rot-vdd-supply = <&mdss_core_gdsc>; qcom,supply-names = "rot-vdd"; clocks = @@ -546,9 +548,8 @@ <0xaf08000 0x4>; reg-names = "dsi_ctrl", "disp_cc_base"; interrupt-parent = <&mdss_mdp>; + status = "disabled"; interrupts = <4 0>; - vdda-1p2-supply = <&pm8150_l9>; - refgen-supply = <&refgen>; clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK>, <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&clock_dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, @@ -596,9 +597,8 @@ <0xaf08000 0x4>; reg-names = "dsi_ctrl", "disp_cc_base"; interrupt-parent = <&mdss_mdp>; + status = "disabled"; interrupts = <5 0>; - vdda-1p2-supply = <&pm8150_l9>; - refgen-supply = <&refgen>; clocks = <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK>, <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&clock_dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, @@ -643,7 +643,7 @@ reg = <0xae94400 0x7c0>, <0xae94200 0x100>; reg-names = "dsi_phy", "dyn_refresh_base"; - vdda-0p9-supply = <&pm8150_l5>; + status = "disabled"; qcom,platform-strength-ctrl = [55 03 55 03 55 03 @@ -676,7 +676,7 @@ reg = <0xae96400 0x7c0>, <0xae96200 0x100>; reg-names = "dsi_phy", "dyn_refresh_base"; - vdda-0p9-supply = <&pm8150_l5>; + status = "disabled"; qcom,platform-strength-ctrl = [55 03 55 03 55 03