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ARM: mach-ux500: enable 128KB way L2 cache on DB8540

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DB8540 L2 was configured with 64KB way size, but it has 128KB as AP9540.

Fix this by modifying ux500_l2x0_init() to use 128KB way size for all
cpus in the x540 family.

Signed-off-by: Maxime Coquelin <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Signed-off-by: Fabio Baltieri <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>
This commit is contained in:
Maxime Coquelin 2013-01-23 11:27:58 +01:00 • committed by Linus Walleij
commit 0f2fa40e46
1 changed files with 2 additions and 2 deletions
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4
arch/arm/mach-ux500/cache-l2x0.c
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@ -47,8 +47,8 @@ static int __init ux500_l2x0_init(void)
/* Unlock before init */
ux500_l2x0_unlock();
/* DB9540's L2 has 128KB way size */
if (cpu_is_u9540())
/* DBx540's L2 has 128KB way size */
if (cpu_is_ux540_family())
/* 128KB way size */
aux_val |= (0x4 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT);
else