mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-30 03:27:44 -04:00
Merge branches 'pci/aspm', 'pci/enumeration', 'pci/hotplug', 'pci/misc', 'pci/msi', 'pci/resource' and 'pci/virtualization' into next
* pci/aspm: PCI/ASPM: Simplify Clock Power Management setting PCI: Use dev->has_secondary_link to find downstream PCIe links PCI/ASPM: Use dev->has_secondary_link to find downstream links PCI: Add dev->has_secondary_link to track downstream PCIe links PCI/ASPM: Remove redundant PCIe port type checking PCI/ASPM: Drop __pci_disable_link_state() useless "force" parameter * pci/enumeration: PCI: Remove unused pci_scan_bus_parented() xen/pcifront: Don't use deprecated function pci_scan_bus_parented() PCI: designware: Use pci_scan_root_bus() for simplicity PCI: tegra: Remove tegra_pcie_scan_bus() PCI: mvebu: Remove mvebu_pcie_scan_bus() * pci/hotplug: PCI: pciehp: Wait for hotplug command completion where necessary PCI: Propagate the "ignore hotplug" setting to parent ACPI / hotplug / PCI: Check ignore_hotplug for all downstream devices PCI: pciehp: Drop pointless label from pciehp_probe() PCI: pciehp: Drop pointless ACPI-based "slot detection" check * pci/misc: PCI: Remove unused pci_dma_burst_advice() PCI: Remove unused pcibios_select_root() (again) PCI: Remove unnecessary #includes of <asm/pci.h> PCI: Include <linux/pci.h>, not <asm/pci.h> * pci/msi: PCI/MSI: Remove unused pci_msi_off() PCI/MSI: Drop pci_msi_off() calls from quirks ntb: Drop pci_msi_off() call during probe virtio_pci: drop pci_msi_off() call during probe PCI/MSI: Disable MSI at enumeration even if kernel doesn't support MSI PCI/MSI: Export pci_msi_set_enable(), pci_msix_clear_and_set_ctrl() PCI/MSI: Rename msi_set_enable(), msix_clear_and_set_ctrl() * pci/resource: PCI: Add pci_bus_addr_t * pci/virtualization: ACPI / PCI: Account for ARI in _PRT lookups PCI: Move pci_ari_enabled() to global header PCI: Add function 1 DMA alias quirk for Marvell 9120 PCI: Add ACS quirks for Intel 9-series PCH root ports
This commit is contained in:
Bjorn Helgaas
commit
0ff9b9bad6
56 changed files with 250 additions and 692 deletions
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@ -1,6 +1,10 @@
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#
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# PCI configuration
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#
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config PCI_BUS_ADDR_T_64BIT
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def_bool y if (ARCH_DMA_ADDR_T_64BIT || 64BIT)
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depends on PCI
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config PCI_MSI
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bool "Message Signaled Interrupts (MSI and MSI-X)"
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depends on PCI
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@ -92,11 +92,11 @@ void pci_bus_remove_resources(struct pci_bus *bus)
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}
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static struct pci_bus_region pci_32_bit = {0, 0xffffffffULL};
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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#ifdef CONFIG_PCI_BUS_ADDR_T_64BIT
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static struct pci_bus_region pci_64_bit = {0,
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(dma_addr_t) 0xffffffffffffffffULL};
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static struct pci_bus_region pci_high = {(dma_addr_t) 0x100000000ULL,
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(dma_addr_t) 0xffffffffffffffffULL};
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(pci_bus_addr_t) 0xffffffffffffffffULL};
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static struct pci_bus_region pci_high = {(pci_bus_addr_t) 0x100000000ULL,
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(pci_bus_addr_t) 0xffffffffffffffffULL};
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#endif
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/*
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@ -200,7 +200,7 @@ int pci_bus_alloc_resource(struct pci_bus *bus, struct resource *res,
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resource_size_t),
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void *alignf_data)
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{
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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#ifdef CONFIG_PCI_BUS_ADDR_T_64BIT
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int rc;
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if (res->flags & IORESOURCE_MEM_64) {
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@ -751,21 +751,6 @@ static int mvebu_pcie_setup(int nr, struct pci_sys_data *sys)
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return 1;
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}
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static struct pci_bus *mvebu_pcie_scan_bus(int nr, struct pci_sys_data *sys)
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{
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struct mvebu_pcie *pcie = sys_to_pcie(sys);
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struct pci_bus *bus;
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bus = pci_create_root_bus(&pcie->pdev->dev, sys->busnr,
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&mvebu_pcie_ops, sys, &sys->resources);
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if (!bus)
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return NULL;
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pci_scan_child_bus(bus);
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return bus;
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}
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static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
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const struct resource *res,
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resource_size_t start,
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@ -809,12 +794,11 @@ static void mvebu_pcie_enable(struct mvebu_pcie *pcie)
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hw.nr_controllers = 1;
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hw.private_data = (void **)&pcie;
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hw.setup = mvebu_pcie_setup;
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hw.scan = mvebu_pcie_scan_bus;
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hw.map_irq = of_irq_parse_and_map_pci;
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hw.ops = &mvebu_pcie_ops;
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hw.align_resource = mvebu_pcie_align_resource;
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pci_common_init(&hw);
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pci_common_init_dev(&pcie->pdev->dev, &hw);
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}
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/*
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@ -630,21 +630,6 @@ static int tegra_pcie_map_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
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return irq;
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}
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static struct pci_bus *tegra_pcie_scan_bus(int nr, struct pci_sys_data *sys)
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{
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struct tegra_pcie *pcie = sys_to_pcie(sys);
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struct pci_bus *bus;
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bus = pci_create_root_bus(pcie->dev, sys->busnr, &tegra_pcie_ops, sys,
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&sys->resources);
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if (!bus)
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return NULL;
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pci_scan_child_bus(bus);
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return bus;
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}
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static irqreturn_t tegra_pcie_isr(int irq, void *arg)
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{
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const char *err_msg[] = {
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@ -1831,7 +1816,6 @@ static int tegra_pcie_enable(struct tegra_pcie *pcie)
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hw.private_data = (void **)&pcie;
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hw.setup = tegra_pcie_setup;
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hw.map_irq = tegra_pcie_map_irq;
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hw.scan = tegra_pcie_scan_bus;
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hw.ops = &tegra_pcie_ops;
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pci_common_init_dev(pcie->dev, &hw);
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@ -728,13 +728,11 @@ static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys)
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struct pcie_port *pp = sys_to_pcie(sys);
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pp->root_bus_nr = sys->busnr;
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bus = pci_create_root_bus(pp->dev, sys->busnr,
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bus = pci_scan_root_bus(pp->dev, sys->busnr,
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&dw_pcie_ops, sys, &sys->resources);
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if (!bus)
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return NULL;
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pci_scan_child_bus(bus);
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if (bus && pp->ops->scan_bus)
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pp->ops->scan_bus(pp);
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@ -61,9 +61,6 @@ pciehp-objs := pciehp_core.o \
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pciehp_ctrl.o \
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pciehp_pci.o \
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pciehp_hpc.o
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ifdef CONFIG_ACPI
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pciehp-objs += pciehp_acpi.o
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endif
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shpchp-objs := shpchp_core.o \
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shpchp_ctrl.o \
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@ -632,15 +632,14 @@ static void trim_stale_devices(struct pci_dev *dev)
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{
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struct acpi_device *adev = ACPI_COMPANION(&dev->dev);
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struct pci_bus *bus = dev->subordinate;
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bool alive = false;
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bool alive = dev->ignore_hotplug;
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if (adev) {
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acpi_status status;
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unsigned long long sta;
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status = acpi_evaluate_integer(adev->handle, "_STA", NULL, &sta);
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alive = (ACPI_SUCCESS(status) && device_status_valid(sta))
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|| dev->ignore_hotplug;
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alive = alive || (ACPI_SUCCESS(status) && device_status_valid(sta));
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}
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if (!alive)
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alive = pci_device_is_present(dev);
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@ -167,21 +167,4 @@ static inline const char *slot_name(struct slot *slot)
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return hotplug_slot_name(slot->hotplug_slot);
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}
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#ifdef CONFIG_ACPI
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#include <linux/pci-acpi.h>
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void __init pciehp_acpi_slot_detection_init(void);
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int pciehp_acpi_slot_detection_check(struct pci_dev *dev);
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static inline void pciehp_firmware_init(void)
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{
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pciehp_acpi_slot_detection_init();
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}
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#else
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#define pciehp_firmware_init() do {} while (0)
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static inline int pciehp_acpi_slot_detection_check(struct pci_dev *dev)
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{
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return 0;
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}
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#endif /* CONFIG_ACPI */
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#endif /* _PCIEHP_H */
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@ -1,137 +0,0 @@
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/*
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* ACPI related functions for PCI Express Hot Plug driver.
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*
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* Copyright (C) 2008 Kenji Kaneshige
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* Copyright (C) 2008 Fujitsu Limited.
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*
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or (at
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* your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#include <linux/acpi.h>
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#include <linux/pci.h>
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#include <linux/pci_hotplug.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include "pciehp.h"
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#define PCIEHP_DETECT_PCIE (0)
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#define PCIEHP_DETECT_ACPI (1)
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#define PCIEHP_DETECT_AUTO (2)
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#define PCIEHP_DETECT_DEFAULT PCIEHP_DETECT_AUTO
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struct dummy_slot {
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u32 number;
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struct list_head list;
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};
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static int slot_detection_mode;
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static char *pciehp_detect_mode;
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module_param(pciehp_detect_mode, charp, 0444);
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MODULE_PARM_DESC(pciehp_detect_mode,
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"Slot detection mode: pcie, acpi, auto\n"
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" pcie - Use PCIe based slot detection\n"
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" acpi - Use ACPI for slot detection\n"
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" auto(default) - Auto select mode. Use acpi option if duplicate\n"
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" slot ids are found. Otherwise, use pcie option\n");
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int pciehp_acpi_slot_detection_check(struct pci_dev *dev)
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{
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if (slot_detection_mode != PCIEHP_DETECT_ACPI)
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return 0;
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if (acpi_pci_detect_ejectable(ACPI_HANDLE(&dev->dev)))
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return 0;
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return -ENODEV;
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}
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static int __init parse_detect_mode(void)
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{
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if (!pciehp_detect_mode)
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return PCIEHP_DETECT_DEFAULT;
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if (!strcmp(pciehp_detect_mode, "pcie"))
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return PCIEHP_DETECT_PCIE;
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if (!strcmp(pciehp_detect_mode, "acpi"))
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return PCIEHP_DETECT_ACPI;
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if (!strcmp(pciehp_detect_mode, "auto"))
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return PCIEHP_DETECT_AUTO;
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warn("bad specifier '%s' for pciehp_detect_mode. Use default\n",
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pciehp_detect_mode);
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return PCIEHP_DETECT_DEFAULT;
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}
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static int __initdata dup_slot_id;
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static int __initdata acpi_slot_detected;
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static struct list_head __initdata dummy_slots = LIST_HEAD_INIT(dummy_slots);
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/* Dummy driver for duplicate name detection */
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static int __init dummy_probe(struct pcie_device *dev)
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{
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u32 slot_cap;
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acpi_handle handle;
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struct dummy_slot *slot, *tmp;
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struct pci_dev *pdev = dev->port;
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pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
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slot = kzalloc(sizeof(*slot), GFP_KERNEL);
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if (!slot)
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return -ENOMEM;
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slot->number = (slot_cap & PCI_EXP_SLTCAP_PSN) >> 19;
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list_for_each_entry(tmp, &dummy_slots, list) {
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if (tmp->number == slot->number)
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dup_slot_id++;
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}
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list_add_tail(&slot->list, &dummy_slots);
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handle = ACPI_HANDLE(&pdev->dev);
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if (!acpi_slot_detected && acpi_pci_detect_ejectable(handle))
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acpi_slot_detected = 1;
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return -ENODEV; /* dummy driver always returns error */
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}
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|
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static struct pcie_port_service_driver __initdata dummy_driver = {
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.name = "pciehp_dummy",
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.port_type = PCIE_ANY_PORT,
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.service = PCIE_PORT_SERVICE_HP,
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.probe = dummy_probe,
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};
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static int __init select_detection_mode(void)
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{
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struct dummy_slot *slot, *tmp;
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|
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if (pcie_port_service_register(&dummy_driver))
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return PCIEHP_DETECT_ACPI;
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pcie_port_service_unregister(&dummy_driver);
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list_for_each_entry_safe(slot, tmp, &dummy_slots, list) {
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list_del(&slot->list);
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kfree(slot);
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}
|
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if (acpi_slot_detected && dup_slot_id)
|
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return PCIEHP_DETECT_ACPI;
|
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return PCIEHP_DETECT_PCIE;
|
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}
|
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|
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void __init pciehp_acpi_slot_detection_init(void)
|
||||
{
|
||||
slot_detection_mode = parse_detect_mode();
|
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if (slot_detection_mode != PCIEHP_DETECT_AUTO)
|
||||
goto out;
|
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slot_detection_mode = select_detection_mode();
|
||||
out:
|
||||
if (slot_detection_mode == PCIEHP_DETECT_ACPI)
|
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info("Using ACPI for slot detection.\n");
|
||||
}
|
||||
|
|
@ -248,24 +248,21 @@ static int pciehp_probe(struct pcie_device *dev)
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|||
struct slot *slot;
|
||||
u8 occupied, poweron;
|
||||
|
||||
if (pciehp_force)
|
||||
dev_info(&dev->device,
|
||||
"Bypassing BIOS check for pciehp use on %s\n",
|
||||
pci_name(dev->port));
|
||||
else if (pciehp_acpi_slot_detection_check(dev->port))
|
||||
goto err_out_none;
|
||||
/* If this is not a "hotplug" service, we have no business here. */
|
||||
if (dev->service != PCIE_PORT_SERVICE_HP)
|
||||
return -ENODEV;
|
||||
|
||||
if (!dev->port->subordinate) {
|
||||
/* Can happen if we run out of bus numbers during probe */
|
||||
dev_err(&dev->device,
|
||||
"Hotplug bridge without secondary bus, ignoring\n");
|
||||
goto err_out_none;
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
ctrl = pcie_init(dev);
|
||||
if (!ctrl) {
|
||||
dev_err(&dev->device, "Controller initialization failed\n");
|
||||
goto err_out_none;
|
||||
return -ENODEV;
|
||||
}
|
||||
set_service_data(dev, ctrl);
|
||||
|
||||
|
|
@ -305,7 +302,6 @@ err_out_free_ctrl_slot:
|
|||
cleanup_slot(ctrl);
|
||||
err_out_release_ctlr:
|
||||
pciehp_release_ctrl(ctrl);
|
||||
err_out_none:
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
|
|
@ -366,7 +362,6 @@ static int __init pcied_init(void)
|
|||
{
|
||||
int retval = 0;
|
||||
|
||||
pciehp_firmware_init();
|
||||
retval = pcie_port_service_register(&hpdriver_portdrv);
|
||||
dbg("pcie_port_service_register = %d\n", retval);
|
||||
info(DRIVER_DESC " version: " DRIVER_VERSION "\n");
|
||||
|
|
|
|||
|
|
@ -176,20 +176,17 @@ static void pcie_wait_cmd(struct controller *ctrl)
|
|||
jiffies_to_msecs(jiffies - ctrl->cmd_started));
|
||||
}
|
||||
|
||||
/**
|
||||
* pcie_write_cmd - Issue controller command
|
||||
* @ctrl: controller to which the command is issued
|
||||
* @cmd: command value written to slot control register
|
||||
* @mask: bitmask of slot control register to be modified
|
||||
*/
|
||||
static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
|
||||
static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd,
|
||||
u16 mask, bool wait)
|
||||
{
|
||||
struct pci_dev *pdev = ctrl_dev(ctrl);
|
||||
u16 slot_ctrl;
|
||||
|
||||
mutex_lock(&ctrl->ctrl_lock);
|
||||
|
||||
/* Wait for any previous command that might still be in progress */
|
||||
/*
|
||||
* Always wait for any previous command that might still be in progress
|
||||
*/
|
||||
pcie_wait_cmd(ctrl);
|
||||
|
||||
pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
|
||||
|
|
@ -201,9 +198,33 @@ static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
|
|||
ctrl->cmd_started = jiffies;
|
||||
ctrl->slot_ctrl = slot_ctrl;
|
||||
|
||||
/*
|
||||
* Optionally wait for the hardware to be ready for a new command,
|
||||
* indicating completion of the above issued command.
|
||||
*/
|
||||
if (wait)
|
||||
pcie_wait_cmd(ctrl);
|
||||
|
||||
mutex_unlock(&ctrl->ctrl_lock);
|
||||
}
|
||||
|
||||
/**
|
||||
* pcie_write_cmd - Issue controller command
|
||||
* @ctrl: controller to which the command is issued
|
||||
* @cmd: command value written to slot control register
|
||||
* @mask: bitmask of slot control register to be modified
|
||||
*/
|
||||
static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
|
||||
{
|
||||
pcie_do_write_cmd(ctrl, cmd, mask, true);
|
||||
}
|
||||
|
||||
/* Same as above without waiting for the hardware to latch */
|
||||
static void pcie_write_cmd_nowait(struct controller *ctrl, u16 cmd, u16 mask)
|
||||
{
|
||||
pcie_do_write_cmd(ctrl, cmd, mask, false);
|
||||
}
|
||||
|
||||
bool pciehp_check_link_active(struct controller *ctrl)
|
||||
{
|
||||
struct pci_dev *pdev = ctrl_dev(ctrl);
|
||||
|
|
@ -422,7 +443,7 @@ void pciehp_set_attention_status(struct slot *slot, u8 value)
|
|||
default:
|
||||
return;
|
||||
}
|
||||
pcie_write_cmd(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC);
|
||||
pcie_write_cmd_nowait(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC);
|
||||
ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
|
||||
pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
|
||||
}
|
||||
|
|
@ -434,7 +455,8 @@ void pciehp_green_led_on(struct slot *slot)
|
|||
if (!PWR_LED(ctrl))
|
||||
return;
|
||||
|
||||
pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_ON, PCI_EXP_SLTCTL_PIC);
|
||||
pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_ON,
|
||||
PCI_EXP_SLTCTL_PIC);
|
||||
ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
|
||||
pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
|
||||
PCI_EXP_SLTCTL_PWR_IND_ON);
|
||||
|
|
@ -447,7 +469,8 @@ void pciehp_green_led_off(struct slot *slot)
|
|||
if (!PWR_LED(ctrl))
|
||||
return;
|
||||
|
||||
pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF, PCI_EXP_SLTCTL_PIC);
|
||||
pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF,
|
||||
PCI_EXP_SLTCTL_PIC);
|
||||
ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
|
||||
pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
|
||||
PCI_EXP_SLTCTL_PWR_IND_OFF);
|
||||
|
|
@ -460,7 +483,8 @@ void pciehp_green_led_blink(struct slot *slot)
|
|||
if (!PWR_LED(ctrl))
|
||||
return;
|
||||
|
||||
pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK, PCI_EXP_SLTCTL_PIC);
|
||||
pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK,
|
||||
PCI_EXP_SLTCTL_PIC);
|
||||
ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
|
||||
pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
|
||||
PCI_EXP_SLTCTL_PWR_IND_BLINK);
|
||||
|
|
@ -613,7 +637,7 @@ void pcie_enable_notification(struct controller *ctrl)
|
|||
PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
|
||||
PCI_EXP_SLTCTL_DLLSCE);
|
||||
|
||||
pcie_write_cmd(ctrl, cmd, mask);
|
||||
pcie_write_cmd_nowait(ctrl, cmd, mask);
|
||||
ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
|
||||
pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
|
||||
}
|
||||
|
|
@ -664,7 +688,7 @@ int pciehp_reset_slot(struct slot *slot, int probe)
|
|||
pci_reset_bridge_secondary_bus(ctrl->pcie->port);
|
||||
|
||||
pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask);
|
||||
pcie_write_cmd(ctrl, ctrl_mask, ctrl_mask);
|
||||
pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask);
|
||||
ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
|
||||
pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask);
|
||||
if (pciehp_poll_mode)
|
||||
|
|
|
|||
|
|
@ -185,27 +185,6 @@ void __weak arch_restore_msi_irqs(struct pci_dev *dev)
|
|||
return default_restore_msi_irqs(dev);
|
||||
}
|
||||
|
||||
static void msi_set_enable(struct pci_dev *dev, int enable)
|
||||
{
|
||||
u16 control;
|
||||
|
||||
pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
|
||||
control &= ~PCI_MSI_FLAGS_ENABLE;
|
||||
if (enable)
|
||||
control |= PCI_MSI_FLAGS_ENABLE;
|
||||
pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
|
||||
}
|
||||
|
||||
static void msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
|
||||
{
|
||||
u16 ctrl;
|
||||
|
||||
pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
|
||||
ctrl &= ~clear;
|
||||
ctrl |= set;
|
||||
pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
|
||||
}
|
||||
|
||||
static inline __attribute_const__ u32 msi_mask(unsigned x)
|
||||
{
|
||||
/* Don't shift by >= width of type */
|
||||
|
|
@ -452,7 +431,7 @@ static void __pci_restore_msi_state(struct pci_dev *dev)
|
|||
entry = irq_get_msi_desc(dev->irq);
|
||||
|
||||
pci_intx_for_msi(dev, 0);
|
||||
msi_set_enable(dev, 0);
|
||||
pci_msi_set_enable(dev, 0);
|
||||
arch_restore_msi_irqs(dev);
|
||||
|
||||
pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
|
||||
|
|
@ -473,14 +452,14 @@ static void __pci_restore_msix_state(struct pci_dev *dev)
|
|||
|
||||
/* route the table */
|
||||
pci_intx_for_msi(dev, 0);
|
||||
msix_clear_and_set_ctrl(dev, 0,
|
||||
pci_msix_clear_and_set_ctrl(dev, 0,
|
||||
PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL);
|
||||
|
||||
arch_restore_msi_irqs(dev);
|
||||
list_for_each_entry(entry, &dev->msi_list, list)
|
||||
msix_mask_irq(entry, entry->masked);
|
||||
|
||||
msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
|
||||
pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
|
||||
}
|
||||
|
||||
void pci_restore_msi_state(struct pci_dev *dev)
|
||||
|
|
@ -647,7 +626,7 @@ static int msi_capability_init(struct pci_dev *dev, int nvec)
|
|||
int ret;
|
||||
unsigned mask;
|
||||
|
||||
msi_set_enable(dev, 0); /* Disable MSI during set up */
|
||||
pci_msi_set_enable(dev, 0); /* Disable MSI during set up */
|
||||
|
||||
entry = msi_setup_entry(dev, nvec);
|
||||
if (!entry)
|
||||
|
|
@ -683,7 +662,7 @@ static int msi_capability_init(struct pci_dev *dev, int nvec)
|
|||
|
||||
/* Set MSI enabled bits */
|
||||
pci_intx_for_msi(dev, 0);
|
||||
msi_set_enable(dev, 1);
|
||||
pci_msi_set_enable(dev, 1);
|
||||
dev->msi_enabled = 1;
|
||||
|
||||
dev->irq = entry->irq;
|
||||
|
|
@ -775,7 +754,7 @@ static int msix_capability_init(struct pci_dev *dev,
|
|||
void __iomem *base;
|
||||
|
||||
/* Ensure MSI-X is disabled while it is set up */
|
||||
msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
|
||||
pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
|
||||
|
||||
pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
|
||||
/* Request & Map MSI-X table region */
|
||||
|
|
@ -801,7 +780,7 @@ static int msix_capability_init(struct pci_dev *dev,
|
|||
* MSI-X registers. We need to mask all the vectors to prevent
|
||||
* interrupts coming in before they're fully set up.
|
||||
*/
|
||||
msix_clear_and_set_ctrl(dev, 0,
|
||||
pci_msix_clear_and_set_ctrl(dev, 0,
|
||||
PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE);
|
||||
|
||||
msix_program_entries(dev, entries);
|
||||
|
|
@ -814,7 +793,7 @@ static int msix_capability_init(struct pci_dev *dev,
|
|||
pci_intx_for_msi(dev, 0);
|
||||
dev->msix_enabled = 1;
|
||||
|
||||
msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
|
||||
pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
|
||||
|
||||
return 0;
|
||||
|
||||
|
|
@ -919,7 +898,7 @@ void pci_msi_shutdown(struct pci_dev *dev)
|
|||
BUG_ON(list_empty(&dev->msi_list));
|
||||
desc = list_first_entry(&dev->msi_list, struct msi_desc, list);
|
||||
|
||||
msi_set_enable(dev, 0);
|
||||
pci_msi_set_enable(dev, 0);
|
||||
pci_intx_for_msi(dev, 1);
|
||||
dev->msi_enabled = 0;
|
||||
|
||||
|
|
@ -1027,7 +1006,7 @@ void pci_msix_shutdown(struct pci_dev *dev)
|
|||
__pci_msix_desc_mask_irq(entry, 1);
|
||||
}
|
||||
|
||||
msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
|
||||
pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
|
||||
pci_intx_for_msi(dev, 1);
|
||||
dev->msix_enabled = 0;
|
||||
}
|
||||
|
|
@ -1062,18 +1041,6 @@ EXPORT_SYMBOL(pci_msi_enabled);
|
|||
void pci_msi_init_pci_dev(struct pci_dev *dev)
|
||||
{
|
||||
INIT_LIST_HEAD(&dev->msi_list);
|
||||
|
||||
/* Disable the msi hardware to avoid screaming interrupts
|
||||
* during boot. This is the power on reset default so
|
||||
* usually this should be a noop.
|
||||
*/
|
||||
dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
|
||||
if (dev->msi_cap)
|
||||
msi_set_enable(dev, 0);
|
||||
|
||||
dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
|
||||
if (dev->msix_cap)
|
||||
msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -3101,39 +3101,6 @@ bool pci_check_and_unmask_intx(struct pci_dev *dev)
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
|
||||
|
||||
/**
|
||||
* pci_msi_off - disables any MSI or MSI-X capabilities
|
||||
* @dev: the PCI device to operate on
|
||||
*
|
||||
* If you want to use MSI, see pci_enable_msi() and friends.
|
||||
* This is a lower-level primitive that allows us to disable
|
||||
* MSI operation at the device level.
|
||||
*/
|
||||
void pci_msi_off(struct pci_dev *dev)
|
||||
{
|
||||
int pos;
|
||||
u16 control;
|
||||
|
||||
/*
|
||||
* This looks like it could go in msi.c, but we need it even when
|
||||
* CONFIG_PCI_MSI=n. For the same reason, we can't use
|
||||
* dev->msi_cap or dev->msix_cap here.
|
||||
*/
|
||||
pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
|
||||
if (pos) {
|
||||
pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
|
||||
control &= ~PCI_MSI_FLAGS_ENABLE;
|
||||
pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
|
||||
}
|
||||
pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
|
||||
if (pos) {
|
||||
pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
|
||||
control &= ~PCI_MSIX_FLAGS_ENABLE;
|
||||
pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_msi_off);
|
||||
|
||||
int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
|
||||
{
|
||||
return dma_set_max_seg_size(&dev->dev, size);
|
||||
|
|
@ -4324,6 +4291,17 @@ bool pci_device_is_present(struct pci_dev *pdev)
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(pci_device_is_present);
|
||||
|
||||
void pci_ignore_hotplug(struct pci_dev *dev)
|
||||
{
|
||||
struct pci_dev *bridge = dev->bus->self;
|
||||
|
||||
dev->ignore_hotplug = 1;
|
||||
/* Propagate the "ignore hotplug" setting to the parent bridge. */
|
||||
if (bridge)
|
||||
bridge->ignore_hotplug = 1;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_ignore_hotplug);
|
||||
|
||||
#define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
|
||||
static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
|
||||
static DEFINE_SPINLOCK(resource_alignment_lock);
|
||||
|
|
|
|||
|
|
@ -146,6 +146,27 @@ static inline void pci_no_msi(void) { }
|
|||
static inline void pci_msi_init_pci_dev(struct pci_dev *dev) { }
|
||||
#endif
|
||||
|
||||
static inline void pci_msi_set_enable(struct pci_dev *dev, int enable)
|
||||
{
|
||||
u16 control;
|
||||
|
||||
pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
|
||||
control &= ~PCI_MSI_FLAGS_ENABLE;
|
||||
if (enable)
|
||||
control |= PCI_MSI_FLAGS_ENABLE;
|
||||
pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
|
||||
}
|
||||
|
||||
static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
|
||||
{
|
||||
u16 ctrl;
|
||||
|
||||
pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
|
||||
ctrl &= ~clear;
|
||||
ctrl |= set;
|
||||
pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
|
||||
}
|
||||
|
||||
void pci_realloc_get_opt(char *);
|
||||
|
||||
static inline int pci_no_d1d2(struct pci_dev *dev)
|
||||
|
|
@ -216,17 +237,6 @@ void __pci_bus_assign_resources(const struct pci_bus *bus,
|
|||
struct list_head *fail_head);
|
||||
bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
|
||||
|
||||
/**
|
||||
* pci_ari_enabled - query ARI forwarding status
|
||||
* @bus: the PCI bus
|
||||
*
|
||||
* Returns 1 if ARI forwarding is enabled, or 0 if not enabled;
|
||||
*/
|
||||
static inline int pci_ari_enabled(struct pci_bus *bus)
|
||||
{
|
||||
return bus->self && bus->self->ari_enabled;
|
||||
}
|
||||
|
||||
void pci_reassigndev_resource_alignment(struct pci_dev *dev);
|
||||
void pci_disable_bridge_window(struct pci_dev *dev);
|
||||
|
||||
|
|
|
|||
|
|
@ -425,8 +425,7 @@ static pci_ers_result_t reset_link(struct pci_dev *dev)
|
|||
|
||||
if (driver && driver->reset_link) {
|
||||
status = driver->reset_link(udev);
|
||||
} else if (pci_pcie_type(udev) == PCI_EXP_TYPE_DOWNSTREAM ||
|
||||
pci_pcie_type(udev) == PCI_EXP_TYPE_ROOT_PORT) {
|
||||
} else if (udev->has_secondary_link) {
|
||||
status = default_reset_link(udev);
|
||||
} else {
|
||||
dev_printk(KERN_DEBUG, &dev->dev,
|
||||
|
|
|
|||
|
|
@ -127,15 +127,12 @@ static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable)
|
|||
{
|
||||
struct pci_dev *child;
|
||||
struct pci_bus *linkbus = link->pdev->subordinate;
|
||||
u32 val = enable ? PCI_EXP_LNKCTL_CLKREQ_EN : 0;
|
||||
|
||||
list_for_each_entry(child, &linkbus->devices, bus_list) {
|
||||
if (enable)
|
||||
pcie_capability_set_word(child, PCI_EXP_LNKCTL,
|
||||
PCI_EXP_LNKCTL_CLKREQ_EN);
|
||||
else
|
||||
pcie_capability_clear_word(child, PCI_EXP_LNKCTL,
|
||||
PCI_EXP_LNKCTL_CLKREQ_EN);
|
||||
}
|
||||
list_for_each_entry(child, &linkbus->devices, bus_list)
|
||||
pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
|
||||
PCI_EXP_LNKCTL_CLKREQ_EN,
|
||||
val);
|
||||
link->clkpm_enabled = !!enable;
|
||||
}
|
||||
|
||||
|
|
@ -525,7 +522,7 @@ static struct pcie_link_state *alloc_pcie_link_state(struct pci_dev *pdev)
|
|||
INIT_LIST_HEAD(&link->children);
|
||||
INIT_LIST_HEAD(&link->link);
|
||||
link->pdev = pdev;
|
||||
if (pci_pcie_type(pdev) == PCI_EXP_TYPE_DOWNSTREAM) {
|
||||
if (pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT) {
|
||||
struct pcie_link_state *parent;
|
||||
parent = pdev->bus->parent->self->link_state;
|
||||
if (!parent) {
|
||||
|
|
@ -559,10 +556,15 @@ void pcie_aspm_init_link_state(struct pci_dev *pdev)
|
|||
if (!aspm_support_enabled)
|
||||
return;
|
||||
|
||||
if (!pci_is_pcie(pdev) || pdev->link_state)
|
||||
if (pdev->link_state)
|
||||
return;
|
||||
if (pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT &&
|
||||
pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM)
|
||||
|
||||
/*
|
||||
* We allocate pcie_link_state for the component on the upstream
|
||||
* end of a Link, so there's nothing to do unless this device has a
|
||||
* Link on its secondary side.
|
||||
*/
|
||||
if (!pdev->has_secondary_link)
|
||||
return;
|
||||
|
||||
/* VIA has a strange chipset, root port is under a bridge */
|
||||
|
|
@ -675,10 +677,7 @@ void pcie_aspm_pm_state_change(struct pci_dev *pdev)
|
|||
{
|
||||
struct pcie_link_state *link = pdev->link_state;
|
||||
|
||||
if (aspm_disabled || !pci_is_pcie(pdev) || !link)
|
||||
return;
|
||||
if ((pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT) &&
|
||||
(pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM))
|
||||
if (aspm_disabled || !link)
|
||||
return;
|
||||
/*
|
||||
* Devices changed PM state, we should recheck if latency
|
||||
|
|
@ -696,16 +695,12 @@ void pcie_aspm_powersave_config_link(struct pci_dev *pdev)
|
|||
{
|
||||
struct pcie_link_state *link = pdev->link_state;
|
||||
|
||||
if (aspm_disabled || !pci_is_pcie(pdev) || !link)
|
||||
if (aspm_disabled || !link)
|
||||
return;
|
||||
|
||||
if (aspm_policy != POLICY_POWERSAVE)
|
||||
return;
|
||||
|
||||
if ((pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT) &&
|
||||
(pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM))
|
||||
return;
|
||||
|
||||
down_read(&pci_bus_sem);
|
||||
mutex_lock(&aspm_lock);
|
||||
pcie_config_aspm_path(link);
|
||||
|
|
@ -714,8 +709,7 @@ void pcie_aspm_powersave_config_link(struct pci_dev *pdev)
|
|||
up_read(&pci_bus_sem);
|
||||
}
|
||||
|
||||
static void __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem,
|
||||
bool force)
|
||||
static void __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem)
|
||||
{
|
||||
struct pci_dev *parent = pdev->bus->self;
|
||||
struct pcie_link_state *link;
|
||||
|
|
@ -723,8 +717,7 @@ static void __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem,
|
|||
if (!pci_is_pcie(pdev))
|
||||
return;
|
||||
|
||||
if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT ||
|
||||
pci_pcie_type(pdev) == PCI_EXP_TYPE_DOWNSTREAM)
|
||||
if (pdev->has_secondary_link)
|
||||
parent = pdev;
|
||||
if (!parent || !parent->link_state)
|
||||
return;
|
||||
|
|
@ -737,7 +730,7 @@ static void __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem,
|
|||
* a similar mechanism using "PciASPMOptOut", which is also
|
||||
* ignored in this situation.
|
||||
*/
|
||||
if (aspm_disabled && !force) {
|
||||
if (aspm_disabled) {
|
||||
dev_warn(&pdev->dev, "can't disable ASPM; OS doesn't have ASPM control\n");
|
||||
return;
|
||||
}
|
||||
|
|
@ -763,7 +756,7 @@ static void __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem,
|
|||
|
||||
void pci_disable_link_state_locked(struct pci_dev *pdev, int state)
|
||||
{
|
||||
__pci_disable_link_state(pdev, state, false, false);
|
||||
__pci_disable_link_state(pdev, state, false);
|
||||
}
|
||||
EXPORT_SYMBOL(pci_disable_link_state_locked);
|
||||
|
||||
|
|
@ -778,7 +771,7 @@ EXPORT_SYMBOL(pci_disable_link_state_locked);
|
|||
*/
|
||||
void pci_disable_link_state(struct pci_dev *pdev, int state)
|
||||
{
|
||||
__pci_disable_link_state(pdev, state, true, false);
|
||||
__pci_disable_link_state(pdev, state, true);
|
||||
}
|
||||
EXPORT_SYMBOL(pci_disable_link_state);
|
||||
|
||||
|
|
@ -907,9 +900,7 @@ void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev)
|
|||
{
|
||||
struct pcie_link_state *link_state = pdev->link_state;
|
||||
|
||||
if (!pci_is_pcie(pdev) ||
|
||||
(pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT &&
|
||||
pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM) || !link_state)
|
||||
if (!link_state)
|
||||
return;
|
||||
|
||||
if (link_state->aspm_support)
|
||||
|
|
@ -924,9 +915,7 @@ void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev)
|
|||
{
|
||||
struct pcie_link_state *link_state = pdev->link_state;
|
||||
|
||||
if (!pci_is_pcie(pdev) ||
|
||||
(pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT &&
|
||||
pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM) || !link_state)
|
||||
if (!link_state)
|
||||
return;
|
||||
|
||||
if (link_state->aspm_support)
|
||||
|
|
|
|||
|
|
@ -254,8 +254,8 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
|
|||
}
|
||||
|
||||
if (res->flags & IORESOURCE_MEM_64) {
|
||||
if ((sizeof(dma_addr_t) < 8 || sizeof(resource_size_t) < 8) &&
|
||||
sz64 > 0x100000000ULL) {
|
||||
if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
|
||||
&& sz64 > 0x100000000ULL) {
|
||||
res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
|
||||
res->start = 0;
|
||||
res->end = 0;
|
||||
|
|
@ -264,7 +264,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
|
|||
goto out;
|
||||
}
|
||||
|
||||
if ((sizeof(dma_addr_t) < 8) && l) {
|
||||
if ((sizeof(pci_bus_addr_t) < 8) && l) {
|
||||
/* Above 32-bit boundary; try to reallocate */
|
||||
res->flags |= IORESOURCE_UNSET;
|
||||
res->start = 0;
|
||||
|
|
@ -399,7 +399,7 @@ static void pci_read_bridge_mmio_pref(struct pci_bus *child)
|
|||
struct pci_dev *dev = child->self;
|
||||
u16 mem_base_lo, mem_limit_lo;
|
||||
u64 base64, limit64;
|
||||
dma_addr_t base, limit;
|
||||
pci_bus_addr_t base, limit;
|
||||
struct pci_bus_region region;
|
||||
struct resource *res;
|
||||
|
||||
|
|
@ -426,8 +426,8 @@ static void pci_read_bridge_mmio_pref(struct pci_bus *child)
|
|||
}
|
||||
}
|
||||
|
||||
base = (dma_addr_t) base64;
|
||||
limit = (dma_addr_t) limit64;
|
||||
base = (pci_bus_addr_t) base64;
|
||||
limit = (pci_bus_addr_t) limit64;
|
||||
|
||||
if (base != base64) {
|
||||
dev_err(&dev->dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
|
||||
|
|
@ -973,6 +973,8 @@ void set_pcie_port_type(struct pci_dev *pdev)
|
|||
{
|
||||
int pos;
|
||||
u16 reg16;
|
||||
int type;
|
||||
struct pci_dev *parent;
|
||||
|
||||
pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
|
||||
if (!pos)
|
||||
|
|
@ -982,6 +984,22 @@ void set_pcie_port_type(struct pci_dev *pdev)
|
|||
pdev->pcie_flags_reg = reg16;
|
||||
pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
|
||||
pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
|
||||
|
||||
/*
|
||||
* A Root Port is always the upstream end of a Link. No PCIe
|
||||
* component has two Links. Two Links are connected by a Switch
|
||||
* that has a Port on each Link and internal logic to connect the
|
||||
* two Ports.
|
||||
*/
|
||||
type = pci_pcie_type(pdev);
|
||||
if (type == PCI_EXP_TYPE_ROOT_PORT)
|
||||
pdev->has_secondary_link = 1;
|
||||
else if (type == PCI_EXP_TYPE_UPSTREAM ||
|
||||
type == PCI_EXP_TYPE_DOWNSTREAM) {
|
||||
parent = pci_upstream_bridge(pdev);
|
||||
if (!parent->has_secondary_link)
|
||||
pdev->has_secondary_link = 1;
|
||||
}
|
||||
}
|
||||
|
||||
void set_pcie_hotplug_bridge(struct pci_dev *pdev)
|
||||
|
|
@ -1085,6 +1103,22 @@ int pci_cfg_space_size(struct pci_dev *dev)
|
|||
|
||||
#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
|
||||
|
||||
static void pci_msi_setup_pci_dev(struct pci_dev *dev)
|
||||
{
|
||||
/*
|
||||
* Disable the MSI hardware to avoid screaming interrupts
|
||||
* during boot. This is the power on reset default so
|
||||
* usually this should be a noop.
|
||||
*/
|
||||
dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
|
||||
if (dev->msi_cap)
|
||||
pci_msi_set_enable(dev, 0);
|
||||
|
||||
dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
|
||||
if (dev->msix_cap)
|
||||
pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* pci_setup_device - fill in class and map information of a device
|
||||
* @dev: the device structure to fill
|
||||
|
|
@ -1140,6 +1174,8 @@ int pci_setup_device(struct pci_dev *dev)
|
|||
/* "Unknown power state" */
|
||||
dev->current_state = PCI_UNKNOWN;
|
||||
|
||||
pci_msi_setup_pci_dev(dev);
|
||||
|
||||
/* Early fixups, before probing the BARs */
|
||||
pci_fixup_device(pci_fixup_early, dev);
|
||||
/* device class may be changed after fixup */
|
||||
|
|
@ -1611,7 +1647,7 @@ static int only_one_child(struct pci_bus *bus)
|
|||
return 0;
|
||||
if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
|
||||
return 1;
|
||||
if (pci_pcie_type(parent) == PCI_EXP_TYPE_DOWNSTREAM &&
|
||||
if (parent->has_secondary_link &&
|
||||
!pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
|
||||
return 1;
|
||||
return 0;
|
||||
|
|
@ -2094,25 +2130,6 @@ struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
|
|||
}
|
||||
EXPORT_SYMBOL(pci_scan_root_bus);
|
||||
|
||||
/* Deprecated; use pci_scan_root_bus() instead */
|
||||
struct pci_bus *pci_scan_bus_parented(struct device *parent,
|
||||
int bus, struct pci_ops *ops, void *sysdata)
|
||||
{
|
||||
LIST_HEAD(resources);
|
||||
struct pci_bus *b;
|
||||
|
||||
pci_add_resource(&resources, &ioport_resource);
|
||||
pci_add_resource(&resources, &iomem_resource);
|
||||
pci_add_resource(&resources, &busn_resource);
|
||||
b = pci_create_root_bus(parent, bus, ops, sysdata, &resources);
|
||||
if (b)
|
||||
pci_scan_child_bus(b);
|
||||
else
|
||||
pci_free_resource_list(&resources);
|
||||
return b;
|
||||
}
|
||||
EXPORT_SYMBOL(pci_scan_bus_parented);
|
||||
|
||||
struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
|
||||
void *sysdata)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -1600,7 +1600,6 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_a
|
|||
|
||||
static void quirk_pcie_mch(struct pci_dev *pdev)
|
||||
{
|
||||
pci_msi_off(pdev);
|
||||
pdev->no_msi = 1;
|
||||
}
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
|
||||
|
|
@ -1614,7 +1613,6 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quir
|
|||
*/
|
||||
static void quirk_pcie_pxh(struct pci_dev *dev)
|
||||
{
|
||||
pci_msi_off(dev);
|
||||
dev->no_msi = 1;
|
||||
dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
|
||||
}
|
||||
|
|
@ -3572,6 +3570,8 @@ static void quirk_dma_func1_alias(struct pci_dev *dev)
|
|||
* SKUs this function is not present, making this a ghost requester.
|
||||
* https://bugzilla.kernel.org/show_bug.cgi?id=42679
|
||||
*/
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
|
||||
quirk_dma_func1_alias);
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
|
||||
quirk_dma_func1_alias);
|
||||
/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
|
||||
|
|
@ -3740,6 +3740,8 @@ static const u16 pci_quirk_intel_pch_acs_ids[] = {
|
|||
/* Wellsburg (X99) PCH */
|
||||
0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
|
||||
0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
|
||||
/* Lynx Point (9 series) PCH */
|
||||
0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
|
||||
};
|
||||
|
||||
static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
|
||||
|
|
|
|||
|
|
@ -108,8 +108,7 @@ static void pci_vc_enable(struct pci_dev *dev, int pos, int res)
|
|||
struct pci_dev *link = NULL;
|
||||
|
||||
/* Enable VCs from the downstream device */
|
||||
if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT ||
|
||||
pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM)
|
||||
if (!dev->has_secondary_link)
|
||||
return;
|
||||
|
||||
ctrl_pos = pos + PCI_VC_RES_CTRL + (res * PCI_CAP_VC_PER_VC_SIZEOF);
|
||||
|
|
|
|||
|
|
@ -446,9 +446,15 @@ static int pcifront_scan_root(struct pcifront_device *pdev,
|
|||
unsigned int domain, unsigned int bus)
|
||||
{
|
||||
struct pci_bus *b;
|
||||
LIST_HEAD(resources);
|
||||
struct pcifront_sd *sd = NULL;
|
||||
struct pci_bus_entry *bus_entry = NULL;
|
||||
int err = 0;
|
||||
static struct resource busn_res = {
|
||||
.start = 0,
|
||||
.end = 255,
|
||||
.flags = IORESOURCE_BUS,
|
||||
};
|
||||
|
||||
#ifndef CONFIG_PCI_DOMAINS
|
||||
if (domain != 0) {
|
||||
|
|
@ -470,17 +476,21 @@ static int pcifront_scan_root(struct pcifront_device *pdev,
|
|||
err = -ENOMEM;
|
||||
goto err_out;
|
||||
}
|
||||
pci_add_resource(&resources, &ioport_resource);
|
||||
pci_add_resource(&resources, &iomem_resource);
|
||||
pci_add_resource(&resources, &busn_res);
|
||||
pcifront_init_sd(sd, domain, bus, pdev);
|
||||
|
||||
pci_lock_rescan_remove();
|
||||
|
||||
b = pci_scan_bus_parented(&pdev->xdev->dev, bus,
|
||||
&pcifront_bus_ops, sd);
|
||||
b = pci_scan_root_bus(&pdev->xdev->dev, bus,
|
||||
&pcifront_bus_ops, sd, &resources);
|
||||
if (!b) {
|
||||
dev_err(&pdev->xdev->dev,
|
||||
"Error creating PCI Frontend Bus!\n");
|
||||
err = -ENOMEM;
|
||||
pci_unlock_rescan_remove();
|
||||
pci_free_resource_list(&resources);
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
|
|
@ -488,7 +498,7 @@ static int pcifront_scan_root(struct pcifront_device *pdev,
|
|||
|
||||
list_add(&bus_entry->list, &pdev->root_buses);
|
||||
|
||||
/* pci_scan_bus_parented skips devices which do not have a have
|
||||
/* pci_scan_root_bus skips devices which do not have a
|
||||
* devfn==0. The pcifront_scan_bus enumerates all devfn. */
|
||||
err = pcifront_scan_bus(pdev, domain, bus, b);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue