From 10047ad8446450b1936e0db4cd796e2c8b0782d7 Mon Sep 17 00:00:00 2001
From: Mukesh Kumar Savaliya <msavaliy@qti.qualcomm.com>
Date: Fri, 20 Dec 2019 13:54:12 +0530
Subject: [PATCH] ARM: dts: msm: Add 2-wire UART node for lahaina

Adds 2-wire HSUART node for travel adapter case. This doesn't
support wakeup and no flow control support needed.

Change-Id: I55f9e5c7e767c43462d73b06b47255420a1aa3e6
---
 qcom/lahaina-pinctrl.dtsi | 41 +++++++++++++++++++++++++++++++++++++++
 qcom/lahaina-qupv3.dtsi   | 18 +++++++++++++++++
 2 files changed, 59 insertions(+)

diff --git a/qcom/lahaina-pinctrl.dtsi b/qcom/lahaina-pinctrl.dtsi
index 0a545d6c098f..904e717a828a 100644
--- a/qcom/lahaina-pinctrl.dtsi
+++ b/qcom/lahaina-pinctrl.dtsi
@@ -65,6 +65,47 @@
 			};
 		};
 
+		qupv3_se6_2uart_pins: qupv3_se6_2uart_pins {
+			qupv3_se6_default_txrx: qupv3_se6_default_txrx {
+				mux {
+					pins = "gpio30", "gpio31";
+					function = "qup6";
+				};
+
+				config {
+					pins = "gpio30", "gpio31";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+
+			qupv3_se6_2uart_active: qupv3_se6_2uart_active {
+				mux {
+					pins = "gpio30", "gpio31";
+					function = "qup6";
+				};
+
+				config {
+					pins = "gpio30", "gpio31";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+
+			qupv3_se6_2uart_sleep: qupv3_se6_2uart_sleep {
+				mux {
+					pins = "gpio30", "gpio31";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio30", "gpio31";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+		};
+
 		qupv3_se18_4uart_pins: qupv3_se18_4uart_pins {
 			qupv3_se18_default_cts:
 				qupv3_se18_default_cts {
diff --git a/qcom/lahaina-qupv3.dtsi b/qcom/lahaina-qupv3.dtsi
index b3cee1d16222..03adf8f0a6e1 100644
--- a/qcom/lahaina-qupv3.dtsi
+++ b/qcom/lahaina-qupv3.dtsi
@@ -89,6 +89,24 @@
 		status = "disabled";
 	};
 
+	/* Travel adapter over 2-wire HSUART, no wakeup */
+	qupv3_se6_2uart: qcom,qup_uart@998000 {
+		compatible = "qcom,msm-geni-serial-hs";
+		reg = <0x998000 0x4000>;
+		reg-names = "se_phys";
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S6_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		pinctrl-names = "default", "active", "sleep";
+		pinctrl-0 = <&qupv3_se6_default_txrx>;
+		pinctrl-1 = <&qupv3_se6_2uart_active>;
+		pinctrl-2 = <&qupv3_se6_2uart_sleep>;
+		interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "disabled";
+	};
+
 	/* SPI */
 	qupv3_se0_spi: spi@980000 {
 		compatible = "qcom,spi-geni";