mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-29 19:21:31 -04:00
ARM: SoC driver updates for v4.3
Some releases this branch is nearly empty, others we have more stuff. It
tends to gather drivers that need SoC modification or dependencies such
that they have to (also) go in through our tree.
For this release, we have merged in part of the reset controller tree
(with handshake that the parts we have merged in will remain stable),
as well as dependencies on a few clock branches.
In general, new items here are:
- Qualcomm driver for SMM/SMD, which is how they communicate with the
coprocessors on (some) of their platforms
- Memory controller work for ARM's PL172 memory controller
- Reset drivers for various platforms
- PMU power domain support for Marvell platforms
- Tegra support for T132/T210 SoCs: PMC, fuse, memory controller per-SoC support
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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Olof Johansson:
"Some releases this branch is nearly empty, others we have more stuff.
It tends to gather drivers that need SoC modification or dependencies
such that they have to (also) go in through our tree.
For this release, we have merged in part of the reset controller tree
(with handshake that the parts we have merged in will remain stable),
as well as dependencies on a few clock branches.
In general, new items here are:
- Qualcomm driver for SMM/SMD, which is how they communicate with the
coprocessors on (some) of their platforms
- memory controller work for ARM's PL172 memory controller
- reset drivers for various platforms
- PMU power domain support for Marvell platforms
- Tegra support for T132/T210 SoCs: PMC, fuse, memory controller
per-SoC support"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (49 commits)
ARM: tegra: cpuidle: implement cpuidle_state.enter_freeze()
ARM: tegra: Disable cpuidle if PSCI is available
soc/tegra: pmc: Use existing pclk reference
soc/tegra: pmc: Remove unnecessary return statement
soc: tegra: Remove redundant $(CONFIG_ARCH_TEGRA) in Makefile
memory: tegra: Add Tegra210 support
memory: tegra: Add support for a variable-size client ID bitfield
clk: shmobile: rz: Add CPG/MSTP Clock Domain support
clk: shmobile: rcar-gen2: Add CPG/MSTP Clock Domain support
clk: shmobile: r8a7779: Add CPG/MSTP Clock Domain support
clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain support
clk: shmobile: Add CPG/MSTP Clock Domain support
ARM: dove: create a proper PMU driver for power domains, PMU IRQs and resets
reset: reset-zynq: Adding support for Xilinx Zynq reset controller.
docs: dts: Added documentation for Xilinx Zynq Reset Controller bindings.
MIPS: ath79: Add the reset controller to the AR9132 dtsi
reset: Add a driver for the reset controller on the AR71XX/AR9XXX
devicetree: Add bindings for the ATH79 reset controller
reset: socfpga: Update reset-socfpga to read the altr,modrst-offset property
doc: dt: add documentation for lpc1850-rgu reset driver
...
This commit is contained in:
Linus Torvalds
commit
102178108e
88 changed files with 6781 additions and 498 deletions
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@ -2,6 +2,7 @@
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# Makefile for the Linux Kernel SOC specific device drivers.
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#
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obj-$(CONFIG_MACH_DOVE) += dove/
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obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
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obj-$(CONFIG_ARCH_QCOM) += qcom/
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obj-$(CONFIG_ARCH_SUNXI) += sunxi/
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|
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1
drivers/soc/dove/Makefile
Normal file
1
drivers/soc/dove/Makefile
Normal file
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@ -0,0 +1 @@
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obj-y += pmu.o
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412
drivers/soc/dove/pmu.c
Normal file
412
drivers/soc/dove/pmu.c
Normal file
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@ -0,0 +1,412 @@
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/*
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* Marvell Dove PMU support
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*/
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/pm_domain.h>
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#include <linux/reset.h>
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#include <linux/reset-controller.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/soc/dove/pmu.h>
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#include <linux/spinlock.h>
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#define NR_PMU_IRQS 7
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#define PMC_SW_RST 0x30
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#define PMC_IRQ_CAUSE 0x50
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#define PMC_IRQ_MASK 0x54
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#define PMU_PWR 0x10
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#define PMU_ISO 0x58
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struct pmu_data {
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spinlock_t lock;
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struct device_node *of_node;
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void __iomem *pmc_base;
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void __iomem *pmu_base;
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struct irq_chip_generic *irq_gc;
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struct irq_domain *irq_domain;
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#ifdef CONFIG_RESET_CONTROLLER
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struct reset_controller_dev reset;
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#endif
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};
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/*
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* The PMU contains a register to reset various subsystems within the
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* SoC. Export this as a reset controller.
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*/
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#ifdef CONFIG_RESET_CONTROLLER
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#define rcdev_to_pmu(rcdev) container_of(rcdev, struct pmu_data, reset)
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static int pmu_reset_reset(struct reset_controller_dev *rc, unsigned long id)
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{
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struct pmu_data *pmu = rcdev_to_pmu(rc);
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&pmu->lock, flags);
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val = readl_relaxed(pmu->pmc_base + PMC_SW_RST);
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writel_relaxed(val & ~BIT(id), pmu->pmc_base + PMC_SW_RST);
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writel_relaxed(val | BIT(id), pmu->pmc_base + PMC_SW_RST);
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spin_unlock_irqrestore(&pmu->lock, flags);
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return 0;
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}
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static int pmu_reset_assert(struct reset_controller_dev *rc, unsigned long id)
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{
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struct pmu_data *pmu = rcdev_to_pmu(rc);
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unsigned long flags;
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u32 val = ~BIT(id);
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spin_lock_irqsave(&pmu->lock, flags);
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val &= readl_relaxed(pmu->pmc_base + PMC_SW_RST);
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writel_relaxed(val, pmu->pmc_base + PMC_SW_RST);
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spin_unlock_irqrestore(&pmu->lock, flags);
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return 0;
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}
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static int pmu_reset_deassert(struct reset_controller_dev *rc, unsigned long id)
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{
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struct pmu_data *pmu = rcdev_to_pmu(rc);
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unsigned long flags;
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u32 val = BIT(id);
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spin_lock_irqsave(&pmu->lock, flags);
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val |= readl_relaxed(pmu->pmc_base + PMC_SW_RST);
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writel_relaxed(val, pmu->pmc_base + PMC_SW_RST);
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spin_unlock_irqrestore(&pmu->lock, flags);
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return 0;
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}
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static struct reset_control_ops pmu_reset_ops = {
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.reset = pmu_reset_reset,
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.assert = pmu_reset_assert,
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.deassert = pmu_reset_deassert,
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};
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static struct reset_controller_dev pmu_reset __initdata = {
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.ops = &pmu_reset_ops,
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.owner = THIS_MODULE,
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.nr_resets = 32,
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};
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static void __init pmu_reset_init(struct pmu_data *pmu)
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{
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int ret;
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pmu->reset = pmu_reset;
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pmu->reset.of_node = pmu->of_node;
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ret = reset_controller_register(&pmu->reset);
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if (ret)
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pr_err("pmu: %s failed: %d\n", "reset_controller_register", ret);
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}
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#else
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static void __init pmu_reset_init(struct pmu_data *pmu)
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{
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}
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#endif
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struct pmu_domain {
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struct pmu_data *pmu;
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u32 pwr_mask;
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u32 rst_mask;
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u32 iso_mask;
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struct generic_pm_domain base;
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};
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#define to_pmu_domain(dom) container_of(dom, struct pmu_domain, base)
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/*
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* This deals with the "old" Marvell sequence of bringing a power domain
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* down/up, which is: apply power, release reset, disable isolators.
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*
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* Later devices apparantly use a different sequence: power up, disable
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* isolators, assert repair signal, enable SRMA clock, enable AXI clock,
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* enable module clock, deassert reset.
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*
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* Note: reading the assembly, it seems that the IO accessors have an
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* unfortunate side-effect - they cause memory already read into registers
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* for the if () to be re-read for the bit-set or bit-clear operation.
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* The code is written to avoid this.
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*/
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static int pmu_domain_power_off(struct generic_pm_domain *domain)
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{
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struct pmu_domain *pmu_dom = to_pmu_domain(domain);
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struct pmu_data *pmu = pmu_dom->pmu;
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unsigned long flags;
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unsigned int val;
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void __iomem *pmu_base = pmu->pmu_base;
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void __iomem *pmc_base = pmu->pmc_base;
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spin_lock_irqsave(&pmu->lock, flags);
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/* Enable isolators */
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if (pmu_dom->iso_mask) {
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val = ~pmu_dom->iso_mask;
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val &= readl_relaxed(pmu_base + PMU_ISO);
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writel_relaxed(val, pmu_base + PMU_ISO);
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}
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/* Reset unit */
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if (pmu_dom->rst_mask) {
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val = ~pmu_dom->rst_mask;
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val &= readl_relaxed(pmc_base + PMC_SW_RST);
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writel_relaxed(val, pmc_base + PMC_SW_RST);
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}
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/* Power down */
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val = readl_relaxed(pmu_base + PMU_PWR) | pmu_dom->pwr_mask;
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writel_relaxed(val, pmu_base + PMU_PWR);
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spin_unlock_irqrestore(&pmu->lock, flags);
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return 0;
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}
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static int pmu_domain_power_on(struct generic_pm_domain *domain)
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{
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struct pmu_domain *pmu_dom = to_pmu_domain(domain);
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struct pmu_data *pmu = pmu_dom->pmu;
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unsigned long flags;
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unsigned int val;
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void __iomem *pmu_base = pmu->pmu_base;
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void __iomem *pmc_base = pmu->pmc_base;
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spin_lock_irqsave(&pmu->lock, flags);
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/* Power on */
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val = ~pmu_dom->pwr_mask & readl_relaxed(pmu_base + PMU_PWR);
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writel_relaxed(val, pmu_base + PMU_PWR);
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/* Release reset */
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if (pmu_dom->rst_mask) {
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val = pmu_dom->rst_mask;
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val |= readl_relaxed(pmc_base + PMC_SW_RST);
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writel_relaxed(val, pmc_base + PMC_SW_RST);
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}
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/* Disable isolators */
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if (pmu_dom->iso_mask) {
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val = pmu_dom->iso_mask;
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val |= readl_relaxed(pmu_base + PMU_ISO);
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writel_relaxed(val, pmu_base + PMU_ISO);
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}
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spin_unlock_irqrestore(&pmu->lock, flags);
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return 0;
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}
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static void __pmu_domain_register(struct pmu_domain *domain,
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struct device_node *np)
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{
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unsigned int val = readl_relaxed(domain->pmu->pmu_base + PMU_PWR);
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domain->base.power_off = pmu_domain_power_off;
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domain->base.power_on = pmu_domain_power_on;
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pm_genpd_init(&domain->base, NULL, !(val & domain->pwr_mask));
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if (np)
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of_genpd_add_provider_simple(np, &domain->base);
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}
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/* PMU IRQ controller */
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static void pmu_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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struct pmu_data *pmu = irq_get_handler_data(irq);
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struct irq_chip_generic *gc = pmu->irq_gc;
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struct irq_domain *domain = pmu->irq_domain;
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void __iomem *base = gc->reg_base;
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u32 stat = readl_relaxed(base + PMC_IRQ_CAUSE) & gc->mask_cache;
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u32 done = ~0;
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if (stat == 0) {
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handle_bad_irq(irq, desc);
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return;
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}
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while (stat) {
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u32 hwirq = fls(stat) - 1;
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stat &= ~(1 << hwirq);
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done &= ~(1 << hwirq);
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generic_handle_irq(irq_find_mapping(domain, hwirq));
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}
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/*
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* The PMU mask register is not RW0C: it is RW. This means that
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* the bits take whatever value is written to them; if you write
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* a '1', you will set the interrupt.
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*
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* Unfortunately this means there is NO race free way to clear
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* these interrupts.
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*
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* So, let's structure the code so that the window is as small as
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* possible.
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*/
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irq_gc_lock(gc);
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done &= readl_relaxed(base + PMC_IRQ_CAUSE);
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writel_relaxed(done, base + PMC_IRQ_CAUSE);
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irq_gc_unlock(gc);
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}
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static int __init dove_init_pmu_irq(struct pmu_data *pmu, int irq)
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{
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const char *name = "pmu_irq";
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struct irq_chip_generic *gc;
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struct irq_domain *domain;
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int ret;
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/* mask and clear all interrupts */
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writel(0, pmu->pmc_base + PMC_IRQ_MASK);
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writel(0, pmu->pmc_base + PMC_IRQ_CAUSE);
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domain = irq_domain_add_linear(pmu->of_node, NR_PMU_IRQS,
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&irq_generic_chip_ops, NULL);
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if (!domain) {
|
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pr_err("%s: unable to add irq domain\n", name);
|
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return -ENOMEM;
|
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}
|
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ret = irq_alloc_domain_generic_chips(domain, NR_PMU_IRQS, 1, name,
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handle_level_irq,
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IRQ_NOREQUEST | IRQ_NOPROBE, 0,
|
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IRQ_GC_INIT_MASK_CACHE);
|
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if (ret) {
|
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pr_err("%s: unable to alloc irq domain gc: %d\n", name, ret);
|
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irq_domain_remove(domain);
|
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return ret;
|
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}
|
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|
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gc = irq_get_domain_generic_chip(domain, 0);
|
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gc->reg_base = pmu->pmc_base;
|
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gc->chip_types[0].regs.mask = PMC_IRQ_MASK;
|
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gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
|
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gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
|
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|
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pmu->irq_domain = domain;
|
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pmu->irq_gc = gc;
|
||||
|
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irq_set_handler_data(irq, pmu);
|
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irq_set_chained_handler(irq, pmu_irq_handler);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* pmu: power-manager@d0000 {
|
||||
* compatible = "marvell,dove-pmu";
|
||||
* reg = <0xd0000 0x8000> <0xd8000 0x8000>;
|
||||
* interrupts = <33>;
|
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* interrupt-controller;
|
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* #reset-cells = 1;
|
||||
* vpu_domain: vpu-domain {
|
||||
* #power-domain-cells = <0>;
|
||||
* marvell,pmu_pwr_mask = <0x00000008>;
|
||||
* marvell,pmu_iso_mask = <0x00000001>;
|
||||
* resets = <&pmu 16>;
|
||||
* };
|
||||
* gpu_domain: gpu-domain {
|
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* #power-domain-cells = <0>;
|
||||
* marvell,pmu_pwr_mask = <0x00000004>;
|
||||
* marvell,pmu_iso_mask = <0x00000002>;
|
||||
* resets = <&pmu 18>;
|
||||
* };
|
||||
* };
|
||||
*/
|
||||
int __init dove_init_pmu(void)
|
||||
{
|
||||
struct device_node *np_pmu, *domains_node, *np;
|
||||
struct pmu_data *pmu;
|
||||
int ret, parent_irq;
|
||||
|
||||
/* Lookup the PMU node */
|
||||
np_pmu = of_find_compatible_node(NULL, NULL, "marvell,dove-pmu");
|
||||
if (!np_pmu)
|
||||
return 0;
|
||||
|
||||
domains_node = of_get_child_by_name(np_pmu, "domains");
|
||||
if (!domains_node) {
|
||||
pr_err("%s: failed to find domains sub-node\n", np_pmu->name);
|
||||
return 0;
|
||||
}
|
||||
|
||||
pmu = kzalloc(sizeof(*pmu), GFP_KERNEL);
|
||||
if (!pmu)
|
||||
return -ENOMEM;
|
||||
|
||||
spin_lock_init(&pmu->lock);
|
||||
pmu->of_node = np_pmu;
|
||||
pmu->pmc_base = of_iomap(pmu->of_node, 0);
|
||||
pmu->pmu_base = of_iomap(pmu->of_node, 1);
|
||||
if (!pmu->pmc_base || !pmu->pmu_base) {
|
||||
pr_err("%s: failed to map PMU\n", np_pmu->name);
|
||||
iounmap(pmu->pmu_base);
|
||||
iounmap(pmu->pmc_base);
|
||||
kfree(pmu);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
pmu_reset_init(pmu);
|
||||
|
||||
for_each_available_child_of_node(domains_node, np) {
|
||||
struct of_phandle_args args;
|
||||
struct pmu_domain *domain;
|
||||
|
||||
domain = kzalloc(sizeof(*domain), GFP_KERNEL);
|
||||
if (!domain)
|
||||
break;
|
||||
|
||||
domain->pmu = pmu;
|
||||
domain->base.name = kstrdup(np->name, GFP_KERNEL);
|
||||
if (!domain->base.name) {
|
||||
kfree(domain);
|
||||
break;
|
||||
}
|
||||
|
||||
of_property_read_u32(np, "marvell,pmu_pwr_mask",
|
||||
&domain->pwr_mask);
|
||||
of_property_read_u32(np, "marvell,pmu_iso_mask",
|
||||
&domain->iso_mask);
|
||||
|
||||
/*
|
||||
* We parse the reset controller property directly here
|
||||
* to ensure that we can operate when the reset controller
|
||||
* support is not configured into the kernel.
|
||||
*/
|
||||
ret = of_parse_phandle_with_args(np, "resets", "#reset-cells",
|
||||
0, &args);
|
||||
if (ret == 0) {
|
||||
if (args.np == pmu->of_node)
|
||||
domain->rst_mask = BIT(args.args[0]);
|
||||
of_node_put(args.np);
|
||||
}
|
||||
|
||||
__pmu_domain_register(domain, np);
|
||||
}
|
||||
pm_genpd_poweroff_unused();
|
||||
|
||||
/* Loss of the interrupt controller is not a fatal error. */
|
||||
parent_irq = irq_of_parse_and_map(pmu->of_node, 0);
|
||||
if (!parent_irq) {
|
||||
pr_err("%s: no interrupt specified\n", np_pmu->name);
|
||||
} else {
|
||||
ret = dove_init_pmu_irq(pmu, parent_irq);
|
||||
if (ret)
|
||||
pr_err("dove_init_pmu_irq() failed: %d\n", ret);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -13,7 +13,38 @@ config QCOM_GSBI
|
|||
config QCOM_PM
|
||||
bool "Qualcomm Power Management"
|
||||
depends on ARCH_QCOM && !ARM64
|
||||
select QCOM_SCM
|
||||
help
|
||||
QCOM Platform specific power driver to manage cores and L2 low power
|
||||
modes. It interface with various system drivers to put the cores in
|
||||
low power modes.
|
||||
|
||||
config QCOM_SMD
|
||||
tristate "Qualcomm Shared Memory Driver (SMD)"
|
||||
depends on QCOM_SMEM
|
||||
help
|
||||
Say y here to enable support for the Qualcomm Shared Memory Driver
|
||||
providing communication channels to remote processors in Qualcomm
|
||||
platforms.
|
||||
|
||||
config QCOM_SMD_RPM
|
||||
tristate "Qualcomm Resource Power Manager (RPM) over SMD"
|
||||
depends on QCOM_SMD && OF
|
||||
help
|
||||
If you say yes to this option, support will be included for the
|
||||
Resource Power Manager system found in the Qualcomm 8974 based
|
||||
devices.
|
||||
|
||||
This is required to access many regulators, clocks and bus
|
||||
frequencies controlled by the RPM on these devices.
|
||||
|
||||
Say M here if you want to include support for the Qualcomm RPM as a
|
||||
module. This will build a module called "qcom-smd-rpm".
|
||||
|
||||
config QCOM_SMEM
|
||||
tristate "Qualcomm Shared Memory Manager (SMEM)"
|
||||
depends on ARCH_QCOM
|
||||
help
|
||||
Say y here to enable support for the Qualcomm Shared Memory Manager.
|
||||
The driver provides an interface to items in a heap shared among all
|
||||
processors in a Qualcomm platform.
|
||||
|
|
|
|||
|
|
@ -1,2 +1,5 @@
|
|||
obj-$(CONFIG_QCOM_GSBI) += qcom_gsbi.o
|
||||
obj-$(CONFIG_QCOM_PM) += spm.o
|
||||
obj-$(CONFIG_QCOM_SMD) += smd.o
|
||||
obj-$(CONFIG_QCOM_SMD_RPM) += smd-rpm.o
|
||||
obj-$(CONFIG_QCOM_SMEM) += smem.o
|
||||
|
|
|
|||
244
drivers/soc/qcom/smd-rpm.c
Normal file
244
drivers/soc/qcom/smd-rpm.c
Normal file
|
|
@ -0,0 +1,244 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Sony Mobile Communications AB.
|
||||
* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/interrupt.h>
|
||||
|
||||
#include <linux/soc/qcom/smd.h>
|
||||
#include <linux/soc/qcom/smd-rpm.h>
|
||||
|
||||
#define RPM_REQUEST_TIMEOUT (5 * HZ)
|
||||
|
||||
/**
|
||||
* struct qcom_smd_rpm - state of the rpm device driver
|
||||
* @rpm_channel: reference to the smd channel
|
||||
* @ack: completion for acks
|
||||
* @lock: mutual exclusion around the send/complete pair
|
||||
* @ack_status: result of the rpm request
|
||||
*/
|
||||
struct qcom_smd_rpm {
|
||||
struct qcom_smd_channel *rpm_channel;
|
||||
|
||||
struct completion ack;
|
||||
struct mutex lock;
|
||||
int ack_status;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct qcom_rpm_header - header for all rpm requests and responses
|
||||
* @service_type: identifier of the service
|
||||
* @length: length of the payload
|
||||
*/
|
||||
struct qcom_rpm_header {
|
||||
u32 service_type;
|
||||
u32 length;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct qcom_rpm_request - request message to the rpm
|
||||
* @msg_id: identifier of the outgoing message
|
||||
* @flags: active/sleep state flags
|
||||
* @type: resource type
|
||||
* @id: resource id
|
||||
* @data_len: length of the payload following this header
|
||||
*/
|
||||
struct qcom_rpm_request {
|
||||
u32 msg_id;
|
||||
u32 flags;
|
||||
u32 type;
|
||||
u32 id;
|
||||
u32 data_len;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct qcom_rpm_message - response message from the rpm
|
||||
* @msg_type: indicator of the type of message
|
||||
* @length: the size of this message, including the message header
|
||||
* @msg_id: message id
|
||||
* @message: textual message from the rpm
|
||||
*
|
||||
* Multiple of these messages can be stacked in an rpm message.
|
||||
*/
|
||||
struct qcom_rpm_message {
|
||||
u32 msg_type;
|
||||
u32 length;
|
||||
union {
|
||||
u32 msg_id;
|
||||
u8 message[0];
|
||||
};
|
||||
};
|
||||
|
||||
#define RPM_SERVICE_TYPE_REQUEST 0x00716572 /* "req\0" */
|
||||
|
||||
#define RPM_MSG_TYPE_ERR 0x00727265 /* "err\0" */
|
||||
#define RPM_MSG_TYPE_MSG_ID 0x2367736d /* "msg#" */
|
||||
|
||||
/**
|
||||
* qcom_rpm_smd_write - write @buf to @type:@id
|
||||
* @rpm: rpm handle
|
||||
* @type: resource type
|
||||
* @id: resource identifier
|
||||
* @buf: the data to be written
|
||||
* @count: number of bytes in @buf
|
||||
*/
|
||||
int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm,
|
||||
int state,
|
||||
u32 type, u32 id,
|
||||
void *buf,
|
||||
size_t count)
|
||||
{
|
||||
static unsigned msg_id = 1;
|
||||
int left;
|
||||
int ret;
|
||||
|
||||
struct {
|
||||
struct qcom_rpm_header hdr;
|
||||
struct qcom_rpm_request req;
|
||||
u8 payload[count];
|
||||
} pkt;
|
||||
|
||||
/* SMD packets to the RPM may not exceed 256 bytes */
|
||||
if (WARN_ON(sizeof(pkt) >= 256))
|
||||
return -EINVAL;
|
||||
|
||||
mutex_lock(&rpm->lock);
|
||||
|
||||
pkt.hdr.service_type = RPM_SERVICE_TYPE_REQUEST;
|
||||
pkt.hdr.length = sizeof(struct qcom_rpm_request) + count;
|
||||
|
||||
pkt.req.msg_id = msg_id++;
|
||||
pkt.req.flags = BIT(state);
|
||||
pkt.req.type = type;
|
||||
pkt.req.id = id;
|
||||
pkt.req.data_len = count;
|
||||
memcpy(pkt.payload, buf, count);
|
||||
|
||||
ret = qcom_smd_send(rpm->rpm_channel, &pkt, sizeof(pkt));
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
left = wait_for_completion_timeout(&rpm->ack, RPM_REQUEST_TIMEOUT);
|
||||
if (!left)
|
||||
ret = -ETIMEDOUT;
|
||||
else
|
||||
ret = rpm->ack_status;
|
||||
|
||||
out:
|
||||
mutex_unlock(&rpm->lock);
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(qcom_rpm_smd_write);
|
||||
|
||||
static int qcom_smd_rpm_callback(struct qcom_smd_device *qsdev,
|
||||
const void *data,
|
||||
size_t count)
|
||||
{
|
||||
const struct qcom_rpm_header *hdr = data;
|
||||
const struct qcom_rpm_message *msg;
|
||||
struct qcom_smd_rpm *rpm = dev_get_drvdata(&qsdev->dev);
|
||||
const u8 *buf = data + sizeof(struct qcom_rpm_header);
|
||||
const u8 *end = buf + hdr->length;
|
||||
char msgbuf[32];
|
||||
int status = 0;
|
||||
u32 len;
|
||||
|
||||
if (hdr->service_type != RPM_SERVICE_TYPE_REQUEST ||
|
||||
hdr->length < sizeof(struct qcom_rpm_message)) {
|
||||
dev_err(&qsdev->dev, "invalid request\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
while (buf < end) {
|
||||
msg = (struct qcom_rpm_message *)buf;
|
||||
switch (msg->msg_type) {
|
||||
case RPM_MSG_TYPE_MSG_ID:
|
||||
break;
|
||||
case RPM_MSG_TYPE_ERR:
|
||||
len = min_t(u32, ALIGN(msg->length, 4), sizeof(msgbuf));
|
||||
memcpy_fromio(msgbuf, msg->message, len);
|
||||
msgbuf[len - 1] = 0;
|
||||
|
||||
if (!strcmp(msgbuf, "resource does not exist"))
|
||||
status = -ENXIO;
|
||||
else
|
||||
status = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
buf = PTR_ALIGN(buf + 2 * sizeof(u32) + msg->length, 4);
|
||||
}
|
||||
|
||||
rpm->ack_status = status;
|
||||
complete(&rpm->ack);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int qcom_smd_rpm_probe(struct qcom_smd_device *sdev)
|
||||
{
|
||||
struct qcom_smd_rpm *rpm;
|
||||
|
||||
rpm = devm_kzalloc(&sdev->dev, sizeof(*rpm), GFP_KERNEL);
|
||||
if (!rpm)
|
||||
return -ENOMEM;
|
||||
|
||||
mutex_init(&rpm->lock);
|
||||
init_completion(&rpm->ack);
|
||||
|
||||
rpm->rpm_channel = sdev->channel;
|
||||
|
||||
dev_set_drvdata(&sdev->dev, rpm);
|
||||
|
||||
return of_platform_populate(sdev->dev.of_node, NULL, NULL, &sdev->dev);
|
||||
}
|
||||
|
||||
static void qcom_smd_rpm_remove(struct qcom_smd_device *sdev)
|
||||
{
|
||||
of_platform_depopulate(&sdev->dev);
|
||||
}
|
||||
|
||||
static const struct of_device_id qcom_smd_rpm_of_match[] = {
|
||||
{ .compatible = "qcom,rpm-msm8974" },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, qcom_smd_rpm_of_match);
|
||||
|
||||
static struct qcom_smd_driver qcom_smd_rpm_driver = {
|
||||
.probe = qcom_smd_rpm_probe,
|
||||
.remove = qcom_smd_rpm_remove,
|
||||
.callback = qcom_smd_rpm_callback,
|
||||
.driver = {
|
||||
.name = "qcom_smd_rpm",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = qcom_smd_rpm_of_match,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init qcom_smd_rpm_init(void)
|
||||
{
|
||||
return qcom_smd_driver_register(&qcom_smd_rpm_driver);
|
||||
}
|
||||
arch_initcall(qcom_smd_rpm_init);
|
||||
|
||||
static void __exit qcom_smd_rpm_exit(void)
|
||||
{
|
||||
qcom_smd_driver_unregister(&qcom_smd_rpm_driver);
|
||||
}
|
||||
module_exit(qcom_smd_rpm_exit);
|
||||
|
||||
MODULE_AUTHOR("Bjorn Andersson <[email protected]>");
|
||||
MODULE_DESCRIPTION("Qualcomm SMD backed RPM driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
1319
drivers/soc/qcom/smd.c
Normal file
1319
drivers/soc/qcom/smd.c
Normal file
File diff suppressed because it is too large
Load diff
775
drivers/soc/qcom/smem.c
Normal file
775
drivers/soc/qcom/smem.c
Normal file
|
|
@ -0,0 +1,775 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Sony Mobile Communications AB.
|
||||
* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/hwspinlock.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/soc/qcom/smem.h>
|
||||
|
||||
/*
|
||||
* The Qualcomm shared memory system is a allocate only heap structure that
|
||||
* consists of one of more memory areas that can be accessed by the processors
|
||||
* in the SoC.
|
||||
*
|
||||
* All systems contains a global heap, accessible by all processors in the SoC,
|
||||
* with a table of contents data structure (@smem_header) at the beginning of
|
||||
* the main shared memory block.
|
||||
*
|
||||
* The global header contains meta data for allocations as well as a fixed list
|
||||
* of 512 entries (@smem_global_entry) that can be initialized to reference
|
||||
* parts of the shared memory space.
|
||||
*
|
||||
*
|
||||
* In addition to this global heap a set of "private" heaps can be set up at
|
||||
* boot time with access restrictions so that only certain processor pairs can
|
||||
* access the data.
|
||||
*
|
||||
* These partitions are referenced from an optional partition table
|
||||
* (@smem_ptable), that is found 4kB from the end of the main smem region. The
|
||||
* partition table entries (@smem_ptable_entry) lists the involved processors
|
||||
* (or hosts) and their location in the main shared memory region.
|
||||
*
|
||||
* Each partition starts with a header (@smem_partition_header) that identifies
|
||||
* the partition and holds properties for the two internal memory regions. The
|
||||
* two regions are cached and non-cached memory respectively. Each region
|
||||
* contain a link list of allocation headers (@smem_private_entry) followed by
|
||||
* their data.
|
||||
*
|
||||
* Items in the non-cached region are allocated from the start of the partition
|
||||
* while items in the cached region are allocated from the end. The free area
|
||||
* is hence the region between the cached and non-cached offsets.
|
||||
*
|
||||
*
|
||||
* To synchronize allocations in the shared memory heaps a remote spinlock must
|
||||
* be held - currently lock number 3 of the sfpb or tcsr is used for this on all
|
||||
* platforms.
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* Item 3 of the global heap contains an array of versions for the various
|
||||
* software components in the SoC. We verify that the boot loader version is
|
||||
* what the expected version (SMEM_EXPECTED_VERSION) as a sanity check.
|
||||
*/
|
||||
#define SMEM_ITEM_VERSION 3
|
||||
#define SMEM_MASTER_SBL_VERSION_INDEX 7
|
||||
#define SMEM_EXPECTED_VERSION 11
|
||||
|
||||
/*
|
||||
* The first 8 items are only to be allocated by the boot loader while
|
||||
* initializing the heap.
|
||||
*/
|
||||
#define SMEM_ITEM_LAST_FIXED 8
|
||||
|
||||
/* Highest accepted item number, for both global and private heaps */
|
||||
#define SMEM_ITEM_COUNT 512
|
||||
|
||||
/* Processor/host identifier for the application processor */
|
||||
#define SMEM_HOST_APPS 0
|
||||
|
||||
/* Max number of processors/hosts in a system */
|
||||
#define SMEM_HOST_COUNT 9
|
||||
|
||||
/**
|
||||
* struct smem_proc_comm - proc_comm communication struct (legacy)
|
||||
* @command: current command to be executed
|
||||
* @status: status of the currently requested command
|
||||
* @params: parameters to the command
|
||||
*/
|
||||
struct smem_proc_comm {
|
||||
u32 command;
|
||||
u32 status;
|
||||
u32 params[2];
|
||||
};
|
||||
|
||||
/**
|
||||
* struct smem_global_entry - entry to reference smem items on the heap
|
||||
* @allocated: boolean to indicate if this entry is used
|
||||
* @offset: offset to the allocated space
|
||||
* @size: size of the allocated space, 8 byte aligned
|
||||
* @aux_base: base address for the memory region used by this unit, or 0 for
|
||||
* the default region. bits 0,1 are reserved
|
||||
*/
|
||||
struct smem_global_entry {
|
||||
u32 allocated;
|
||||
u32 offset;
|
||||
u32 size;
|
||||
u32 aux_base; /* bits 1:0 reserved */
|
||||
};
|
||||
#define AUX_BASE_MASK 0xfffffffc
|
||||
|
||||
/**
|
||||
* struct smem_header - header found in beginning of primary smem region
|
||||
* @proc_comm: proc_comm communication interface (legacy)
|
||||
* @version: array of versions for the various subsystems
|
||||
* @initialized: boolean to indicate that smem is initialized
|
||||
* @free_offset: index of the first unallocated byte in smem
|
||||
* @available: number of bytes available for allocation
|
||||
* @reserved: reserved field, must be 0
|
||||
* toc: array of references to items
|
||||
*/
|
||||
struct smem_header {
|
||||
struct smem_proc_comm proc_comm[4];
|
||||
u32 version[32];
|
||||
u32 initialized;
|
||||
u32 free_offset;
|
||||
u32 available;
|
||||
u32 reserved;
|
||||
struct smem_global_entry toc[SMEM_ITEM_COUNT];
|
||||
};
|
||||
|
||||
/**
|
||||
* struct smem_ptable_entry - one entry in the @smem_ptable list
|
||||
* @offset: offset, within the main shared memory region, of the partition
|
||||
* @size: size of the partition
|
||||
* @flags: flags for the partition (currently unused)
|
||||
* @host0: first processor/host with access to this partition
|
||||
* @host1: second processor/host with access to this partition
|
||||
* @reserved: reserved entries for later use
|
||||
*/
|
||||
struct smem_ptable_entry {
|
||||
u32 offset;
|
||||
u32 size;
|
||||
u32 flags;
|
||||
u16 host0;
|
||||
u16 host1;
|
||||
u32 reserved[8];
|
||||
};
|
||||
|
||||
/**
|
||||
* struct smem_ptable - partition table for the private partitions
|
||||
* @magic: magic number, must be SMEM_PTABLE_MAGIC
|
||||
* @version: version of the partition table
|
||||
* @num_entries: number of partitions in the table
|
||||
* @reserved: for now reserved entries
|
||||
* @entry: list of @smem_ptable_entry for the @num_entries partitions
|
||||
*/
|
||||
struct smem_ptable {
|
||||
u32 magic;
|
||||
u32 version;
|
||||
u32 num_entries;
|
||||
u32 reserved[5];
|
||||
struct smem_ptable_entry entry[];
|
||||
};
|
||||
#define SMEM_PTABLE_MAGIC 0x434f5424 /* "$TOC" */
|
||||
|
||||
/**
|
||||
* struct smem_partition_header - header of the partitions
|
||||
* @magic: magic number, must be SMEM_PART_MAGIC
|
||||
* @host0: first processor/host with access to this partition
|
||||
* @host1: second processor/host with access to this partition
|
||||
* @size: size of the partition
|
||||
* @offset_free_uncached: offset to the first free byte of uncached memory in
|
||||
* this partition
|
||||
* @offset_free_cached: offset to the first free byte of cached memory in this
|
||||
* partition
|
||||
* @reserved: for now reserved entries
|
||||
*/
|
||||
struct smem_partition_header {
|
||||
u32 magic;
|
||||
u16 host0;
|
||||
u16 host1;
|
||||
u32 size;
|
||||
u32 offset_free_uncached;
|
||||
u32 offset_free_cached;
|
||||
u32 reserved[3];
|
||||
};
|
||||
#define SMEM_PART_MAGIC 0x54525024 /* "$PRT" */
|
||||
|
||||
/**
|
||||
* struct smem_private_entry - header of each item in the private partition
|
||||
* @canary: magic number, must be SMEM_PRIVATE_CANARY
|
||||
* @item: identifying number of the smem item
|
||||
* @size: size of the data, including padding bytes
|
||||
* @padding_data: number of bytes of padding of data
|
||||
* @padding_hdr: number of bytes of padding between the header and the data
|
||||
* @reserved: for now reserved entry
|
||||
*/
|
||||
struct smem_private_entry {
|
||||
u16 canary;
|
||||
u16 item;
|
||||
u32 size; /* includes padding bytes */
|
||||
u16 padding_data;
|
||||
u16 padding_hdr;
|
||||
u32 reserved;
|
||||
};
|
||||
#define SMEM_PRIVATE_CANARY 0xa5a5
|
||||
|
||||
/**
|
||||
* struct smem_region - representation of a chunk of memory used for smem
|
||||
* @aux_base: identifier of aux_mem base
|
||||
* @virt_base: virtual base address of memory with this aux_mem identifier
|
||||
* @size: size of the memory region
|
||||
*/
|
||||
struct smem_region {
|
||||
u32 aux_base;
|
||||
void __iomem *virt_base;
|
||||
size_t size;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct qcom_smem - device data for the smem device
|
||||
* @dev: device pointer
|
||||
* @hwlock: reference to a hwspinlock
|
||||
* @partitions: list of pointers to partitions affecting the current
|
||||
* processor/host
|
||||
* @num_regions: number of @regions
|
||||
* @regions: list of the memory regions defining the shared memory
|
||||
*/
|
||||
struct qcom_smem {
|
||||
struct device *dev;
|
||||
|
||||
struct hwspinlock *hwlock;
|
||||
|
||||
struct smem_partition_header *partitions[SMEM_HOST_COUNT];
|
||||
|
||||
unsigned num_regions;
|
||||
struct smem_region regions[0];
|
||||
};
|
||||
|
||||
/* Pointer to the one and only smem handle */
|
||||
static struct qcom_smem *__smem;
|
||||
|
||||
/* Timeout (ms) for the trylock of remote spinlocks */
|
||||
#define HWSPINLOCK_TIMEOUT 1000
|
||||
|
||||
static int qcom_smem_alloc_private(struct qcom_smem *smem,
|
||||
unsigned host,
|
||||
unsigned item,
|
||||
size_t size)
|
||||
{
|
||||
struct smem_partition_header *phdr;
|
||||
struct smem_private_entry *hdr;
|
||||
size_t alloc_size;
|
||||
void *p;
|
||||
|
||||
/* We're not going to find it if there's no matching partition */
|
||||
if (host >= SMEM_HOST_COUNT || !smem->partitions[host])
|
||||
return -ENOENT;
|
||||
|
||||
phdr = smem->partitions[host];
|
||||
|
||||
p = (void *)phdr + sizeof(*phdr);
|
||||
while (p < (void *)phdr + phdr->offset_free_uncached) {
|
||||
hdr = p;
|
||||
|
||||
if (hdr->canary != SMEM_PRIVATE_CANARY) {
|
||||
dev_err(smem->dev,
|
||||
"Found invalid canary in host %d partition\n",
|
||||
host);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (hdr->item == item)
|
||||
return -EEXIST;
|
||||
|
||||
p += sizeof(*hdr) + hdr->padding_hdr + hdr->size;
|
||||
}
|
||||
|
||||
/* Check that we don't grow into the cached region */
|
||||
alloc_size = sizeof(*hdr) + ALIGN(size, 8);
|
||||
if (p + alloc_size >= (void *)phdr + phdr->offset_free_cached) {
|
||||
dev_err(smem->dev, "Out of memory\n");
|
||||
return -ENOSPC;
|
||||
}
|
||||
|
||||
hdr = p;
|
||||
hdr->canary = SMEM_PRIVATE_CANARY;
|
||||
hdr->item = item;
|
||||
hdr->size = ALIGN(size, 8);
|
||||
hdr->padding_data = hdr->size - size;
|
||||
hdr->padding_hdr = 0;
|
||||
|
||||
/*
|
||||
* Ensure the header is written before we advance the free offset, so
|
||||
* that remote processors that does not take the remote spinlock still
|
||||
* gets a consistent view of the linked list.
|
||||
*/
|
||||
wmb();
|
||||
phdr->offset_free_uncached += alloc_size;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int qcom_smem_alloc_global(struct qcom_smem *smem,
|
||||
unsigned item,
|
||||
size_t size)
|
||||
{
|
||||
struct smem_header *header;
|
||||
struct smem_global_entry *entry;
|
||||
|
||||
if (WARN_ON(item >= SMEM_ITEM_COUNT))
|
||||
return -EINVAL;
|
||||
|
||||
header = smem->regions[0].virt_base;
|
||||
entry = &header->toc[item];
|
||||
if (entry->allocated)
|
||||
return -EEXIST;
|
||||
|
||||
size = ALIGN(size, 8);
|
||||
if (WARN_ON(size > header->available))
|
||||
return -ENOMEM;
|
||||
|
||||
entry->offset = header->free_offset;
|
||||
entry->size = size;
|
||||
|
||||
/*
|
||||
* Ensure the header is consistent before we mark the item allocated,
|
||||
* so that remote processors will get a consistent view of the item
|
||||
* even though they do not take the spinlock on read.
|
||||
*/
|
||||
wmb();
|
||||
entry->allocated = 1;
|
||||
|
||||
header->free_offset += size;
|
||||
header->available -= size;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* qcom_smem_alloc() - allocate space for a smem item
|
||||
* @host: remote processor id, or -1
|
||||
* @item: smem item handle
|
||||
* @size: number of bytes to be allocated
|
||||
*
|
||||
* Allocate space for a given smem item of size @size, given that the item is
|
||||
* not yet allocated.
|
||||
*/
|
||||
int qcom_smem_alloc(unsigned host, unsigned item, size_t size)
|
||||
{
|
||||
unsigned long flags;
|
||||
int ret;
|
||||
|
||||
if (!__smem)
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
if (item < SMEM_ITEM_LAST_FIXED) {
|
||||
dev_err(__smem->dev,
|
||||
"Rejecting allocation of static entry %d\n", item);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = hwspin_lock_timeout_irqsave(__smem->hwlock,
|
||||
HWSPINLOCK_TIMEOUT,
|
||||
&flags);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = qcom_smem_alloc_private(__smem, host, item, size);
|
||||
if (ret == -ENOENT)
|
||||
ret = qcom_smem_alloc_global(__smem, item, size);
|
||||
|
||||
hwspin_unlock_irqrestore(__smem->hwlock, &flags);
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(qcom_smem_alloc);
|
||||
|
||||
static int qcom_smem_get_global(struct qcom_smem *smem,
|
||||
unsigned item,
|
||||
void **ptr,
|
||||
size_t *size)
|
||||
{
|
||||
struct smem_header *header;
|
||||
struct smem_region *area;
|
||||
struct smem_global_entry *entry;
|
||||
u32 aux_base;
|
||||
unsigned i;
|
||||
|
||||
if (WARN_ON(item >= SMEM_ITEM_COUNT))
|
||||
return -EINVAL;
|
||||
|
||||
header = smem->regions[0].virt_base;
|
||||
entry = &header->toc[item];
|
||||
if (!entry->allocated)
|
||||
return -ENXIO;
|
||||
|
||||
if (ptr != NULL) {
|
||||
aux_base = entry->aux_base & AUX_BASE_MASK;
|
||||
|
||||
for (i = 0; i < smem->num_regions; i++) {
|
||||
area = &smem->regions[i];
|
||||
|
||||
if (area->aux_base == aux_base || !aux_base) {
|
||||
*ptr = area->virt_base + entry->offset;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
if (size != NULL)
|
||||
*size = entry->size;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int qcom_smem_get_private(struct qcom_smem *smem,
|
||||
unsigned host,
|
||||
unsigned item,
|
||||
void **ptr,
|
||||
size_t *size)
|
||||
{
|
||||
struct smem_partition_header *phdr;
|
||||
struct smem_private_entry *hdr;
|
||||
void *p;
|
||||
|
||||
/* We're not going to find it if there's no matching partition */
|
||||
if (host >= SMEM_HOST_COUNT || !smem->partitions[host])
|
||||
return -ENOENT;
|
||||
|
||||
phdr = smem->partitions[host];
|
||||
|
||||
p = (void *)phdr + sizeof(*phdr);
|
||||
while (p < (void *)phdr + phdr->offset_free_uncached) {
|
||||
hdr = p;
|
||||
|
||||
if (hdr->canary != SMEM_PRIVATE_CANARY) {
|
||||
dev_err(smem->dev,
|
||||
"Found invalid canary in host %d partition\n",
|
||||
host);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (hdr->item == item) {
|
||||
if (ptr != NULL)
|
||||
*ptr = p + sizeof(*hdr) + hdr->padding_hdr;
|
||||
|
||||
if (size != NULL)
|
||||
*size = hdr->size - hdr->padding_data;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
p += sizeof(*hdr) + hdr->padding_hdr + hdr->size;
|
||||
}
|
||||
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
/**
|
||||
* qcom_smem_get() - resolve ptr of size of a smem item
|
||||
* @host: the remote processor, or -1
|
||||
* @item: smem item handle
|
||||
* @ptr: pointer to be filled out with address of the item
|
||||
* @size: pointer to be filled out with size of the item
|
||||
*
|
||||
* Looks up pointer and size of a smem item.
|
||||
*/
|
||||
int qcom_smem_get(unsigned host, unsigned item, void **ptr, size_t *size)
|
||||
{
|
||||
unsigned long flags;
|
||||
int ret;
|
||||
|
||||
if (!__smem)
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
ret = hwspin_lock_timeout_irqsave(__smem->hwlock,
|
||||
HWSPINLOCK_TIMEOUT,
|
||||
&flags);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = qcom_smem_get_private(__smem, host, item, ptr, size);
|
||||
if (ret == -ENOENT)
|
||||
ret = qcom_smem_get_global(__smem, item, ptr, size);
|
||||
|
||||
hwspin_unlock_irqrestore(__smem->hwlock, &flags);
|
||||
return ret;
|
||||
|
||||
}
|
||||
EXPORT_SYMBOL(qcom_smem_get);
|
||||
|
||||
/**
|
||||
* qcom_smem_get_free_space() - retrieve amount of free space in a partition
|
||||
* @host: the remote processor identifying a partition, or -1
|
||||
*
|
||||
* To be used by smem clients as a quick way to determine if any new
|
||||
* allocations has been made.
|
||||
*/
|
||||
int qcom_smem_get_free_space(unsigned host)
|
||||
{
|
||||
struct smem_partition_header *phdr;
|
||||
struct smem_header *header;
|
||||
unsigned ret;
|
||||
|
||||
if (!__smem)
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
if (host < SMEM_HOST_COUNT && __smem->partitions[host]) {
|
||||
phdr = __smem->partitions[host];
|
||||
ret = phdr->offset_free_cached - phdr->offset_free_uncached;
|
||||
} else {
|
||||
header = __smem->regions[0].virt_base;
|
||||
ret = header->available;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(qcom_smem_get_free_space);
|
||||
|
||||
static int qcom_smem_get_sbl_version(struct qcom_smem *smem)
|
||||
{
|
||||
unsigned *versions;
|
||||
size_t size;
|
||||
int ret;
|
||||
|
||||
ret = qcom_smem_get_global(smem, SMEM_ITEM_VERSION,
|
||||
(void **)&versions, &size);
|
||||
if (ret < 0) {
|
||||
dev_err(smem->dev, "Unable to read the version item\n");
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
if (size < sizeof(unsigned) * SMEM_MASTER_SBL_VERSION_INDEX) {
|
||||
dev_err(smem->dev, "Version item is too small\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return versions[SMEM_MASTER_SBL_VERSION_INDEX];
|
||||
}
|
||||
|
||||
static int qcom_smem_enumerate_partitions(struct qcom_smem *smem,
|
||||
unsigned local_host)
|
||||
{
|
||||
struct smem_partition_header *header;
|
||||
struct smem_ptable_entry *entry;
|
||||
struct smem_ptable *ptable;
|
||||
unsigned remote_host;
|
||||
int i;
|
||||
|
||||
ptable = smem->regions[0].virt_base + smem->regions[0].size - SZ_4K;
|
||||
if (ptable->magic != SMEM_PTABLE_MAGIC)
|
||||
return 0;
|
||||
|
||||
if (ptable->version != 1) {
|
||||
dev_err(smem->dev,
|
||||
"Unsupported partition header version %d\n",
|
||||
ptable->version);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
for (i = 0; i < ptable->num_entries; i++) {
|
||||
entry = &ptable->entry[i];
|
||||
|
||||
if (entry->host0 != local_host && entry->host1 != local_host)
|
||||
continue;
|
||||
|
||||
if (!entry->offset)
|
||||
continue;
|
||||
|
||||
if (!entry->size)
|
||||
continue;
|
||||
|
||||
if (entry->host0 == local_host)
|
||||
remote_host = entry->host1;
|
||||
else
|
||||
remote_host = entry->host0;
|
||||
|
||||
if (remote_host >= SMEM_HOST_COUNT) {
|
||||
dev_err(smem->dev,
|
||||
"Invalid remote host %d\n",
|
||||
remote_host);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (smem->partitions[remote_host]) {
|
||||
dev_err(smem->dev,
|
||||
"Already found a partition for host %d\n",
|
||||
remote_host);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
header = smem->regions[0].virt_base + entry->offset;
|
||||
|
||||
if (header->magic != SMEM_PART_MAGIC) {
|
||||
dev_err(smem->dev,
|
||||
"Partition %d has invalid magic\n", i);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (header->host0 != local_host && header->host1 != local_host) {
|
||||
dev_err(smem->dev,
|
||||
"Partition %d hosts are invalid\n", i);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (header->host0 != remote_host && header->host1 != remote_host) {
|
||||
dev_err(smem->dev,
|
||||
"Partition %d hosts are invalid\n", i);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (header->size != entry->size) {
|
||||
dev_err(smem->dev,
|
||||
"Partition %d has invalid size\n", i);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (header->offset_free_uncached > header->size) {
|
||||
dev_err(smem->dev,
|
||||
"Partition %d has invalid free pointer\n", i);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
smem->partitions[remote_host] = header;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int qcom_smem_count_mem_regions(struct platform_device *pdev)
|
||||
{
|
||||
struct resource *res;
|
||||
int num_regions = 0;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < pdev->num_resources; i++) {
|
||||
res = &pdev->resource[i];
|
||||
|
||||
if (resource_type(res) == IORESOURCE_MEM)
|
||||
num_regions++;
|
||||
}
|
||||
|
||||
return num_regions;
|
||||
}
|
||||
|
||||
static int qcom_smem_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct smem_header *header;
|
||||
struct device_node *np;
|
||||
struct qcom_smem *smem;
|
||||
struct resource *res;
|
||||
struct resource r;
|
||||
size_t array_size;
|
||||
int num_regions = 0;
|
||||
int hwlock_id;
|
||||
u32 version;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
num_regions = qcom_smem_count_mem_regions(pdev) + 1;
|
||||
|
||||
array_size = num_regions * sizeof(struct smem_region);
|
||||
smem = devm_kzalloc(&pdev->dev, sizeof(*smem) + array_size, GFP_KERNEL);
|
||||
if (!smem)
|
||||
return -ENOMEM;
|
||||
|
||||
smem->dev = &pdev->dev;
|
||||
smem->num_regions = num_regions;
|
||||
|
||||
np = of_parse_phandle(pdev->dev.of_node, "memory-region", 0);
|
||||
if (!np) {
|
||||
dev_err(&pdev->dev, "No memory-region specified\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = of_address_to_resource(np, 0, &r);
|
||||
of_node_put(np);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
smem->regions[0].aux_base = (u32)r.start;
|
||||
smem->regions[0].size = resource_size(&r);
|
||||
smem->regions[0].virt_base = devm_ioremap_nocache(&pdev->dev,
|
||||
r.start,
|
||||
resource_size(&r));
|
||||
if (!smem->regions[0].virt_base)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 1; i < num_regions; i++) {
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, i - 1);
|
||||
|
||||
smem->regions[i].aux_base = (u32)res->start;
|
||||
smem->regions[i].size = resource_size(res);
|
||||
smem->regions[i].virt_base = devm_ioremap_nocache(&pdev->dev,
|
||||
res->start,
|
||||
resource_size(res));
|
||||
if (!smem->regions[i].virt_base)
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
header = smem->regions[0].virt_base;
|
||||
if (header->initialized != 1 || header->reserved) {
|
||||
dev_err(&pdev->dev, "SMEM is not initialized by SBL\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
version = qcom_smem_get_sbl_version(smem);
|
||||
if (version >> 16 != SMEM_EXPECTED_VERSION) {
|
||||
dev_err(&pdev->dev, "Unsupported SMEM version 0x%x\n", version);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = qcom_smem_enumerate_partitions(smem, SMEM_HOST_APPS);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0);
|
||||
if (hwlock_id < 0) {
|
||||
dev_err(&pdev->dev, "failed to retrieve hwlock\n");
|
||||
return hwlock_id;
|
||||
}
|
||||
|
||||
smem->hwlock = hwspin_lock_request_specific(hwlock_id);
|
||||
if (!smem->hwlock)
|
||||
return -ENXIO;
|
||||
|
||||
__smem = smem;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int qcom_smem_remove(struct platform_device *pdev)
|
||||
{
|
||||
__smem = NULL;
|
||||
hwspin_lock_free(__smem->hwlock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id qcom_smem_of_match[] = {
|
||||
{ .compatible = "qcom,smem" },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, qcom_smem_of_match);
|
||||
|
||||
static struct platform_driver qcom_smem_driver = {
|
||||
.probe = qcom_smem_probe,
|
||||
.remove = qcom_smem_remove,
|
||||
.driver = {
|
||||
.name = "qcom-smem",
|
||||
.of_match_table = qcom_smem_of_match,
|
||||
.suppress_bind_attrs = true,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init qcom_smem_init(void)
|
||||
{
|
||||
return platform_driver_register(&qcom_smem_driver);
|
||||
}
|
||||
arch_initcall(qcom_smem_init);
|
||||
|
||||
static void __exit qcom_smem_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&qcom_smem_driver);
|
||||
}
|
||||
module_exit(qcom_smem_exit)
|
||||
|
||||
MODULE_AUTHOR("Bjorn Andersson <[email protected]>");
|
||||
MODULE_DESCRIPTION("Qualcomm Shared Memory Manager");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
obj-$(CONFIG_ARCH_TEGRA) += fuse/
|
||||
obj-y += fuse/
|
||||
|
||||
obj-$(CONFIG_ARCH_TEGRA) += common.o
|
||||
obj-$(CONFIG_ARCH_TEGRA) += pmc.o
|
||||
obj-y += common.o
|
||||
obj-y += pmc.o
|
||||
|
|
|
|||
|
|
@ -15,6 +15,8 @@ static const struct of_device_id tegra_machine_match[] = {
|
|||
{ .compatible = "nvidia,tegra30", },
|
||||
{ .compatible = "nvidia,tegra114", },
|
||||
{ .compatible = "nvidia,tegra124", },
|
||||
{ .compatible = "nvidia,tegra132", },
|
||||
{ .compatible = "nvidia,tegra210", },
|
||||
{ }
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -6,3 +6,5 @@ obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += speedo-tegra20.o
|
|||
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += speedo-tegra30.o
|
||||
obj-$(CONFIG_ARCH_TEGRA_114_SOC) += speedo-tegra114.o
|
||||
obj-$(CONFIG_ARCH_TEGRA_124_SOC) += speedo-tegra124.o
|
||||
obj-$(CONFIG_ARCH_TEGRA_132_SOC) += speedo-tegra124.o
|
||||
obj-$(CONFIG_ARCH_TEGRA_210_SOC) += speedo-tegra210.o
|
||||
|
|
|
|||
|
|
@ -15,9 +15,10 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/kobject.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
|
|
@ -28,8 +29,6 @@
|
|||
|
||||
#include "fuse.h"
|
||||
|
||||
static u32 (*fuse_readl)(const unsigned int offset);
|
||||
static int fuse_size;
|
||||
struct tegra_sku_info tegra_sku_info;
|
||||
EXPORT_SYMBOL(tegra_sku_info);
|
||||
|
||||
|
|
@ -42,11 +41,11 @@ static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
|
|||
[TEGRA_REVISION_A04] = "A04",
|
||||
};
|
||||
|
||||
static u8 fuse_readb(const unsigned int offset)
|
||||
static u8 fuse_readb(struct tegra_fuse *fuse, unsigned int offset)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
val = fuse_readl(round_down(offset, 4));
|
||||
val = fuse->read(fuse, round_down(offset, 4));
|
||||
val >>= (offset % 4) * 8;
|
||||
val &= 0xff;
|
||||
|
||||
|
|
@ -54,19 +53,21 @@ static u8 fuse_readb(const unsigned int offset)
|
|||
}
|
||||
|
||||
static ssize_t fuse_read(struct file *fd, struct kobject *kobj,
|
||||
struct bin_attribute *attr, char *buf,
|
||||
loff_t pos, size_t size)
|
||||
struct bin_attribute *attr, char *buf,
|
||||
loff_t pos, size_t size)
|
||||
{
|
||||
struct device *dev = kobj_to_dev(kobj);
|
||||
struct tegra_fuse *fuse = dev_get_drvdata(dev);
|
||||
int i;
|
||||
|
||||
if (pos < 0 || pos >= fuse_size)
|
||||
if (pos < 0 || pos >= attr->size)
|
||||
return 0;
|
||||
|
||||
if (size > fuse_size - pos)
|
||||
size = fuse_size - pos;
|
||||
if (size > attr->size - pos)
|
||||
size = attr->size - pos;
|
||||
|
||||
for (i = 0; i < size; i++)
|
||||
buf[i] = fuse_readb(pos + i);
|
||||
buf[i] = fuse_readb(fuse, pos + i);
|
||||
|
||||
return i;
|
||||
}
|
||||
|
|
@ -76,15 +77,122 @@ static struct bin_attribute fuse_bin_attr = {
|
|||
.read = fuse_read,
|
||||
};
|
||||
|
||||
static int tegra_fuse_create_sysfs(struct device *dev, unsigned int size,
|
||||
const struct tegra_fuse_info *info)
|
||||
{
|
||||
fuse_bin_attr.size = size;
|
||||
|
||||
return device_create_bin_file(dev, &fuse_bin_attr);
|
||||
}
|
||||
|
||||
static const struct of_device_id car_match[] __initconst = {
|
||||
{ .compatible = "nvidia,tegra20-car", },
|
||||
{ .compatible = "nvidia,tegra30-car", },
|
||||
{ .compatible = "nvidia,tegra114-car", },
|
||||
{ .compatible = "nvidia,tegra124-car", },
|
||||
{ .compatible = "nvidia,tegra132-car", },
|
||||
{ .compatible = "nvidia,tegra210-car", },
|
||||
{},
|
||||
};
|
||||
|
||||
static struct tegra_fuse *fuse = &(struct tegra_fuse) {
|
||||
.base = NULL,
|
||||
.soc = NULL,
|
||||
};
|
||||
|
||||
static const struct of_device_id tegra_fuse_match[] = {
|
||||
#ifdef CONFIG_ARCH_TEGRA_210_SOC
|
||||
{ .compatible = "nvidia,tegra210-efuse", .data = &tegra210_fuse_soc },
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_TEGRA_132_SOC
|
||||
{ .compatible = "nvidia,tegra132-efuse", .data = &tegra124_fuse_soc },
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_TEGRA_124_SOC
|
||||
{ .compatible = "nvidia,tegra124-efuse", .data = &tegra124_fuse_soc },
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_TEGRA_114_SOC
|
||||
{ .compatible = "nvidia,tegra114-efuse", .data = &tegra114_fuse_soc },
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
|
||||
{ .compatible = "nvidia,tegra30-efuse", .data = &tegra30_fuse_soc },
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
|
||||
{ .compatible = "nvidia,tegra20-efuse", .data = &tegra20_fuse_soc },
|
||||
#endif
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static int tegra_fuse_probe(struct platform_device *pdev)
|
||||
{
|
||||
void __iomem *base = fuse->base;
|
||||
struct resource *res;
|
||||
int err;
|
||||
|
||||
/* take over the memory region from the early initialization */
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
fuse->base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(fuse->base))
|
||||
return PTR_ERR(fuse->base);
|
||||
|
||||
fuse->clk = devm_clk_get(&pdev->dev, "fuse");
|
||||
if (IS_ERR(fuse->clk)) {
|
||||
dev_err(&pdev->dev, "failed to get FUSE clock: %ld",
|
||||
PTR_ERR(fuse->clk));
|
||||
return PTR_ERR(fuse->clk);
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, fuse);
|
||||
fuse->dev = &pdev->dev;
|
||||
|
||||
if (fuse->soc->probe) {
|
||||
err = fuse->soc->probe(fuse);
|
||||
if (err < 0)
|
||||
return err;
|
||||
}
|
||||
|
||||
if (tegra_fuse_create_sysfs(&pdev->dev, fuse->soc->info->size,
|
||||
fuse->soc->info))
|
||||
return -ENODEV;
|
||||
|
||||
/* release the early I/O memory mapping */
|
||||
iounmap(base);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver tegra_fuse_driver = {
|
||||
.driver = {
|
||||
.name = "tegra-fuse",
|
||||
.of_match_table = tegra_fuse_match,
|
||||
.suppress_bind_attrs = true,
|
||||
},
|
||||
.probe = tegra_fuse_probe,
|
||||
};
|
||||
module_platform_driver(tegra_fuse_driver);
|
||||
|
||||
bool __init tegra_fuse_read_spare(unsigned int spare)
|
||||
{
|
||||
unsigned int offset = fuse->soc->info->spare + spare * 4;
|
||||
|
||||
return fuse->read_early(fuse, offset) & 1;
|
||||
}
|
||||
|
||||
u32 __init tegra_fuse_read_early(unsigned int offset)
|
||||
{
|
||||
return fuse->read_early(fuse, offset);
|
||||
}
|
||||
|
||||
int tegra_fuse_readl(unsigned long offset, u32 *value)
|
||||
{
|
||||
if (!fuse->read)
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
*value = fuse->read(fuse, offset);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(tegra_fuse_readl);
|
||||
|
||||
static void tegra_enable_fuse_clk(void __iomem *base)
|
||||
{
|
||||
u32 reg;
|
||||
|
|
@ -102,63 +210,106 @@ static void tegra_enable_fuse_clk(void __iomem *base)
|
|||
writel(reg, base + 0x14);
|
||||
}
|
||||
|
||||
int tegra_fuse_readl(unsigned long offset, u32 *value)
|
||||
{
|
||||
if (!fuse_readl)
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
*value = fuse_readl(offset);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(tegra_fuse_readl);
|
||||
|
||||
int tegra_fuse_create_sysfs(struct device *dev, int size,
|
||||
u32 (*readl)(const unsigned int offset))
|
||||
{
|
||||
if (fuse_size)
|
||||
return -ENODEV;
|
||||
|
||||
fuse_bin_attr.size = size;
|
||||
fuse_bin_attr.read = fuse_read;
|
||||
|
||||
fuse_size = size;
|
||||
fuse_readl = readl;
|
||||
|
||||
return device_create_bin_file(dev, &fuse_bin_attr);
|
||||
}
|
||||
|
||||
static int __init tegra_init_fuse(void)
|
||||
{
|
||||
const struct of_device_id *match;
|
||||
struct device_node *np;
|
||||
void __iomem *car_base;
|
||||
|
||||
if (!soc_is_tegra())
|
||||
return 0;
|
||||
struct resource regs;
|
||||
|
||||
tegra_init_apbmisc();
|
||||
|
||||
np = of_find_matching_node(NULL, car_match);
|
||||
car_base = of_iomap(np, 0);
|
||||
if (car_base) {
|
||||
tegra_enable_fuse_clk(car_base);
|
||||
iounmap(car_base);
|
||||
np = of_find_matching_node_and_match(NULL, tegra_fuse_match, &match);
|
||||
if (!np) {
|
||||
/*
|
||||
* Fall back to legacy initialization for 32-bit ARM only. All
|
||||
* 64-bit ARM device tree files for Tegra are required to have
|
||||
* a FUSE node.
|
||||
*
|
||||
* This is for backwards-compatibility with old device trees
|
||||
* that didn't contain a FUSE node.
|
||||
*/
|
||||
if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
|
||||
u8 chip = tegra_get_chip_id();
|
||||
|
||||
regs.start = 0x7000f800;
|
||||
regs.end = 0x7000fbff;
|
||||
regs.flags = IORESOURCE_MEM;
|
||||
|
||||
switch (chip) {
|
||||
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
|
||||
case TEGRA20:
|
||||
fuse->soc = &tegra20_fuse_soc;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
|
||||
case TEGRA30:
|
||||
fuse->soc = &tegra30_fuse_soc;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_TEGRA_114_SOC
|
||||
case TEGRA114:
|
||||
fuse->soc = &tegra114_fuse_soc;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_TEGRA_124_SOC
|
||||
case TEGRA124:
|
||||
fuse->soc = &tegra124_fuse_soc;
|
||||
break;
|
||||
#endif
|
||||
|
||||
default:
|
||||
pr_warn("Unsupported SoC: %02x\n", chip);
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
/*
|
||||
* At this point we're not running on Tegra, so play
|
||||
* nice with multi-platform kernels.
|
||||
*/
|
||||
return 0;
|
||||
}
|
||||
} else {
|
||||
pr_err("Could not enable fuse clk. ioremap tegra car failed.\n");
|
||||
/*
|
||||
* Extract information from the device tree if we've found a
|
||||
* matching node.
|
||||
*/
|
||||
if (of_address_to_resource(np, 0, ®s) < 0) {
|
||||
pr_err("failed to get FUSE register\n");
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
fuse->soc = match->data;
|
||||
}
|
||||
|
||||
np = of_find_matching_node(NULL, car_match);
|
||||
if (np) {
|
||||
void __iomem *base = of_iomap(np, 0);
|
||||
if (base) {
|
||||
tegra_enable_fuse_clk(base);
|
||||
iounmap(base);
|
||||
} else {
|
||||
pr_err("failed to map clock registers\n");
|
||||
return -ENXIO;
|
||||
}
|
||||
}
|
||||
|
||||
fuse->base = ioremap_nocache(regs.start, resource_size(®s));
|
||||
if (!fuse->base) {
|
||||
pr_err("failed to map FUSE registers\n");
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
if (tegra_get_chip_id() == TEGRA20)
|
||||
tegra20_init_fuse_early();
|
||||
else
|
||||
tegra30_init_fuse_early();
|
||||
fuse->soc->init(fuse);
|
||||
|
||||
pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
|
||||
pr_info("Tegra Revision: %s SKU: %d CPU Process: %d SoC Process: %d\n",
|
||||
tegra_revision_name[tegra_sku_info.revision],
|
||||
tegra_sku_info.sku_id, tegra_sku_info.cpu_process_id,
|
||||
tegra_sku_info.core_process_id);
|
||||
pr_debug("Tegra CPU Speedo ID %d, Soc Speedo ID %d\n",
|
||||
tegra_sku_info.cpu_speedo_id, tegra_sku_info.soc_speedo_id);
|
||||
tegra_sku_info.soc_process_id);
|
||||
pr_debug("Tegra CPU Speedo ID %d, SoC Speedo ID %d\n",
|
||||
tegra_sku_info.cpu_speedo_id, tegra_sku_info.soc_speedo_id);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -34,159 +34,107 @@
|
|||
#include "fuse.h"
|
||||
|
||||
#define FUSE_BEGIN 0x100
|
||||
#define FUSE_SIZE 0x1f8
|
||||
#define FUSE_UID_LOW 0x08
|
||||
#define FUSE_UID_HIGH 0x0c
|
||||
|
||||
static phys_addr_t fuse_phys;
|
||||
static struct clk *fuse_clk;
|
||||
static void __iomem __initdata *fuse_base;
|
||||
|
||||
static DEFINE_MUTEX(apb_dma_lock);
|
||||
static DECLARE_COMPLETION(apb_dma_wait);
|
||||
static struct dma_chan *apb_dma_chan;
|
||||
static struct dma_slave_config dma_sconfig;
|
||||
static u32 *apb_buffer;
|
||||
static dma_addr_t apb_buffer_phys;
|
||||
static u32 tegra20_fuse_read_early(struct tegra_fuse *fuse, unsigned int offset)
|
||||
{
|
||||
return readl_relaxed(fuse->base + FUSE_BEGIN + offset);
|
||||
}
|
||||
|
||||
static void apb_dma_complete(void *args)
|
||||
{
|
||||
complete(&apb_dma_wait);
|
||||
struct tegra_fuse *fuse = args;
|
||||
|
||||
complete(&fuse->apbdma.wait);
|
||||
}
|
||||
|
||||
static u32 tegra20_fuse_readl(const unsigned int offset)
|
||||
static u32 tegra20_fuse_read(struct tegra_fuse *fuse, unsigned int offset)
|
||||
{
|
||||
int ret;
|
||||
u32 val = 0;
|
||||
unsigned long flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK;
|
||||
struct dma_async_tx_descriptor *dma_desc;
|
||||
unsigned long time_left;
|
||||
u32 value = 0;
|
||||
int err;
|
||||
|
||||
mutex_lock(&apb_dma_lock);
|
||||
mutex_lock(&fuse->apbdma.lock);
|
||||
|
||||
dma_sconfig.src_addr = fuse_phys + FUSE_BEGIN + offset;
|
||||
ret = dmaengine_slave_config(apb_dma_chan, &dma_sconfig);
|
||||
if (ret)
|
||||
fuse->apbdma.config.src_addr = fuse->apbdma.phys + FUSE_BEGIN + offset;
|
||||
|
||||
err = dmaengine_slave_config(fuse->apbdma.chan, &fuse->apbdma.config);
|
||||
if (err)
|
||||
goto out;
|
||||
|
||||
dma_desc = dmaengine_prep_slave_single(apb_dma_chan, apb_buffer_phys,
|
||||
sizeof(u32), DMA_DEV_TO_MEM,
|
||||
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
||||
dma_desc = dmaengine_prep_slave_single(fuse->apbdma.chan,
|
||||
fuse->apbdma.phys,
|
||||
sizeof(u32), DMA_DEV_TO_MEM,
|
||||
flags);
|
||||
if (!dma_desc)
|
||||
goto out;
|
||||
|
||||
dma_desc->callback = apb_dma_complete;
|
||||
dma_desc->callback_param = NULL;
|
||||
dma_desc->callback_param = fuse;
|
||||
|
||||
reinit_completion(&apb_dma_wait);
|
||||
reinit_completion(&fuse->apbdma.wait);
|
||||
|
||||
clk_prepare_enable(fuse_clk);
|
||||
clk_prepare_enable(fuse->clk);
|
||||
|
||||
dmaengine_submit(dma_desc);
|
||||
dma_async_issue_pending(apb_dma_chan);
|
||||
time_left = wait_for_completion_timeout(&apb_dma_wait,
|
||||
dma_async_issue_pending(fuse->apbdma.chan);
|
||||
time_left = wait_for_completion_timeout(&fuse->apbdma.wait,
|
||||
msecs_to_jiffies(50));
|
||||
|
||||
if (WARN(time_left == 0, "apb read dma timed out"))
|
||||
dmaengine_terminate_all(apb_dma_chan);
|
||||
dmaengine_terminate_all(fuse->apbdma.chan);
|
||||
else
|
||||
val = *apb_buffer;
|
||||
value = *fuse->apbdma.virt;
|
||||
|
||||
clk_disable_unprepare(fuse->clk);
|
||||
|
||||
clk_disable_unprepare(fuse_clk);
|
||||
out:
|
||||
mutex_unlock(&apb_dma_lock);
|
||||
|
||||
return val;
|
||||
mutex_unlock(&fuse->apbdma.lock);
|
||||
return value;
|
||||
}
|
||||
|
||||
static const struct of_device_id tegra20_fuse_of_match[] = {
|
||||
{ .compatible = "nvidia,tegra20-efuse" },
|
||||
{},
|
||||
};
|
||||
|
||||
static int apb_dma_init(void)
|
||||
static int tegra20_fuse_probe(struct tegra_fuse *fuse)
|
||||
{
|
||||
dma_cap_mask_t mask;
|
||||
|
||||
dma_cap_zero(mask);
|
||||
dma_cap_set(DMA_SLAVE, mask);
|
||||
apb_dma_chan = dma_request_channel(mask, NULL, NULL);
|
||||
if (!apb_dma_chan)
|
||||
|
||||
fuse->apbdma.chan = dma_request_channel(mask, NULL, NULL);
|
||||
if (!fuse->apbdma.chan)
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
apb_buffer = dma_alloc_coherent(NULL, sizeof(u32), &apb_buffer_phys,
|
||||
GFP_KERNEL);
|
||||
if (!apb_buffer) {
|
||||
dma_release_channel(apb_dma_chan);
|
||||
fuse->apbdma.virt = dma_alloc_coherent(fuse->dev, sizeof(u32),
|
||||
&fuse->apbdma.phys,
|
||||
GFP_KERNEL);
|
||||
if (!fuse->apbdma.virt) {
|
||||
dma_release_channel(fuse->apbdma.chan);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
||||
dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
||||
dma_sconfig.src_maxburst = 1;
|
||||
dma_sconfig.dst_maxburst = 1;
|
||||
fuse->apbdma.config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
||||
fuse->apbdma.config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
||||
fuse->apbdma.config.src_maxburst = 1;
|
||||
fuse->apbdma.config.dst_maxburst = 1;
|
||||
|
||||
init_completion(&fuse->apbdma.wait);
|
||||
mutex_init(&fuse->apbdma.lock);
|
||||
fuse->read = tegra20_fuse_read;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra20_fuse_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct resource *res;
|
||||
int err;
|
||||
|
||||
fuse_clk = devm_clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(fuse_clk)) {
|
||||
dev_err(&pdev->dev, "missing clock");
|
||||
return PTR_ERR(fuse_clk);
|
||||
}
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res)
|
||||
return -EINVAL;
|
||||
fuse_phys = res->start;
|
||||
|
||||
err = apb_dma_init();
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
if (tegra_fuse_create_sysfs(&pdev->dev, FUSE_SIZE, tegra20_fuse_readl))
|
||||
return -ENODEV;
|
||||
|
||||
dev_dbg(&pdev->dev, "loaded\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver tegra20_fuse_driver = {
|
||||
.probe = tegra20_fuse_probe,
|
||||
.driver = {
|
||||
.name = "tegra20_fuse",
|
||||
.of_match_table = tegra20_fuse_of_match,
|
||||
}
|
||||
static const struct tegra_fuse_info tegra20_fuse_info = {
|
||||
.read = tegra20_fuse_read,
|
||||
.size = 0x1f8,
|
||||
.spare = 0x100,
|
||||
};
|
||||
|
||||
static int __init tegra20_fuse_init(void)
|
||||
{
|
||||
return platform_driver_register(&tegra20_fuse_driver);
|
||||
}
|
||||
postcore_initcall(tegra20_fuse_init);
|
||||
|
||||
/* Early boot code. This code is called before the devices are created */
|
||||
|
||||
u32 __init tegra20_fuse_early(const unsigned int offset)
|
||||
{
|
||||
return readl_relaxed(fuse_base + FUSE_BEGIN + offset);
|
||||
}
|
||||
|
||||
bool __init tegra20_spare_fuse_early(int spare_bit)
|
||||
{
|
||||
u32 offset = spare_bit * 4;
|
||||
bool value;
|
||||
|
||||
value = tegra20_fuse_early(offset + 0x100);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
static void __init tegra20_fuse_add_randomness(void)
|
||||
{
|
||||
u32 randomness[7];
|
||||
|
|
@ -195,22 +143,27 @@ static void __init tegra20_fuse_add_randomness(void)
|
|||
randomness[1] = tegra_read_straps();
|
||||
randomness[2] = tegra_read_chipid();
|
||||
randomness[3] = tegra_sku_info.cpu_process_id << 16;
|
||||
randomness[3] |= tegra_sku_info.core_process_id;
|
||||
randomness[3] |= tegra_sku_info.soc_process_id;
|
||||
randomness[4] = tegra_sku_info.cpu_speedo_id << 16;
|
||||
randomness[4] |= tegra_sku_info.soc_speedo_id;
|
||||
randomness[5] = tegra20_fuse_early(FUSE_UID_LOW);
|
||||
randomness[6] = tegra20_fuse_early(FUSE_UID_HIGH);
|
||||
randomness[5] = tegra_fuse_read_early(FUSE_UID_LOW);
|
||||
randomness[6] = tegra_fuse_read_early(FUSE_UID_HIGH);
|
||||
|
||||
add_device_randomness(randomness, sizeof(randomness));
|
||||
}
|
||||
|
||||
void __init tegra20_init_fuse_early(void)
|
||||
static void __init tegra20_fuse_init(struct tegra_fuse *fuse)
|
||||
{
|
||||
fuse_base = ioremap(TEGRA_FUSE_BASE, TEGRA_FUSE_SIZE);
|
||||
fuse->read_early = tegra20_fuse_read_early;
|
||||
|
||||
tegra_init_revision();
|
||||
tegra20_init_speedo_data(&tegra_sku_info);
|
||||
fuse->soc->speedo_init(&tegra_sku_info);
|
||||
tegra20_fuse_add_randomness();
|
||||
|
||||
iounmap(fuse_base);
|
||||
}
|
||||
|
||||
const struct tegra_fuse_soc tegra20_fuse_soc = {
|
||||
.init = tegra20_fuse_init,
|
||||
.speedo_init = tegra20_init_speedo_data,
|
||||
.probe = tegra20_fuse_probe,
|
||||
.info = &tegra20_fuse_info,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -42,114 +42,34 @@
|
|||
|
||||
#define FUSE_HAS_REVISION_INFO BIT(0)
|
||||
|
||||
enum speedo_idx {
|
||||
SPEEDO_TEGRA30 = 0,
|
||||
SPEEDO_TEGRA114,
|
||||
SPEEDO_TEGRA124,
|
||||
};
|
||||
|
||||
struct tegra_fuse_info {
|
||||
int size;
|
||||
int spare_bit;
|
||||
enum speedo_idx speedo_idx;
|
||||
};
|
||||
|
||||
static void __iomem *fuse_base;
|
||||
static struct clk *fuse_clk;
|
||||
static const struct tegra_fuse_info *fuse_info;
|
||||
|
||||
u32 tegra30_fuse_readl(const unsigned int offset)
|
||||
#if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \
|
||||
defined(CONFIG_ARCH_TEGRA_114_SOC) || \
|
||||
defined(CONFIG_ARCH_TEGRA_124_SOC) || \
|
||||
defined(CONFIG_ARCH_TEGRA_132_SOC) || \
|
||||
defined(CONFIG_ARCH_TEGRA_210_SOC)
|
||||
static u32 tegra30_fuse_read_early(struct tegra_fuse *fuse, unsigned int offset)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
/*
|
||||
* early in the boot, the fuse clock will be enabled by
|
||||
* tegra_init_fuse()
|
||||
*/
|
||||
|
||||
if (fuse_clk)
|
||||
clk_prepare_enable(fuse_clk);
|
||||
|
||||
val = readl_relaxed(fuse_base + FUSE_BEGIN + offset);
|
||||
|
||||
if (fuse_clk)
|
||||
clk_disable_unprepare(fuse_clk);
|
||||
|
||||
return val;
|
||||
return readl_relaxed(fuse->base + FUSE_BEGIN + offset);
|
||||
}
|
||||
|
||||
static const struct tegra_fuse_info tegra30_info = {
|
||||
.size = 0x2a4,
|
||||
.spare_bit = 0x144,
|
||||
.speedo_idx = SPEEDO_TEGRA30,
|
||||
};
|
||||
|
||||
static const struct tegra_fuse_info tegra114_info = {
|
||||
.size = 0x2a0,
|
||||
.speedo_idx = SPEEDO_TEGRA114,
|
||||
};
|
||||
|
||||
static const struct tegra_fuse_info tegra124_info = {
|
||||
.size = 0x300,
|
||||
.speedo_idx = SPEEDO_TEGRA124,
|
||||
};
|
||||
|
||||
static const struct of_device_id tegra30_fuse_of_match[] = {
|
||||
{ .compatible = "nvidia,tegra30-efuse", .data = &tegra30_info },
|
||||
{ .compatible = "nvidia,tegra114-efuse", .data = &tegra114_info },
|
||||
{ .compatible = "nvidia,tegra124-efuse", .data = &tegra124_info },
|
||||
{},
|
||||
};
|
||||
|
||||
static int tegra30_fuse_probe(struct platform_device *pdev)
|
||||
static u32 tegra30_fuse_read(struct tegra_fuse *fuse, unsigned int offset)
|
||||
{
|
||||
const struct of_device_id *of_dev_id;
|
||||
u32 value;
|
||||
int err;
|
||||
|
||||
of_dev_id = of_match_device(tegra30_fuse_of_match, &pdev->dev);
|
||||
if (!of_dev_id)
|
||||
return -ENODEV;
|
||||
|
||||
fuse_clk = devm_clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(fuse_clk)) {
|
||||
dev_err(&pdev->dev, "missing clock");
|
||||
return PTR_ERR(fuse_clk);
|
||||
err = clk_prepare_enable(fuse->clk);
|
||||
if (err < 0) {
|
||||
dev_err(fuse->dev, "failed to enable FUSE clock: %d\n", err);
|
||||
return 0;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
value = readl_relaxed(fuse->base + FUSE_BEGIN + offset);
|
||||
|
||||
if (tegra_fuse_create_sysfs(&pdev->dev, fuse_info->size,
|
||||
tegra30_fuse_readl))
|
||||
return -ENODEV;
|
||||
clk_disable_unprepare(fuse->clk);
|
||||
|
||||
dev_dbg(&pdev->dev, "loaded\n");
|
||||
|
||||
return 0;
|
||||
return value;
|
||||
}
|
||||
|
||||
static struct platform_driver tegra30_fuse_driver = {
|
||||
.probe = tegra30_fuse_probe,
|
||||
.driver = {
|
||||
.name = "tegra_fuse",
|
||||
.of_match_table = tegra30_fuse_of_match,
|
||||
}
|
||||
};
|
||||
|
||||
static int __init tegra30_fuse_init(void)
|
||||
{
|
||||
return platform_driver_register(&tegra30_fuse_driver);
|
||||
}
|
||||
postcore_initcall(tegra30_fuse_init);
|
||||
|
||||
/* Early boot code. This code is called before the devices are created */
|
||||
|
||||
typedef void (*speedo_f)(struct tegra_sku_info *sku_info);
|
||||
|
||||
static speedo_f __initdata speedo_tbl[] = {
|
||||
[SPEEDO_TEGRA30] = tegra30_init_speedo_data,
|
||||
[SPEEDO_TEGRA114] = tegra114_init_speedo_data,
|
||||
[SPEEDO_TEGRA124] = tegra124_init_speedo_data,
|
||||
};
|
||||
|
||||
static void __init tegra30_fuse_add_randomness(void)
|
||||
{
|
||||
u32 randomness[12];
|
||||
|
|
@ -158,67 +78,83 @@ static void __init tegra30_fuse_add_randomness(void)
|
|||
randomness[1] = tegra_read_straps();
|
||||
randomness[2] = tegra_read_chipid();
|
||||
randomness[3] = tegra_sku_info.cpu_process_id << 16;
|
||||
randomness[3] |= tegra_sku_info.core_process_id;
|
||||
randomness[3] |= tegra_sku_info.soc_process_id;
|
||||
randomness[4] = tegra_sku_info.cpu_speedo_id << 16;
|
||||
randomness[4] |= tegra_sku_info.soc_speedo_id;
|
||||
randomness[5] = tegra30_fuse_readl(FUSE_VENDOR_CODE);
|
||||
randomness[6] = tegra30_fuse_readl(FUSE_FAB_CODE);
|
||||
randomness[7] = tegra30_fuse_readl(FUSE_LOT_CODE_0);
|
||||
randomness[8] = tegra30_fuse_readl(FUSE_LOT_CODE_1);
|
||||
randomness[9] = tegra30_fuse_readl(FUSE_WAFER_ID);
|
||||
randomness[10] = tegra30_fuse_readl(FUSE_X_COORDINATE);
|
||||
randomness[11] = tegra30_fuse_readl(FUSE_Y_COORDINATE);
|
||||
randomness[5] = tegra_fuse_read_early(FUSE_VENDOR_CODE);
|
||||
randomness[6] = tegra_fuse_read_early(FUSE_FAB_CODE);
|
||||
randomness[7] = tegra_fuse_read_early(FUSE_LOT_CODE_0);
|
||||
randomness[8] = tegra_fuse_read_early(FUSE_LOT_CODE_1);
|
||||
randomness[9] = tegra_fuse_read_early(FUSE_WAFER_ID);
|
||||
randomness[10] = tegra_fuse_read_early(FUSE_X_COORDINATE);
|
||||
randomness[11] = tegra_fuse_read_early(FUSE_Y_COORDINATE);
|
||||
|
||||
add_device_randomness(randomness, sizeof(randomness));
|
||||
}
|
||||
|
||||
static void __init legacy_fuse_init(void)
|
||||
static void __init tegra30_fuse_init(struct tegra_fuse *fuse)
|
||||
{
|
||||
switch (tegra_get_chip_id()) {
|
||||
case TEGRA30:
|
||||
fuse_info = &tegra30_info;
|
||||
break;
|
||||
case TEGRA114:
|
||||
fuse_info = &tegra114_info;
|
||||
break;
|
||||
case TEGRA124:
|
||||
case TEGRA132:
|
||||
fuse_info = &tegra124_info;
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
|
||||
fuse_base = ioremap(TEGRA_FUSE_BASE, TEGRA_FUSE_SIZE);
|
||||
}
|
||||
|
||||
bool __init tegra30_spare_fuse(int spare_bit)
|
||||
{
|
||||
u32 offset = fuse_info->spare_bit + spare_bit * 4;
|
||||
|
||||
return tegra30_fuse_readl(offset) & 1;
|
||||
}
|
||||
|
||||
void __init tegra30_init_fuse_early(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
const struct of_device_id *of_match;
|
||||
|
||||
np = of_find_matching_node_and_match(NULL, tegra30_fuse_of_match,
|
||||
&of_match);
|
||||
if (np) {
|
||||
fuse_base = of_iomap(np, 0);
|
||||
fuse_info = (struct tegra_fuse_info *)of_match->data;
|
||||
} else
|
||||
legacy_fuse_init();
|
||||
|
||||
if (!fuse_base) {
|
||||
pr_warn("fuse DT node missing and unknown chip id: 0x%02x\n",
|
||||
tegra_get_chip_id());
|
||||
return;
|
||||
}
|
||||
fuse->read_early = tegra30_fuse_read_early;
|
||||
fuse->read = tegra30_fuse_read;
|
||||
|
||||
tegra_init_revision();
|
||||
speedo_tbl[fuse_info->speedo_idx](&tegra_sku_info);
|
||||
fuse->soc->speedo_init(&tegra_sku_info);
|
||||
tegra30_fuse_add_randomness();
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
|
||||
static const struct tegra_fuse_info tegra30_fuse_info = {
|
||||
.read = tegra30_fuse_read,
|
||||
.size = 0x2a4,
|
||||
.spare = 0x144,
|
||||
};
|
||||
|
||||
const struct tegra_fuse_soc tegra30_fuse_soc = {
|
||||
.init = tegra30_fuse_init,
|
||||
.speedo_init = tegra30_init_speedo_data,
|
||||
.info = &tegra30_fuse_info,
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_TEGRA_114_SOC
|
||||
static const struct tegra_fuse_info tegra114_fuse_info = {
|
||||
.read = tegra30_fuse_read,
|
||||
.size = 0x2a0,
|
||||
.spare = 0x180,
|
||||
};
|
||||
|
||||
const struct tegra_fuse_soc tegra114_fuse_soc = {
|
||||
.init = tegra30_fuse_init,
|
||||
.speedo_init = tegra114_init_speedo_data,
|
||||
.info = &tegra114_fuse_info,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC)
|
||||
static const struct tegra_fuse_info tegra124_fuse_info = {
|
||||
.read = tegra30_fuse_read,
|
||||
.size = 0x300,
|
||||
.spare = 0x200,
|
||||
};
|
||||
|
||||
const struct tegra_fuse_soc tegra124_fuse_soc = {
|
||||
.init = tegra30_fuse_init,
|
||||
.speedo_init = tegra124_init_speedo_data,
|
||||
.info = &tegra124_fuse_info,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_TEGRA_210_SOC)
|
||||
static const struct tegra_fuse_info tegra210_fuse_info = {
|
||||
.read = tegra30_fuse_read,
|
||||
.size = 0x300,
|
||||
.spare = 0x280,
|
||||
};
|
||||
|
||||
const struct tegra_fuse_soc tegra210_fuse_soc = {
|
||||
.init = tegra30_fuse_init,
|
||||
.speedo_init = tegra210_init_speedo_data,
|
||||
.info = &tegra210_fuse_info,
|
||||
};
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -19,53 +19,90 @@
|
|||
#ifndef __DRIVERS_MISC_TEGRA_FUSE_H
|
||||
#define __DRIVERS_MISC_TEGRA_FUSE_H
|
||||
|
||||
#define TEGRA_FUSE_BASE 0x7000f800
|
||||
#define TEGRA_FUSE_SIZE 0x400
|
||||
#include <linux/dmaengine.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
int tegra_fuse_create_sysfs(struct device *dev, int size,
|
||||
u32 (*readl)(const unsigned int offset));
|
||||
struct tegra_fuse;
|
||||
|
||||
struct tegra_fuse_info {
|
||||
u32 (*read)(struct tegra_fuse *fuse, unsigned int offset);
|
||||
unsigned int size;
|
||||
unsigned int spare;
|
||||
};
|
||||
|
||||
struct tegra_fuse_soc {
|
||||
void (*init)(struct tegra_fuse *fuse);
|
||||
void (*speedo_init)(struct tegra_sku_info *info);
|
||||
int (*probe)(struct tegra_fuse *fuse);
|
||||
|
||||
const struct tegra_fuse_info *info;
|
||||
};
|
||||
|
||||
struct tegra_fuse {
|
||||
struct device *dev;
|
||||
void __iomem *base;
|
||||
phys_addr_t phys;
|
||||
struct clk *clk;
|
||||
|
||||
u32 (*read_early)(struct tegra_fuse *fuse, unsigned int offset);
|
||||
u32 (*read)(struct tegra_fuse *fuse, unsigned int offset);
|
||||
const struct tegra_fuse_soc *soc;
|
||||
|
||||
/* APBDMA on Tegra20 */
|
||||
struct {
|
||||
struct mutex lock;
|
||||
struct completion wait;
|
||||
struct dma_chan *chan;
|
||||
struct dma_slave_config config;
|
||||
dma_addr_t phys;
|
||||
u32 *virt;
|
||||
} apbdma;
|
||||
};
|
||||
|
||||
bool tegra30_spare_fuse(int bit);
|
||||
u32 tegra30_fuse_readl(const unsigned int offset);
|
||||
void tegra30_init_fuse_early(void);
|
||||
void tegra_init_revision(void);
|
||||
void tegra_init_apbmisc(void);
|
||||
|
||||
bool __init tegra_fuse_read_spare(unsigned int spare);
|
||||
u32 __init tegra_fuse_read_early(unsigned int offset);
|
||||
|
||||
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
|
||||
void tegra20_init_speedo_data(struct tegra_sku_info *sku_info);
|
||||
bool tegra20_spare_fuse_early(int spare_bit);
|
||||
void tegra20_init_fuse_early(void);
|
||||
u32 tegra20_fuse_early(const unsigned int offset);
|
||||
#else
|
||||
static inline void tegra20_init_speedo_data(struct tegra_sku_info *sku_info) {}
|
||||
static inline bool tegra20_spare_fuse_early(int spare_bit)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
static inline void tegra20_init_fuse_early(void) {}
|
||||
static inline u32 tegra20_fuse_early(const unsigned int offset)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
|
||||
void tegra30_init_speedo_data(struct tegra_sku_info *sku_info);
|
||||
#else
|
||||
static inline void tegra30_init_speedo_data(struct tegra_sku_info *sku_info) {}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_TEGRA_114_SOC
|
||||
void tegra114_init_speedo_data(struct tegra_sku_info *sku_info);
|
||||
#else
|
||||
static inline void tegra114_init_speedo_data(struct tegra_sku_info *sku_info) {}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_TEGRA_124_SOC
|
||||
#if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC)
|
||||
void tegra124_init_speedo_data(struct tegra_sku_info *sku_info);
|
||||
#else
|
||||
static inline void tegra124_init_speedo_data(struct tegra_sku_info *sku_info) {}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_TEGRA_210_SOC
|
||||
void tegra210_init_speedo_data(struct tegra_sku_info *sku_info);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
|
||||
extern const struct tegra_fuse_soc tegra20_fuse_soc;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
|
||||
extern const struct tegra_fuse_soc tegra30_fuse_soc;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_TEGRA_114_SOC
|
||||
extern const struct tegra_fuse_soc tegra114_fuse_soc;
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC)
|
||||
extern const struct tegra_fuse_soc tegra124_fuse_soc;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_TEGRA_210_SOC
|
||||
extern const struct tegra_fuse_soc tegra210_fuse_soc;
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@
|
|||
|
||||
#include "fuse.h"
|
||||
|
||||
#define CORE_PROCESS_CORNERS 2
|
||||
#define SOC_PROCESS_CORNERS 2
|
||||
#define CPU_PROCESS_CORNERS 2
|
||||
|
||||
enum {
|
||||
|
|
@ -31,7 +31,7 @@ enum {
|
|||
THRESHOLD_INDEX_COUNT,
|
||||
};
|
||||
|
||||
static const u32 __initconst core_process_speedos[][CORE_PROCESS_CORNERS] = {
|
||||
static const u32 __initconst soc_process_speedos[][SOC_PROCESS_CORNERS] = {
|
||||
{1123, UINT_MAX},
|
||||
{0, UINT_MAX},
|
||||
};
|
||||
|
|
@ -74,8 +74,8 @@ static void __init rev_sku_to_speedo_ids(struct tegra_sku_info *sku_info,
|
|||
}
|
||||
|
||||
if (rev == TEGRA_REVISION_A01) {
|
||||
tmp = tegra30_fuse_readl(0x270) << 1;
|
||||
tmp |= tegra30_fuse_readl(0x26c);
|
||||
tmp = tegra_fuse_read_early(0x270) << 1;
|
||||
tmp |= tegra_fuse_read_early(0x26c);
|
||||
if (!tmp)
|
||||
sku_info->cpu_speedo_id = 0;
|
||||
}
|
||||
|
|
@ -84,27 +84,27 @@ static void __init rev_sku_to_speedo_ids(struct tegra_sku_info *sku_info,
|
|||
void __init tegra114_init_speedo_data(struct tegra_sku_info *sku_info)
|
||||
{
|
||||
u32 cpu_speedo_val;
|
||||
u32 core_speedo_val;
|
||||
u32 soc_speedo_val;
|
||||
int threshold;
|
||||
int i;
|
||||
|
||||
BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
|
||||
THRESHOLD_INDEX_COUNT);
|
||||
BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) !=
|
||||
BUILD_BUG_ON(ARRAY_SIZE(soc_process_speedos) !=
|
||||
THRESHOLD_INDEX_COUNT);
|
||||
|
||||
rev_sku_to_speedo_ids(sku_info, &threshold);
|
||||
|
||||
cpu_speedo_val = tegra30_fuse_readl(0x12c) + 1024;
|
||||
core_speedo_val = tegra30_fuse_readl(0x134);
|
||||
cpu_speedo_val = tegra_fuse_read_early(0x12c) + 1024;
|
||||
soc_speedo_val = tegra_fuse_read_early(0x134);
|
||||
|
||||
for (i = 0; i < CPU_PROCESS_CORNERS; i++)
|
||||
if (cpu_speedo_val < cpu_process_speedos[threshold][i])
|
||||
break;
|
||||
sku_info->cpu_process_id = i;
|
||||
|
||||
for (i = 0; i < CORE_PROCESS_CORNERS; i++)
|
||||
if (core_speedo_val < core_process_speedos[threshold][i])
|
||||
for (i = 0; i < SOC_PROCESS_CORNERS; i++)
|
||||
if (soc_speedo_val < soc_process_speedos[threshold][i])
|
||||
break;
|
||||
sku_info->core_process_id = i;
|
||||
sku_info->soc_process_id = i;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@
|
|||
|
||||
#define CPU_PROCESS_CORNERS 2
|
||||
#define GPU_PROCESS_CORNERS 2
|
||||
#define CORE_PROCESS_CORNERS 2
|
||||
#define SOC_PROCESS_CORNERS 2
|
||||
|
||||
#define FUSE_CPU_SPEEDO_0 0x14
|
||||
#define FUSE_CPU_SPEEDO_1 0x2c
|
||||
|
|
@ -53,7 +53,7 @@ static const u32 __initconst gpu_process_speedos[][GPU_PROCESS_CORNERS] = {
|
|||
{0, UINT_MAX},
|
||||
};
|
||||
|
||||
static const u32 __initconst core_process_speedos[][CORE_PROCESS_CORNERS] = {
|
||||
static const u32 __initconst soc_process_speedos[][SOC_PROCESS_CORNERS] = {
|
||||
{2101, UINT_MAX},
|
||||
{0, UINT_MAX},
|
||||
};
|
||||
|
|
@ -119,19 +119,19 @@ void __init tegra124_init_speedo_data(struct tegra_sku_info *sku_info)
|
|||
THRESHOLD_INDEX_COUNT);
|
||||
BUILD_BUG_ON(ARRAY_SIZE(gpu_process_speedos) !=
|
||||
THRESHOLD_INDEX_COUNT);
|
||||
BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) !=
|
||||
BUILD_BUG_ON(ARRAY_SIZE(soc_process_speedos) !=
|
||||
THRESHOLD_INDEX_COUNT);
|
||||
|
||||
cpu_speedo_0_value = tegra30_fuse_readl(FUSE_CPU_SPEEDO_0);
|
||||
cpu_speedo_0_value = tegra_fuse_read_early(FUSE_CPU_SPEEDO_0);
|
||||
|
||||
/* GPU Speedo is stored in CPU_SPEEDO_2 */
|
||||
sku_info->gpu_speedo_value = tegra30_fuse_readl(FUSE_CPU_SPEEDO_2);
|
||||
sku_info->gpu_speedo_value = tegra_fuse_read_early(FUSE_CPU_SPEEDO_2);
|
||||
|
||||
soc_speedo_0_value = tegra30_fuse_readl(FUSE_SOC_SPEEDO_0);
|
||||
soc_speedo_0_value = tegra_fuse_read_early(FUSE_SOC_SPEEDO_0);
|
||||
|
||||
cpu_iddq_value = tegra30_fuse_readl(FUSE_CPU_IDDQ);
|
||||
soc_iddq_value = tegra30_fuse_readl(FUSE_SOC_IDDQ);
|
||||
gpu_iddq_value = tegra30_fuse_readl(FUSE_GPU_IDDQ);
|
||||
cpu_iddq_value = tegra_fuse_read_early(FUSE_CPU_IDDQ);
|
||||
soc_iddq_value = tegra_fuse_read_early(FUSE_SOC_IDDQ);
|
||||
gpu_iddq_value = tegra_fuse_read_early(FUSE_GPU_IDDQ);
|
||||
|
||||
sku_info->cpu_speedo_value = cpu_speedo_0_value;
|
||||
|
||||
|
|
@ -143,7 +143,7 @@ void __init tegra124_init_speedo_data(struct tegra_sku_info *sku_info)
|
|||
|
||||
rev_sku_to_speedo_ids(sku_info, &threshold);
|
||||
|
||||
sku_info->cpu_iddq_value = tegra30_fuse_readl(FUSE_CPU_IDDQ);
|
||||
sku_info->cpu_iddq_value = tegra_fuse_read_early(FUSE_CPU_IDDQ);
|
||||
|
||||
for (i = 0; i < GPU_PROCESS_CORNERS; i++)
|
||||
if (sku_info->gpu_speedo_value <
|
||||
|
|
@ -157,11 +157,11 @@ void __init tegra124_init_speedo_data(struct tegra_sku_info *sku_info)
|
|||
break;
|
||||
sku_info->cpu_process_id = i;
|
||||
|
||||
for (i = 0; i < CORE_PROCESS_CORNERS; i++)
|
||||
for (i = 0; i < SOC_PROCESS_CORNERS; i++)
|
||||
if (soc_speedo_0_value <
|
||||
core_process_speedos[threshold][i])
|
||||
soc_process_speedos[threshold][i])
|
||||
break;
|
||||
sku_info->core_process_id = i;
|
||||
sku_info->soc_process_id = i;
|
||||
|
||||
pr_debug("Tegra GPU Speedo ID=%d, Speedo Value=%d\n",
|
||||
sku_info->gpu_speedo_id, sku_info->gpu_speedo_value);
|
||||
|
|
|
|||
|
|
@ -28,11 +28,11 @@
|
|||
#define CPU_SPEEDO_REDUND_MSBIT 39
|
||||
#define CPU_SPEEDO_REDUND_OFFS (CPU_SPEEDO_REDUND_MSBIT - CPU_SPEEDO_MSBIT)
|
||||
|
||||
#define CORE_SPEEDO_LSBIT 40
|
||||
#define CORE_SPEEDO_MSBIT 47
|
||||
#define CORE_SPEEDO_REDUND_LSBIT 48
|
||||
#define CORE_SPEEDO_REDUND_MSBIT 55
|
||||
#define CORE_SPEEDO_REDUND_OFFS (CORE_SPEEDO_REDUND_MSBIT - CORE_SPEEDO_MSBIT)
|
||||
#define SOC_SPEEDO_LSBIT 40
|
||||
#define SOC_SPEEDO_MSBIT 47
|
||||
#define SOC_SPEEDO_REDUND_LSBIT 48
|
||||
#define SOC_SPEEDO_REDUND_MSBIT 55
|
||||
#define SOC_SPEEDO_REDUND_OFFS (SOC_SPEEDO_REDUND_MSBIT - SOC_SPEEDO_MSBIT)
|
||||
|
||||
#define SPEEDO_MULT 4
|
||||
|
||||
|
|
@ -56,7 +56,7 @@ static const u32 __initconst cpu_process_speedos[][PROCESS_CORNERS_NUM] = {
|
|||
{316, 331, 383, UINT_MAX},
|
||||
};
|
||||
|
||||
static const u32 __initconst core_process_speedos[][PROCESS_CORNERS_NUM] = {
|
||||
static const u32 __initconst soc_process_speedos[][PROCESS_CORNERS_NUM] = {
|
||||
{165, 195, 224, UINT_MAX},
|
||||
{165, 195, 224, UINT_MAX},
|
||||
{165, 195, 224, UINT_MAX},
|
||||
|
|
@ -69,7 +69,7 @@ void __init tegra20_init_speedo_data(struct tegra_sku_info *sku_info)
|
|||
int i;
|
||||
|
||||
BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) != SPEEDO_ID_COUNT);
|
||||
BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) != SPEEDO_ID_COUNT);
|
||||
BUILD_BUG_ON(ARRAY_SIZE(soc_process_speedos) != SPEEDO_ID_COUNT);
|
||||
|
||||
if (SPEEDO_ID_SELECT_0(sku_info->revision))
|
||||
sku_info->soc_speedo_id = SPEEDO_ID_0;
|
||||
|
|
@ -80,8 +80,8 @@ void __init tegra20_init_speedo_data(struct tegra_sku_info *sku_info)
|
|||
|
||||
val = 0;
|
||||
for (i = CPU_SPEEDO_MSBIT; i >= CPU_SPEEDO_LSBIT; i--) {
|
||||
reg = tegra20_spare_fuse_early(i) |
|
||||
tegra20_spare_fuse_early(i + CPU_SPEEDO_REDUND_OFFS);
|
||||
reg = tegra_fuse_read_spare(i) |
|
||||
tegra_fuse_read_spare(i + CPU_SPEEDO_REDUND_OFFS);
|
||||
val = (val << 1) | (reg & 0x1);
|
||||
}
|
||||
val = val * SPEEDO_MULT;
|
||||
|
|
@ -94,17 +94,17 @@ void __init tegra20_init_speedo_data(struct tegra_sku_info *sku_info)
|
|||
sku_info->cpu_process_id = i;
|
||||
|
||||
val = 0;
|
||||
for (i = CORE_SPEEDO_MSBIT; i >= CORE_SPEEDO_LSBIT; i--) {
|
||||
reg = tegra20_spare_fuse_early(i) |
|
||||
tegra20_spare_fuse_early(i + CORE_SPEEDO_REDUND_OFFS);
|
||||
for (i = SOC_SPEEDO_MSBIT; i >= SOC_SPEEDO_LSBIT; i--) {
|
||||
reg = tegra_fuse_read_spare(i) |
|
||||
tegra_fuse_read_spare(i + SOC_SPEEDO_REDUND_OFFS);
|
||||
val = (val << 1) | (reg & 0x1);
|
||||
}
|
||||
val = val * SPEEDO_MULT;
|
||||
pr_debug("Core speedo value %u\n", val);
|
||||
|
||||
for (i = 0; i < (PROCESS_CORNERS_NUM - 1); i++) {
|
||||
if (val <= core_process_speedos[sku_info->soc_speedo_id][i])
|
||||
if (val <= soc_process_speedos[sku_info->soc_speedo_id][i])
|
||||
break;
|
||||
}
|
||||
sku_info->core_process_id = i;
|
||||
sku_info->soc_process_id = i;
|
||||
}
|
||||
|
|
|
|||
184
drivers/soc/tegra/fuse/speedo-tegra210.c
Normal file
184
drivers/soc/tegra/fuse/speedo-tegra210.c
Normal file
|
|
@ -0,0 +1,184 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2015, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/bug.h>
|
||||
|
||||
#include <soc/tegra/fuse.h>
|
||||
|
||||
#include "fuse.h"
|
||||
|
||||
#define CPU_PROCESS_CORNERS 2
|
||||
#define GPU_PROCESS_CORNERS 2
|
||||
#define SOC_PROCESS_CORNERS 3
|
||||
|
||||
#define FUSE_CPU_SPEEDO_0 0x014
|
||||
#define FUSE_CPU_SPEEDO_1 0x02c
|
||||
#define FUSE_CPU_SPEEDO_2 0x030
|
||||
#define FUSE_SOC_SPEEDO_0 0x034
|
||||
#define FUSE_SOC_SPEEDO_1 0x038
|
||||
#define FUSE_SOC_SPEEDO_2 0x03c
|
||||
#define FUSE_CPU_IDDQ 0x018
|
||||
#define FUSE_SOC_IDDQ 0x040
|
||||
#define FUSE_GPU_IDDQ 0x128
|
||||
#define FUSE_FT_REV 0x028
|
||||
|
||||
enum {
|
||||
THRESHOLD_INDEX_0,
|
||||
THRESHOLD_INDEX_1,
|
||||
THRESHOLD_INDEX_COUNT,
|
||||
};
|
||||
|
||||
static const u32 __initconst cpu_process_speedos[][CPU_PROCESS_CORNERS] = {
|
||||
{ 2119, UINT_MAX },
|
||||
{ 2119, UINT_MAX },
|
||||
};
|
||||
|
||||
static const u32 __initconst gpu_process_speedos[][GPU_PROCESS_CORNERS] = {
|
||||
{ UINT_MAX, UINT_MAX },
|
||||
{ UINT_MAX, UINT_MAX },
|
||||
};
|
||||
|
||||
static const u32 __initconst soc_process_speedos[][SOC_PROCESS_CORNERS] = {
|
||||
{ 1950, 2100, UINT_MAX },
|
||||
{ 1950, 2100, UINT_MAX },
|
||||
};
|
||||
|
||||
static u8 __init get_speedo_revision(void)
|
||||
{
|
||||
return tegra_fuse_read_spare(4) << 2 |
|
||||
tegra_fuse_read_spare(3) << 1 |
|
||||
tegra_fuse_read_spare(2) << 0;
|
||||
}
|
||||
|
||||
static void __init rev_sku_to_speedo_ids(struct tegra_sku_info *sku_info,
|
||||
u8 speedo_rev, int *threshold)
|
||||
{
|
||||
int sku = sku_info->sku_id;
|
||||
|
||||
/* Assign to default */
|
||||
sku_info->cpu_speedo_id = 0;
|
||||
sku_info->soc_speedo_id = 0;
|
||||
sku_info->gpu_speedo_id = 0;
|
||||
*threshold = THRESHOLD_INDEX_0;
|
||||
|
||||
switch (sku) {
|
||||
case 0x00: /* Engineering SKU */
|
||||
case 0x01: /* Engineering SKU */
|
||||
case 0x07:
|
||||
case 0x17:
|
||||
case 0x27:
|
||||
if (speedo_rev >= 2)
|
||||
sku_info->gpu_speedo_id = 1;
|
||||
break;
|
||||
|
||||
case 0x13:
|
||||
if (speedo_rev >= 2)
|
||||
sku_info->gpu_speedo_id = 1;
|
||||
|
||||
sku_info->cpu_speedo_id = 1;
|
||||
break;
|
||||
|
||||
default:
|
||||
pr_err("Tegra210: unknown SKU %#04x\n", sku);
|
||||
/* Using the default for the error case */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static int get_process_id(int value, const u32 *speedos, unsigned int num)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < num; i++)
|
||||
if (value < speedos[num])
|
||||
return i;
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
void __init tegra210_init_speedo_data(struct tegra_sku_info *sku_info)
|
||||
{
|
||||
int cpu_speedo[3], soc_speedo[3], cpu_iddq, gpu_iddq, soc_iddq;
|
||||
unsigned int index;
|
||||
u8 speedo_revision;
|
||||
|
||||
BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
|
||||
THRESHOLD_INDEX_COUNT);
|
||||
BUILD_BUG_ON(ARRAY_SIZE(gpu_process_speedos) !=
|
||||
THRESHOLD_INDEX_COUNT);
|
||||
BUILD_BUG_ON(ARRAY_SIZE(soc_process_speedos) !=
|
||||
THRESHOLD_INDEX_COUNT);
|
||||
|
||||
/* Read speedo/IDDQ fuses */
|
||||
cpu_speedo[0] = tegra_fuse_read_early(FUSE_CPU_SPEEDO_0);
|
||||
cpu_speedo[1] = tegra_fuse_read_early(FUSE_CPU_SPEEDO_1);
|
||||
cpu_speedo[2] = tegra_fuse_read_early(FUSE_CPU_SPEEDO_2);
|
||||
|
||||
soc_speedo[0] = tegra_fuse_read_early(FUSE_SOC_SPEEDO_0);
|
||||
soc_speedo[1] = tegra_fuse_read_early(FUSE_SOC_SPEEDO_1);
|
||||
soc_speedo[2] = tegra_fuse_read_early(FUSE_CPU_SPEEDO_2);
|
||||
|
||||
cpu_iddq = tegra_fuse_read_early(FUSE_CPU_IDDQ) * 4;
|
||||
soc_iddq = tegra_fuse_read_early(FUSE_SOC_IDDQ) * 4;
|
||||
gpu_iddq = tegra_fuse_read_early(FUSE_GPU_IDDQ) * 5;
|
||||
|
||||
/*
|
||||
* Determine CPU, GPU and SoC speedo values depending on speedo fusing
|
||||
* revision. Note that GPU speedo value is fused in CPU_SPEEDO_2.
|
||||
*/
|
||||
speedo_revision = get_speedo_revision();
|
||||
pr_info("Speedo Revision %u\n", speedo_revision);
|
||||
|
||||
if (speedo_revision >= 3) {
|
||||
sku_info->cpu_speedo_value = cpu_speedo[0];
|
||||
sku_info->gpu_speedo_value = cpu_speedo[2];
|
||||
sku_info->soc_speedo_value = soc_speedo[0];
|
||||
} else if (speedo_revision == 2) {
|
||||
sku_info->cpu_speedo_value = (-1938 + (1095 * cpu_speedo[0] / 100)) / 10;
|
||||
sku_info->gpu_speedo_value = (-1662 + (1082 * cpu_speedo[2] / 100)) / 10;
|
||||
sku_info->soc_speedo_value = ( -705 + (1037 * soc_speedo[0] / 100)) / 10;
|
||||
} else {
|
||||
sku_info->cpu_speedo_value = 2100;
|
||||
sku_info->gpu_speedo_value = cpu_speedo[2] - 75;
|
||||
sku_info->soc_speedo_value = 1900;
|
||||
}
|
||||
|
||||
if ((sku_info->cpu_speedo_value <= 0) ||
|
||||
(sku_info->gpu_speedo_value <= 0) ||
|
||||
(sku_info->soc_speedo_value <= 0)) {
|
||||
WARN(1, "speedo value not fused\n");
|
||||
return;
|
||||
}
|
||||
|
||||
rev_sku_to_speedo_ids(sku_info, speedo_revision, &index);
|
||||
|
||||
sku_info->gpu_process_id = get_process_id(sku_info->gpu_speedo_value,
|
||||
gpu_process_speedos[index],
|
||||
GPU_PROCESS_CORNERS);
|
||||
|
||||
sku_info->cpu_process_id = get_process_id(sku_info->cpu_speedo_value,
|
||||
cpu_process_speedos[index],
|
||||
CPU_PROCESS_CORNERS);
|
||||
|
||||
sku_info->soc_process_id = get_process_id(sku_info->soc_speedo_value,
|
||||
soc_process_speedos[index],
|
||||
SOC_PROCESS_CORNERS);
|
||||
|
||||
pr_debug("Tegra GPU Speedo ID=%d, Speedo Value=%d\n",
|
||||
sku_info->gpu_speedo_id, sku_info->gpu_speedo_value);
|
||||
}
|
||||
|
|
@ -22,7 +22,7 @@
|
|||
|
||||
#include "fuse.h"
|
||||
|
||||
#define CORE_PROCESS_CORNERS 1
|
||||
#define SOC_PROCESS_CORNERS 1
|
||||
#define CPU_PROCESS_CORNERS 6
|
||||
|
||||
#define FUSE_SPEEDO_CALIB_0 0x14
|
||||
|
|
@ -54,7 +54,7 @@ enum {
|
|||
THRESHOLD_INDEX_COUNT,
|
||||
};
|
||||
|
||||
static const u32 __initconst core_process_speedos[][CORE_PROCESS_CORNERS] = {
|
||||
static const u32 __initconst soc_process_speedos[][SOC_PROCESS_CORNERS] = {
|
||||
{180},
|
||||
{170},
|
||||
{195},
|
||||
|
|
@ -93,25 +93,25 @@ static void __init fuse_speedo_calib(u32 *speedo_g, u32 *speedo_lp)
|
|||
int bit_minus1;
|
||||
int bit_minus2;
|
||||
|
||||
reg = tegra30_fuse_readl(FUSE_SPEEDO_CALIB_0);
|
||||
reg = tegra_fuse_read_early(FUSE_SPEEDO_CALIB_0);
|
||||
|
||||
*speedo_lp = (reg & 0xFFFF) * 4;
|
||||
*speedo_g = ((reg >> 16) & 0xFFFF) * 4;
|
||||
|
||||
ate_ver = tegra30_fuse_readl(FUSE_TEST_PROG_VER);
|
||||
ate_ver = tegra_fuse_read_early(FUSE_TEST_PROG_VER);
|
||||
pr_debug("Tegra ATE prog ver %d.%d\n", ate_ver/10, ate_ver%10);
|
||||
|
||||
if (ate_ver >= 26) {
|
||||
bit_minus1 = tegra30_spare_fuse(LP_SPEEDO_BIT_MINUS1);
|
||||
bit_minus1 |= tegra30_spare_fuse(LP_SPEEDO_BIT_MINUS1_R);
|
||||
bit_minus2 = tegra30_spare_fuse(LP_SPEEDO_BIT_MINUS2);
|
||||
bit_minus2 |= tegra30_spare_fuse(LP_SPEEDO_BIT_MINUS2_R);
|
||||
bit_minus1 = tegra_fuse_read_spare(LP_SPEEDO_BIT_MINUS1);
|
||||
bit_minus1 |= tegra_fuse_read_spare(LP_SPEEDO_BIT_MINUS1_R);
|
||||
bit_minus2 = tegra_fuse_read_spare(LP_SPEEDO_BIT_MINUS2);
|
||||
bit_minus2 |= tegra_fuse_read_spare(LP_SPEEDO_BIT_MINUS2_R);
|
||||
*speedo_lp |= (bit_minus1 << 1) | bit_minus2;
|
||||
|
||||
bit_minus1 = tegra30_spare_fuse(G_SPEEDO_BIT_MINUS1);
|
||||
bit_minus1 |= tegra30_spare_fuse(G_SPEEDO_BIT_MINUS1_R);
|
||||
bit_minus2 = tegra30_spare_fuse(G_SPEEDO_BIT_MINUS2);
|
||||
bit_minus2 |= tegra30_spare_fuse(G_SPEEDO_BIT_MINUS2_R);
|
||||
bit_minus1 = tegra_fuse_read_spare(G_SPEEDO_BIT_MINUS1);
|
||||
bit_minus1 |= tegra_fuse_read_spare(G_SPEEDO_BIT_MINUS1_R);
|
||||
bit_minus2 = tegra_fuse_read_spare(G_SPEEDO_BIT_MINUS2);
|
||||
bit_minus2 |= tegra_fuse_read_spare(G_SPEEDO_BIT_MINUS2_R);
|
||||
*speedo_g |= (bit_minus1 << 1) | bit_minus2;
|
||||
} else {
|
||||
*speedo_lp |= 0x3;
|
||||
|
|
@ -121,7 +121,7 @@ static void __init fuse_speedo_calib(u32 *speedo_g, u32 *speedo_lp)
|
|||
|
||||
static void __init rev_sku_to_speedo_ids(struct tegra_sku_info *sku_info)
|
||||
{
|
||||
int package_id = tegra30_fuse_readl(FUSE_PACKAGE_INFO) & 0x0F;
|
||||
int package_id = tegra_fuse_read_early(FUSE_PACKAGE_INFO) & 0x0F;
|
||||
|
||||
switch (sku_info->revision) {
|
||||
case TEGRA_REVISION_A01:
|
||||
|
|
@ -246,19 +246,19 @@ static void __init rev_sku_to_speedo_ids(struct tegra_sku_info *sku_info)
|
|||
void __init tegra30_init_speedo_data(struct tegra_sku_info *sku_info)
|
||||
{
|
||||
u32 cpu_speedo_val;
|
||||
u32 core_speedo_val;
|
||||
u32 soc_speedo_val;
|
||||
int i;
|
||||
|
||||
BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
|
||||
THRESHOLD_INDEX_COUNT);
|
||||
BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) !=
|
||||
BUILD_BUG_ON(ARRAY_SIZE(soc_process_speedos) !=
|
||||
THRESHOLD_INDEX_COUNT);
|
||||
|
||||
|
||||
rev_sku_to_speedo_ids(sku_info);
|
||||
fuse_speedo_calib(&cpu_speedo_val, &core_speedo_val);
|
||||
fuse_speedo_calib(&cpu_speedo_val, &soc_speedo_val);
|
||||
pr_debug("Tegra CPU speedo value %u\n", cpu_speedo_val);
|
||||
pr_debug("Tegra Core speedo value %u\n", core_speedo_val);
|
||||
pr_debug("Tegra Core speedo value %u\n", soc_speedo_val);
|
||||
|
||||
for (i = 0; i < CPU_PROCESS_CORNERS; i++) {
|
||||
if (cpu_speedo_val < cpu_process_speedos[threshold_index][i])
|
||||
|
|
@ -273,16 +273,16 @@ void __init tegra30_init_speedo_data(struct tegra_sku_info *sku_info)
|
|||
sku_info->cpu_speedo_id = 1;
|
||||
}
|
||||
|
||||
for (i = 0; i < CORE_PROCESS_CORNERS; i++) {
|
||||
if (core_speedo_val < core_process_speedos[threshold_index][i])
|
||||
for (i = 0; i < SOC_PROCESS_CORNERS; i++) {
|
||||
if (soc_speedo_val < soc_process_speedos[threshold_index][i])
|
||||
break;
|
||||
}
|
||||
sku_info->core_process_id = i - 1;
|
||||
sku_info->soc_process_id = i - 1;
|
||||
|
||||
if (sku_info->core_process_id == -1) {
|
||||
pr_warn("Tegra CORE speedo value %3d out of range",
|
||||
core_speedo_val);
|
||||
sku_info->core_process_id = 0;
|
||||
if (sku_info->soc_process_id == -1) {
|
||||
pr_warn("Tegra SoC speedo value %3d out of range",
|
||||
soc_speedo_val);
|
||||
sku_info->soc_process_id = 0;
|
||||
sku_info->soc_speedo_id = 1;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -21,11 +21,10 @@
|
|||
#include <linux/io.h>
|
||||
|
||||
#include <soc/tegra/fuse.h>
|
||||
#include <soc/tegra/common.h>
|
||||
|
||||
#include "fuse.h"
|
||||
|
||||
#define APBMISC_BASE 0x70000800
|
||||
#define APBMISC_SIZE 0x64
|
||||
#define FUSE_SKU_INFO 0x10
|
||||
|
||||
#define PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT 4
|
||||
|
|
@ -95,8 +94,8 @@ void __init tegra_init_revision(void)
|
|||
rev = TEGRA_REVISION_A02;
|
||||
break;
|
||||
case 3:
|
||||
if (chip_id == TEGRA20 && (tegra20_spare_fuse_early(18) ||
|
||||
tegra20_spare_fuse_early(19)))
|
||||
if (chip_id == TEGRA20 && (tegra_fuse_read_spare(18) ||
|
||||
tegra_fuse_read_spare(19)))
|
||||
rev = TEGRA_REVISION_A03p;
|
||||
else
|
||||
rev = TEGRA_REVISION_A03;
|
||||
|
|
@ -110,27 +109,74 @@ void __init tegra_init_revision(void)
|
|||
|
||||
tegra_sku_info.revision = rev;
|
||||
|
||||
if (chip_id == TEGRA20)
|
||||
tegra_sku_info.sku_id = tegra20_fuse_early(FUSE_SKU_INFO);
|
||||
else
|
||||
tegra_sku_info.sku_id = tegra30_fuse_readl(FUSE_SKU_INFO);
|
||||
tegra_sku_info.sku_id = tegra_fuse_read_early(FUSE_SKU_INFO);
|
||||
}
|
||||
|
||||
void __init tegra_init_apbmisc(void)
|
||||
{
|
||||
struct resource apbmisc, straps;
|
||||
struct device_node *np;
|
||||
|
||||
np = of_find_matching_node(NULL, apbmisc_match);
|
||||
apbmisc_base = of_iomap(np, 0);
|
||||
if (!apbmisc_base) {
|
||||
pr_warn("ioremap tegra apbmisc failed. using %08x instead\n",
|
||||
APBMISC_BASE);
|
||||
apbmisc_base = ioremap(APBMISC_BASE, APBMISC_SIZE);
|
||||
if (!np) {
|
||||
/*
|
||||
* Fall back to legacy initialization for 32-bit ARM only. All
|
||||
* 64-bit ARM device tree files for Tegra are required to have
|
||||
* an APBMISC node.
|
||||
*
|
||||
* This is for backwards-compatibility with old device trees
|
||||
* that didn't contain an APBMISC node.
|
||||
*/
|
||||
if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
|
||||
/* APBMISC registers (chip revision, ...) */
|
||||
apbmisc.start = 0x70000800;
|
||||
apbmisc.end = 0x70000863;
|
||||
apbmisc.flags = IORESOURCE_MEM;
|
||||
|
||||
/* strapping options */
|
||||
if (tegra_get_chip_id() == TEGRA124) {
|
||||
straps.start = 0x7000e864;
|
||||
straps.end = 0x7000e867;
|
||||
} else {
|
||||
straps.start = 0x70000008;
|
||||
straps.end = 0x7000000b;
|
||||
}
|
||||
|
||||
straps.flags = IORESOURCE_MEM;
|
||||
|
||||
pr_warn("Using APBMISC region %pR\n", &apbmisc);
|
||||
pr_warn("Using strapping options registers %pR\n",
|
||||
&straps);
|
||||
} else {
|
||||
/*
|
||||
* At this point we're not running on Tegra, so play
|
||||
* nice with multi-platform kernels.
|
||||
*/
|
||||
return;
|
||||
}
|
||||
} else {
|
||||
/*
|
||||
* Extract information from the device tree if we've found a
|
||||
* matching node.
|
||||
*/
|
||||
if (of_address_to_resource(np, 0, &apbmisc) < 0) {
|
||||
pr_err("failed to get APBMISC registers\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if (of_address_to_resource(np, 1, &straps) < 0) {
|
||||
pr_err("failed to get strapping options registers\n");
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
strapping_base = of_iomap(np, 1);
|
||||
apbmisc_base = ioremap_nocache(apbmisc.start, resource_size(&apbmisc));
|
||||
if (!apbmisc_base)
|
||||
pr_err("failed to map APBMISC registers\n");
|
||||
|
||||
strapping_base = ioremap_nocache(straps.start, resource_size(&straps));
|
||||
if (!strapping_base)
|
||||
pr_err("ioremap tegra strapping_base failed\n");
|
||||
pr_err("failed to map strapping options registers\n");
|
||||
|
||||
long_ram_code = of_property_read_bool(np, "nvidia,long-ram-code");
|
||||
}
|
||||
|
|
|
|||
|
|
@ -17,6 +17,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#define pr_fmt(fmt) "tegra-pmc: " fmt
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk/tegra.h>
|
||||
|
|
@ -457,7 +459,6 @@ static int tegra_io_rail_prepare(int id, unsigned long *request,
|
|||
unsigned long *status, unsigned int *bit)
|
||||
{
|
||||
unsigned long rate, value;
|
||||
struct clk *clk;
|
||||
|
||||
*bit = id % 32;
|
||||
|
||||
|
|
@ -476,12 +477,7 @@ static int tegra_io_rail_prepare(int id, unsigned long *request,
|
|||
*request = IO_DPD2_REQ;
|
||||
}
|
||||
|
||||
clk = clk_get_sys(NULL, "pclk");
|
||||
if (IS_ERR(clk))
|
||||
return PTR_ERR(clk);
|
||||
|
||||
rate = clk_get_rate(clk);
|
||||
clk_put(clk);
|
||||
rate = clk_get_rate(pmc->clk);
|
||||
|
||||
tegra_pmc_writel(DPD_SAMPLE_ENABLE, DPD_SAMPLE);
|
||||
|
||||
|
|
@ -535,8 +531,10 @@ int tegra_io_rail_power_on(int id)
|
|||
tegra_pmc_writel(value, request);
|
||||
|
||||
err = tegra_io_rail_poll(status, mask, 0, 250);
|
||||
if (err < 0)
|
||||
if (err < 0) {
|
||||
pr_info("tegra_io_rail_poll() failed: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
tegra_io_rail_unprepare();
|
||||
|
||||
|
|
@ -551,8 +549,10 @@ int tegra_io_rail_power_off(int id)
|
|||
int err;
|
||||
|
||||
err = tegra_io_rail_prepare(id, &request, &status, &bit);
|
||||
if (err < 0)
|
||||
if (err < 0) {
|
||||
pr_info("tegra_io_rail_prepare() failed: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
mask = 1 << bit;
|
||||
|
||||
|
|
@ -736,12 +736,12 @@ void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc)
|
|||
u32 value, checksum;
|
||||
|
||||
if (!pmc->soc->has_tsense_reset)
|
||||
goto out;
|
||||
return;
|
||||
|
||||
np = of_find_node_by_name(pmc->dev->of_node, "i2c-thermtrip");
|
||||
if (!np) {
|
||||
dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled);
|
||||
goto out;
|
||||
return;
|
||||
}
|
||||
|
||||
if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) {
|
||||
|
|
@ -801,7 +801,6 @@ void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc)
|
|||
|
||||
out:
|
||||
of_node_put(np);
|
||||
return;
|
||||
}
|
||||
|
||||
static int tegra_pmc_probe(struct platform_device *pdev)
|
||||
|
|
@ -1002,7 +1001,56 @@ static const struct tegra_pmc_soc tegra124_pmc_soc = {
|
|||
.has_gpu_clamps = true,
|
||||
};
|
||||
|
||||
static const char * const tegra210_powergates[] = {
|
||||
[TEGRA_POWERGATE_CPU] = "crail",
|
||||
[TEGRA_POWERGATE_3D] = "3d",
|
||||
[TEGRA_POWERGATE_VENC] = "venc",
|
||||
[TEGRA_POWERGATE_PCIE] = "pcie",
|
||||
[TEGRA_POWERGATE_L2] = "l2",
|
||||
[TEGRA_POWERGATE_MPE] = "mpe",
|
||||
[TEGRA_POWERGATE_HEG] = "heg",
|
||||
[TEGRA_POWERGATE_SATA] = "sata",
|
||||
[TEGRA_POWERGATE_CPU1] = "cpu1",
|
||||
[TEGRA_POWERGATE_CPU2] = "cpu2",
|
||||
[TEGRA_POWERGATE_CPU3] = "cpu3",
|
||||
[TEGRA_POWERGATE_CELP] = "celp",
|
||||
[TEGRA_POWERGATE_CPU0] = "cpu0",
|
||||
[TEGRA_POWERGATE_C0NC] = "c0nc",
|
||||
[TEGRA_POWERGATE_C1NC] = "c1nc",
|
||||
[TEGRA_POWERGATE_SOR] = "sor",
|
||||
[TEGRA_POWERGATE_DIS] = "dis",
|
||||
[TEGRA_POWERGATE_DISB] = "disb",
|
||||
[TEGRA_POWERGATE_XUSBA] = "xusba",
|
||||
[TEGRA_POWERGATE_XUSBB] = "xusbb",
|
||||
[TEGRA_POWERGATE_XUSBC] = "xusbc",
|
||||
[TEGRA_POWERGATE_VIC] = "vic",
|
||||
[TEGRA_POWERGATE_IRAM] = "iram",
|
||||
[TEGRA_POWERGATE_NVDEC] = "nvdec",
|
||||
[TEGRA_POWERGATE_NVJPG] = "nvjpg",
|
||||
[TEGRA_POWERGATE_AUD] = "aud",
|
||||
[TEGRA_POWERGATE_DFD] = "dfd",
|
||||
[TEGRA_POWERGATE_VE2] = "ve2",
|
||||
};
|
||||
|
||||
static const u8 tegra210_cpu_powergates[] = {
|
||||
TEGRA_POWERGATE_CPU0,
|
||||
TEGRA_POWERGATE_CPU1,
|
||||
TEGRA_POWERGATE_CPU2,
|
||||
TEGRA_POWERGATE_CPU3,
|
||||
};
|
||||
|
||||
static const struct tegra_pmc_soc tegra210_pmc_soc = {
|
||||
.num_powergates = ARRAY_SIZE(tegra210_powergates),
|
||||
.powergates = tegra210_powergates,
|
||||
.num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates),
|
||||
.cpu_powergates = tegra210_cpu_powergates,
|
||||
.has_tsense_reset = true,
|
||||
.has_gpu_clamps = true,
|
||||
};
|
||||
|
||||
static const struct of_device_id tegra_pmc_match[] = {
|
||||
{ .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
|
||||
{ .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
|
||||
{ .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
|
||||
{ .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
|
||||
{ .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
|
||||
|
|
@ -1035,25 +1083,44 @@ static int __init tegra_pmc_early_init(void)
|
|||
bool invert;
|
||||
u32 value;
|
||||
|
||||
if (!soc_is_tegra())
|
||||
return 0;
|
||||
|
||||
np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match);
|
||||
if (!np) {
|
||||
pr_warn("PMC device node not found, disabling powergating\n");
|
||||
/*
|
||||
* Fall back to legacy initialization for 32-bit ARM only. All
|
||||
* 64-bit ARM device tree files for Tegra are required to have
|
||||
* a PMC node.
|
||||
*
|
||||
* This is for backwards-compatibility with old device trees
|
||||
* that didn't contain a PMC node. Note that in this case the
|
||||
* SoC data can't be matched and therefore powergating is
|
||||
* disabled.
|
||||
*/
|
||||
if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
|
||||
pr_warn("DT node not found, powergating disabled\n");
|
||||
|
||||
regs.start = 0x7000e400;
|
||||
regs.end = 0x7000e7ff;
|
||||
regs.flags = IORESOURCE_MEM;
|
||||
regs.start = 0x7000e400;
|
||||
regs.end = 0x7000e7ff;
|
||||
regs.flags = IORESOURCE_MEM;
|
||||
|
||||
pr_warn("Using memory region %pR\n", ®s);
|
||||
pr_warn("Using memory region %pR\n", ®s);
|
||||
} else {
|
||||
/*
|
||||
* At this point we're not running on Tegra, so play
|
||||
* nice with multi-platform kernels.
|
||||
*/
|
||||
return 0;
|
||||
}
|
||||
} else {
|
||||
pmc->soc = match->data;
|
||||
}
|
||||
/*
|
||||
* Extract information from the device tree if we've found a
|
||||
* matching node.
|
||||
*/
|
||||
if (of_address_to_resource(np, 0, ®s) < 0) {
|
||||
pr_err("failed to get PMC registers\n");
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
if (of_address_to_resource(np, 0, ®s) < 0) {
|
||||
pr_err("failed to get PMC registers\n");
|
||||
return -ENXIO;
|
||||
pmc->soc = match->data;
|
||||
}
|
||||
|
||||
pmc->base = ioremap_nocache(regs.start, resource_size(®s));
|
||||
|
|
@ -1064,6 +1131,10 @@ static int __init tegra_pmc_early_init(void)
|
|||
|
||||
mutex_init(&pmc->powergates_lock);
|
||||
|
||||
/*
|
||||
* Invert the interrupt polarity if a PMC device tree node exists and
|
||||
* contains the nvidia,invert-interrupt property.
|
||||
*/
|
||||
invert = of_property_read_bool(np, "nvidia,invert-interrupt");
|
||||
|
||||
value = tegra_pmc_readl(PMC_CNTRL);
|
||||
|
|
|
|||
Loading…
Reference in a new issue