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pci-v4.16-changes

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Merge tag 'pci-v4.16-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

Pull PCI updates from Bjorn Helgaas:

 - skip AER driver error recovery callbacks for correctable errors
   reported via ACPI APEI, as we already do for errors reported via the
   native path (Tyler Baicar)

 - fix DPC shared interrupt handling (Alex Williamson)

 - print full DPC interrupt number (Keith Busch)

 - enable DPC only if AER is available (Keith Busch)

 - simplify DPC code (Bjorn Helgaas)

 - calculate ASPM L1 substate parameter instead of hardcoding it (Bjorn
   Helgaas)

 - enable Latency Tolerance Reporting for ASPM L1 substates (Bjorn
   Helgaas)

 - move ASPM internal interfaces out of public header (Bjorn Helgaas)

 - allow hot-removal of VGA devices (Mika Westerberg)

 - speed up unplug and shutdown by assuming Thunderbolt controllers
   don't support Command Completed events (Lukas Wunner)

 - add AtomicOps support for GPU and Infiniband drivers (Felix Kuehling,
   Jay Cornwall)

 - expose "ari_enabled" in sysfs to help NIC naming (Stuart Hayes)

 - clean up PCI DMA interface usage (Christoph Hellwig)

 - remove PCI pool API (replaced with DMA pool) (Romain Perier)

 - deprecate pci_get_bus_and_slot(), which assumed PCI domain 0 (Sinan
   Kaya)

 - move DT PCI code from drivers/of/ to drivers/pci/ (Rob Herring)

 - add PCI-specific wrappers for dev_info(), etc (Frederick Lawler)

 - remove warnings on sysfs mmap failure (Bjorn Helgaas)

 - quiet ROM validation messages (Alex Deucher)

 - remove redundant memory alloc failure messages (Markus Elfring)

 - fill in types for compile-time VGA and other I/O port resources
   (Bjorn Helgaas)

 - make "pci=pcie_scan_all" work for Root Ports as well as Downstream
   Ports to help AmigaOne X1000 (Bjorn Helgaas)

 - add SPDX tags to all PCI files (Bjorn Helgaas)

 - quirk Marvell 9128 DMA aliases (Alex Williamson)

 - quirk broken INTx disable on Ceton InfiniTV4 (Bjorn Helgaas)

 - fix CONFIG_PCI=n build by adding dummy pci_irqd_intx_xlate() (Niklas
   Cassel)

 - use DMA API to get MSI address for DesignWare IP (Niklas Cassel)

 - fix endpoint-mode DMA mask configuration (Kishon Vijay Abraham I)

 - fix ARTPEC-6 incorrect IS_ERR() usage (Wei Yongjun)

 - add support for ARTPEC-7 SoC (Niklas Cassel)

 - add endpoint-mode support for ARTPEC (Niklas Cassel)

 - add Cadence PCIe host and endpoint controller driver (Cyrille
   Pitchen)

 - handle multiple INTx status bits being set in dra7xx (Vignesh R)

 - translate dra7xx hwirq range to fix INTD handling (Vignesh R)

 - remove deprecated Exynos PHY initialization code (Jaehoon Chung)

 - fix MSI erratum workaround for HiSilicon Hip06/Hip07 (Dongdong Liu)

 - fix NULL pointer dereference in iProc BCMA driver (Ray Jui)

 - fix Keystone interrupt-controller-node lookup (Johan Hovold)

 - constify qcom driver structures (Julia Lawall)

 - rework Tegra config space mapping to increase space available for
   endpoints (Vidya Sagar)

 - simplify Tegra driver by using bus->sysdata (Manikanta Maddireddy)

 - remove PCI_REASSIGN_ALL_BUS usage on Tegra (Manikanta Maddireddy)

 - add support for Global Fabric Manager Server (GFMS) event to
   Microsemi Switchtec switch driver (Logan Gunthorpe)

 - add IDs for Switchtec PSX 24xG3 and PSX 48xG3 (Kelvin Cao)

* tag 'pci-v4.16-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (140 commits)
  PCI: cadence: Add EndPoint Controller driver for Cadence PCIe controller
  dt-bindings: PCI: cadence: Add DT bindings for Cadence PCIe endpoint controller
  PCI: endpoint: Fix EPF device name to support multi-function devices
  PCI: endpoint: Add the function number as argument to EPC ops
  PCI: cadence: Add host driver for Cadence PCIe controller
  dt-bindings: PCI: cadence: Add DT bindings for Cadence PCIe host controller
  PCI: Add vendor ID for Cadence
  PCI: Add generic function to probe PCI host controllers
  PCI: generic: fix missing call of pci_free_resource_list()
  PCI: OF: Add generic function to parse and allocate PCI resources
  PCI: Regroup all PCI related entries into drivers/pci/Makefile
  PCI/DPC: Reformat DPC register definitions
  PCI/DPC: Add and use DPC Status register field definitions
  PCI/DPC: Squash dpc_rp_pio_get_info() into dpc_process_rp_pio_error()
  PCI/DPC: Remove unnecessary RP PIO register structs
  PCI/DPC: Push dpc->rp_pio_status assignment into dpc_rp_pio_get_info()
  PCI/DPC: Squash dpc_rp_pio_print_error() into dpc_rp_pio_get_info()
  PCI/DPC: Make RP PIO log size check more generic
  PCI/DPC: Rename local "status" to "dpc_status"
  PCI/DPC: Squash dpc_rp_pio_print_tlp_header() into dpc_rp_pio_print_error()
  ...
This commit is contained in:
Linus Torvalds 2018-02-06 09:59:40 -08:00
commit 105cf3c8c6
248 changed files with 4503 additions and 3756 deletions
Download patch file Download diff file Expand all files Collapse all files

34
drivers/video/console/vgacon.c
View file

@ -422,7 +422,10 @@ static const char *vgacon_startup(void)
vga_video_port_val = VGA_CRT_DM;
if ((screen_info.orig_video_ega_bx & 0xff) != 0x10) {
static struct resource ega_console_resource =
{ .name = "ega", .start = 0x3B0, .end = 0x3BF };
{ .name = "ega",
.flags = IORESOURCE_IO,
.start = 0x3B0,
.end = 0x3BF };
vga_video_type = VIDEO_TYPE_EGAM;
vga_vram_size = 0x8000;
display_desc = "EGA+";
@ -430,9 +433,15 @@ static const char *vgacon_startup(void)
&ega_console_resource);
} else {
static struct resource mda1_console_resource =
{ .name = "mda", .start = 0x3B0, .end = 0x3BB };
{ .name = "mda",
.flags = IORESOURCE_IO,
.start = 0x3B0,
.end = 0x3BB };
static struct resource mda2_console_resource =
{ .name = "mda", .start = 0x3BF, .end = 0x3BF };
{ .name = "mda",
.flags = IORESOURCE_IO,
.start = 0x3BF,
.end = 0x3BF };
vga_video_type = VIDEO_TYPE_MDA;
vga_vram_size = 0x2000;
display_desc = "*MDA";
@ -454,15 +463,21 @@ static const char *vgacon_startup(void)
vga_vram_size = 0x8000;
if (!screen_info.orig_video_isVGA) {
static struct resource ega_console_resource
= { .name = "ega", .start = 0x3C0, .end = 0x3DF };
static struct resource ega_console_resource =
{ .name = "ega",
.flags = IORESOURCE_IO,
.start = 0x3C0,
.end = 0x3DF };
vga_video_type = VIDEO_TYPE_EGAC;
display_desc = "EGA";
request_resource(&ioport_resource,
&ega_console_resource);
} else {
static struct resource vga_console_resource
= { .name = "vga+", .start = 0x3C0, .end = 0x3DF };
static struct resource vga_console_resource =
{ .name = "vga+",
.flags = IORESOURCE_IO,
.start = 0x3C0,
.end = 0x3DF };
vga_video_type = VIDEO_TYPE_VGAC;
display_desc = "VGA+";
request_resource(&ioport_resource,
@ -494,7 +509,10 @@ static const char *vgacon_startup(void)
}
} else {
static struct resource cga_console_resource =
{ .name = "cga", .start = 0x3D4, .end = 0x3D5 };
{ .name = "cga",
.flags = IORESOURCE_IO,
.start = 0x3D4,
.end = 0x3D5 };
vga_video_type = VIDEO_TYPE_CGA;
vga_vram_size = 0x2000;
display_desc = "*CGA";

4
drivers/video/fbdev/intelfb/intelfbhw.c
View file

@ -181,7 +181,9 @@ int intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
return 1;
/* Find the bridge device. It is always 0:0.0 */
if (!(bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)))) {
bridge_dev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus), 0,
PCI_DEVFN(0, 0));
if (!bridge_dev) {
ERR_MSG("cannot find bridge device\n");
return 1;
}

11
drivers/video/fbdev/nvidia/nv_hw.c
View file

@ -683,10 +683,11 @@ static void nForceUpdateArbitrationSettings(unsigned VClk,
nv10_sim_state sim_data;
unsigned int M, N, P, pll, MClk, NVClk, memctrl;
struct pci_dev *dev;
int domain = pci_domain_nr(par->pci_dev->bus);
if ((par->Chipset & 0x0FF0) == 0x01A0) {
unsigned int uMClkPostDiv;
dev = pci_get_bus_and_slot(0, 3);
dev = pci_get_domain_bus_and_slot(domain, 0, 3);
pci_read_config_dword(dev, 0x6C, &uMClkPostDiv);
uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf;
@ -694,7 +695,7 @@ static void nForceUpdateArbitrationSettings(unsigned VClk,
uMClkPostDiv = 4;
MClk = 400000 / uMClkPostDiv;
} else {
dev = pci_get_bus_and_slot(0, 5);
dev = pci_get_domain_bus_and_slot(domain, 0, 5);
pci_read_config_dword(dev, 0x4c, &MClk);
MClk /= 1000;
}
@ -707,13 +708,13 @@ static void nForceUpdateArbitrationSettings(unsigned VClk,
sim_data.pix_bpp = (char)pixelDepth;
sim_data.enable_video = 0;
sim_data.enable_mp = 0;
dev = pci_get_bus_and_slot(0, 1);
dev = pci_get_domain_bus_and_slot(domain, 0, 1);
pci_read_config_dword(dev, 0x7C, &sim_data.memory_type);
pci_dev_put(dev);
sim_data.memory_type = (sim_data.memory_type >> 12) & 1;
sim_data.memory_width = 64;
dev = pci_get_bus_and_slot(0, 3);
dev = pci_get_domain_bus_and_slot(domain, 0, 3);
pci_read_config_dword(dev, 0, &memctrl);
pci_dev_put(dev);
memctrl >>= 16;
@ -721,7 +722,7 @@ static void nForceUpdateArbitrationSettings(unsigned VClk,
if ((memctrl == 0x1A9) || (memctrl == 0x1AB) || (memctrl == 0x1ED)) {
u32 dimm[3];
dev = pci_get_bus_and_slot(0, 2);
dev = pci_get_domain_bus_and_slot(domain, 0, 2);
pci_read_config_dword(dev, 0x40, &dimm[0]);
dimm[0] = (dimm[0] >> 8) & 0x4f;
pci_read_config_dword(dev, 0x44, &dimm[1]);

3
drivers/video/fbdev/nvidia/nv_setup.c
View file

@ -264,7 +264,8 @@ static void nv10GetConfig(struct nvidia_par *par)
}
#endif
dev = pci_get_bus_and_slot(0, 1);
dev = pci_get_domain_bus_and_slot(pci_domain_nr(par->pci_dev->bus),
0, 1);
if ((par->Chipset & 0xffff) == 0x01a0) {
u32 amt;

2
drivers/video/fbdev/riva/fbdev.c
View file

@ -780,7 +780,7 @@ static int riva_load_video_mode(struct fb_info *info)
else
newmode.misc_output |= 0x80;
rc = CalcStateExt(&par->riva, &newmode.ext, bpp, width,
rc = CalcStateExt(&par->riva, &newmode.ext, par->pdev, bpp, width,
hDisplaySize, height, dotClock);
if (rc)
goto out;

7
drivers/video/fbdev/riva/nv_driver.c
View file

@ -159,6 +159,7 @@ unsigned long riva_get_memlen(struct riva_par *par)
unsigned int chipset = par->Chipset;
struct pci_dev* dev;
u32 amt;
int domain = pci_domain_nr(par->pdev->bus);
switch (chip->Architecture) {
case NV_ARCH_03:
@ -226,12 +227,12 @@ unsigned long riva_get_memlen(struct riva_par *par)
case NV_ARCH_30:
if(chipset == NV_CHIP_IGEFORCE2) {
dev = pci_get_bus_and_slot(0, 1);
dev = pci_get_domain_bus_and_slot(domain, 0, 1);
pci_read_config_dword(dev, 0x7C, &amt);
pci_dev_put(dev);
memlen = (((amt >> 6) & 31) + 1) * 1024;
} else if (chipset == NV_CHIP_0x01F0) {
dev = pci_get_bus_and_slot(0, 1);
dev = pci_get_domain_bus_and_slot(domain, 0, 1);
pci_read_config_dword(dev, 0x84, &amt);
pci_dev_put(dev);
memlen = (((amt >> 4) & 127) + 1) * 1024;
@ -417,6 +418,6 @@ riva_common_setup(struct riva_par *par)
}
par->riva.flatPanel = (par->FlatPanel > 0) ? TRUE : FALSE;
RivaGetConfig(&par->riva, par->Chipset);
RivaGetConfig(&par->riva, par->pdev, par->Chipset);
}

20
drivers/video/fbdev/riva/riva_hw.c
View file

@ -1108,7 +1108,8 @@ static void nForceUpdateArbitrationSettings
unsigned pixelDepth,
unsigned *burst,
unsigned *lwm,
RIVA_HW_INST *chip
RIVA_HW_INST *chip,
struct pci_dev *pdev
)
{
nv10_fifo_info fifo_data;
@ -1116,8 +1117,9 @@ static void nForceUpdateArbitrationSettings
unsigned int M, N, P, pll, MClk, NVClk;
unsigned int uMClkPostDiv;
struct pci_dev *dev;
int domain = pci_domain_nr(pdev->bus);
dev = pci_get_bus_and_slot(0, 3);
dev = pci_get_domain_bus_and_slot(domain, 0, 3);
pci_read_config_dword(dev, 0x6C, &uMClkPostDiv);
pci_dev_put(dev);
uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf;
@ -1132,7 +1134,7 @@ static void nForceUpdateArbitrationSettings
sim_data.enable_video = 0;
sim_data.enable_mp = 0;
dev = pci_get_bus_and_slot(0, 1);
dev = pci_get_domain_bus_and_slot(domain, 0, 1);
pci_read_config_dword(dev, 0x7C, &sim_data.memory_type);
pci_dev_put(dev);
sim_data.memory_type = (sim_data.memory_type >> 12) & 1;
@ -1234,6 +1236,7 @@ int CalcStateExt
(
RIVA_HW_INST *chip,
RIVA_HW_STATE *state,
struct pci_dev *pdev,
int bpp,
int width,
int hDisplaySize,
@ -1300,7 +1303,7 @@ int CalcStateExt
pixelDepth * 8,
&(state->arbitration0),
&(state->arbitration1),
chip);
chip, pdev);
} else {
nv10UpdateArbitrationSettings(VClk,
pixelDepth * 8,
@ -2102,10 +2105,12 @@ static void nv4GetConfig
static void nv10GetConfig
(
RIVA_HW_INST *chip,
struct pci_dev *pdev,
unsigned int chipset
)
{
struct pci_dev* dev;
int domain = pci_domain_nr(pdev->bus);
u32 amt;
#ifdef __BIG_ENDIAN
@ -2118,12 +2123,12 @@ static void nv10GetConfig
* Fill in chip configuration.
*/
if(chipset == NV_CHIP_IGEFORCE2) {
dev = pci_get_bus_and_slot(0, 1);
dev = pci_get_domain_bus_and_slot(domain, 0, 1);
pci_read_config_dword(dev, 0x7C, &amt);
pci_dev_put(dev);
chip->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024;
} else if(chipset == NV_CHIP_0x01F0) {
dev = pci_get_bus_and_slot(0, 1);
dev = pci_get_domain_bus_and_slot(domain, 0, 1);
pci_read_config_dword(dev, 0x84, &amt);
pci_dev_put(dev);
chip->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024;
@ -2224,6 +2229,7 @@ static void nv10GetConfig
int RivaGetConfig
(
RIVA_HW_INST *chip,
struct pci_dev *pdev,
unsigned int chipset
)
{
@ -2245,7 +2251,7 @@ int RivaGetConfig
case NV_ARCH_10:
case NV_ARCH_20:
case NV_ARCH_30:
nv10GetConfig(chip, chipset);
nv10GetConfig(chip, pdev, chipset);
break;
default:
return (-1);

3
drivers/video/fbdev/riva/riva_hw.h
View file

@ -536,6 +536,7 @@ extern int CalcStateExt
(
RIVA_HW_INST *chip,
RIVA_HW_STATE *state,
struct pci_dev *pdev,
int bpp,
int width,
int hDisplaySize,
@ -546,7 +547,7 @@ extern int CalcStateExt
/*
* External routines.
*/
int RivaGetConfig(RIVA_HW_INST *, unsigned int);
int RivaGetConfig(RIVA_HW_INST *chip, struct pci_dev *pdev, unsigned int c);
/*
* FIFO Free Count. Should attempt to yield processor if RIVA is busy.
*/