From b607012878fe3b8ccbdde09ca04c235303df0364 Mon Sep 17 00:00:00 2001 From: Mike Tipton Date: Fri, 25 Sep 2020 12:03:32 -0700 Subject: [PATCH] ARM: dts: msm: Remove interconnect phandles from clock nodes Clock optionally votes for interconnect in runtime_resume and runtime_suspend to ensure access to its configuration registers. However, interconnect also votes for clocks when configuring QoS. This can lead to deadlocks between the clock and interconnect frameworks. Voting for interconnects isn't strictly necessary for register access currently, since the required bus (CNOC) is always on when HLOS is running. Voting may become necessary in the future, but until then remove the interconnect phandles to prevent the deadlocks. Change-Id: If4392361a394b7ace52cb95a0ac2184bf64a7882 --- qcom/lahaina.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index bc26eca67236..7d3ebada79b5 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -2347,7 +2347,6 @@ reg-name = "cc_base"; vdd_mm-supply = <&VDD_MM_LEVEL>; vdd_mx-supply = <&VDD_MXA_LEVEL>; - interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_VENUS_CFG>; clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; clock-names = "iface"; #clock-cells = <1>; @@ -2360,7 +2359,6 @@ reg-names = "cc_base"; vdd_mm-supply = <&VDD_MM_LEVEL>; vdd_mx-supply = <&VDD_MXA_LEVEL>; - interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_CAMERA_CFG>; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; clock-names = "iface"; #clock-cells = <1>; @@ -2372,7 +2370,6 @@ reg = <0xaf00000 0x20000>; reg-name = "cc_base"; vdd_mm-supply = <&VDD_MM_LEVEL>; - interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>; clocks = <&clock_gcc GCC_DISP_AHB_CLK>; clock-names = "iface"; #clock-cells = <1>;