mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 02:32:09 -04:00
ARM: SoC driver changes for 3.17
A handful of driver-related changes. We've had a bunch of them going in through
other branches as well, so it's only a part of what we really have this release.
Larger pieces are:
* Removal of a now unused PWM driver for atmel
- This includes AVR32 changes that have been appropriately acked.
* Performance counter support for the arm CCN interconnect
* OMAP mailbox driver cleanups and consolidation
* PCI and SATA PHY drivers for SPEAr 13xx platforms
* Redefinition (with backwards compatibility!) of PCI DT bindings for Tegra to
better model regulators/power.
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Merge tag 'drivers-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver changes from Olof Johansson:
"A handful of driver-related changes. We've had a bunch of them going
in through other branches as well, so it's only a part of what we
really have this release.
Larger pieces are:
- Removal of a now unused PWM driver for atmel
[ This includes AVR32 changes that have been appropriately acked ]
- Performance counter support for the arm CCN interconnect
- OMAP mailbox driver cleanups and consolidation
- PCI and SATA PHY drivers for SPEAr 13xx platforms
- Redefinition (with backwards compatibility!) of PCI DT bindings for
Tegra to better model regulators/power"
Note: this merge also fixes up the semantic conflict with the new
calling convention for devm_phy_create(), see commit f0ed817638 ("phy:
core: Let node ptr of PHY point to PHY and not of PHY provider") that
came in through Greg's USB tree.
Semantic merge patch by Stephen Rothwell <[email protected]> through
the next tree.
* tag 'drivers-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (38 commits)
bus: arm-ccn: Fix error handling at event allocation
mailbox/omap: add a parent structure for every IP instance
mailbox/omap: remove the private mailbox structure
mailbox/omap: consolidate OMAP mailbox driver
mailbox/omap: simplify the fifo assignment by using macros
mailbox/omap: remove omap_mbox_type_t from mailbox ops
mailbox/omap: remove OMAP1 mailbox driver
mailbox/omap: use devm_* interfaces
bus: ARM CCN: add PERF_EVENTS dependency
bus: ARM CCN PMU driver
PCI: spear: Remove spear13xx_pcie_remove()
PCI: spear: Fix Section mismatch compilation warning for probe()
ARM: tegra: Remove legacy PCIe power supply properties
PCI: tegra: Remove deprecated power supply properties
PCI: tegra: Implement accurate power supply scheme
ARM: SPEAr13xx: Update defconfigs
ARM: SPEAr13xx: Add pcie and miphy DT nodes
ARM: SPEAr13xx: Add bindings and dt node for misc block
ARM: SPEAr13xx: Fix static mapping table
phy: Add drivers for PCIe and SATA phy on SPEAr13xx
...
This commit is contained in:
Linus Torvalds
commit
10c8e05620
74 changed files with 3452 additions and 2023 deletions
|
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@ -46,4 +46,12 @@ config PCI_HOST_GENERIC
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Say Y here if you want to support a simple generic PCI host
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controller, such as the one emulated by kvmtool.
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config PCIE_SPEAR13XX
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tristate "STMicroelectronics SPEAr PCIe controller"
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depends on ARCH_SPEAR13XX
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select PCIEPORTBUS
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select PCIE_DW
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help
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Say Y here if you want PCIe support on SPEAr13XX SoCs.
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endmenu
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@ -6,3 +6,4 @@ obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
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obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
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obj-$(CONFIG_PCI_RCAR_GEN2_PCIE) += pcie-rcar.o
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obj-$(CONFIG_PCI_HOST_GENERIC) += pci-host-generic.o
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obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
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@ -234,7 +234,6 @@ struct tegra_pcie_soc_data {
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bool has_pex_clkreq_en;
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bool has_pex_bias_ctrl;
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bool has_intr_prsnt_sense;
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bool has_avdd_supply;
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bool has_cml_clk;
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};
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@ -273,9 +272,8 @@ struct tegra_pcie {
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unsigned int num_ports;
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u32 xbar_config;
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struct regulator *pex_clk_supply;
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struct regulator *vdd_supply;
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struct regulator *avdd_supply;
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struct regulator_bulk_data *supplies;
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unsigned int num_supplies;
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const struct tegra_pcie_soc_data *soc_data;
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};
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@ -895,7 +893,6 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
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static void tegra_pcie_power_off(struct tegra_pcie *pcie)
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{
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const struct tegra_pcie_soc_data *soc = pcie->soc_data;
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int err;
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/* TODO: disable and unprepare clocks? */
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@ -906,23 +903,9 @@ static void tegra_pcie_power_off(struct tegra_pcie *pcie)
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tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
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if (soc->has_avdd_supply) {
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err = regulator_disable(pcie->avdd_supply);
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if (err < 0)
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dev_warn(pcie->dev,
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"failed to disable AVDD regulator: %d\n",
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err);
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}
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err = regulator_disable(pcie->pex_clk_supply);
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err = regulator_bulk_disable(pcie->num_supplies, pcie->supplies);
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if (err < 0)
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dev_warn(pcie->dev, "failed to disable pex-clk regulator: %d\n",
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err);
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err = regulator_disable(pcie->vdd_supply);
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if (err < 0)
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dev_warn(pcie->dev, "failed to disable VDD regulator: %d\n",
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err);
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dev_warn(pcie->dev, "failed to disable regulators: %d\n", err);
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}
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static int tegra_pcie_power_on(struct tegra_pcie *pcie)
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@ -937,28 +920,9 @@ static int tegra_pcie_power_on(struct tegra_pcie *pcie)
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tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
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/* enable regulators */
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err = regulator_enable(pcie->vdd_supply);
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if (err < 0) {
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dev_err(pcie->dev, "failed to enable VDD regulator: %d\n", err);
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return err;
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}
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err = regulator_enable(pcie->pex_clk_supply);
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if (err < 0) {
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dev_err(pcie->dev, "failed to enable pex-clk regulator: %d\n",
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err);
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return err;
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}
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if (soc->has_avdd_supply) {
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err = regulator_enable(pcie->avdd_supply);
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if (err < 0) {
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dev_err(pcie->dev,
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"failed to enable AVDD regulator: %d\n",
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err);
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return err;
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}
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}
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err = regulator_bulk_enable(pcie->num_supplies, pcie->supplies);
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if (err < 0)
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dev_err(pcie->dev, "failed to enable regulators: %d\n", err);
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err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,
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pcie->pex_clk,
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@ -1395,14 +1359,157 @@ static int tegra_pcie_get_xbar_config(struct tegra_pcie *pcie, u32 lanes,
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return -EINVAL;
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}
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/*
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* Check whether a given set of supplies is available in a device tree node.
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* This is used to check whether the new or the legacy device tree bindings
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* should be used.
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*/
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static bool of_regulator_bulk_available(struct device_node *np,
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struct regulator_bulk_data *supplies,
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unsigned int num_supplies)
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{
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char property[32];
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unsigned int i;
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for (i = 0; i < num_supplies; i++) {
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snprintf(property, 32, "%s-supply", supplies[i].supply);
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if (of_find_property(np, property, NULL) == NULL)
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return false;
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}
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return true;
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}
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/*
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* Old versions of the device tree binding for this device used a set of power
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* supplies that didn't match the hardware inputs. This happened to work for a
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* number of cases but is not future proof. However to preserve backwards-
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* compatibility with old device trees, this function will try to use the old
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* set of supplies.
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*/
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static int tegra_pcie_get_legacy_regulators(struct tegra_pcie *pcie)
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{
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struct device_node *np = pcie->dev->of_node;
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if (of_device_is_compatible(np, "nvidia,tegra30-pcie"))
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pcie->num_supplies = 3;
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else if (of_device_is_compatible(np, "nvidia,tegra20-pcie"))
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pcie->num_supplies = 2;
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if (pcie->num_supplies == 0) {
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dev_err(pcie->dev, "device %s not supported in legacy mode\n",
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np->full_name);
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return -ENODEV;
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}
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pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies,
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sizeof(*pcie->supplies),
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GFP_KERNEL);
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if (!pcie->supplies)
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return -ENOMEM;
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pcie->supplies[0].supply = "pex-clk";
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pcie->supplies[1].supply = "vdd";
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if (pcie->num_supplies > 2)
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pcie->supplies[2].supply = "avdd";
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return devm_regulator_bulk_get(pcie->dev, pcie->num_supplies,
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pcie->supplies);
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}
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/*
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* Obtains the list of regulators required for a particular generation of the
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* IP block.
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*
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* This would've been nice to do simply by providing static tables for use
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* with the regulator_bulk_*() API, but unfortunately Tegra30 is a bit quirky
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* in that it has two pairs or AVDD_PEX and VDD_PEX supplies (PEXA and PEXB)
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* and either seems to be optional depending on which ports are being used.
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*/
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static int tegra_pcie_get_regulators(struct tegra_pcie *pcie, u32 lane_mask)
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{
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struct device_node *np = pcie->dev->of_node;
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unsigned int i = 0;
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if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) {
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bool need_pexa = false, need_pexb = false;
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/* VDD_PEXA and AVDD_PEXA supply lanes 0 to 3 */
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if (lane_mask & 0x0f)
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need_pexa = true;
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/* VDD_PEXB and AVDD_PEXB supply lanes 4 to 5 */
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if (lane_mask & 0x30)
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need_pexb = true;
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pcie->num_supplies = 4 + (need_pexa ? 2 : 0) +
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(need_pexb ? 2 : 0);
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pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies,
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sizeof(*pcie->supplies),
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GFP_KERNEL);
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if (!pcie->supplies)
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return -ENOMEM;
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pcie->supplies[i++].supply = "avdd-pex-pll";
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pcie->supplies[i++].supply = "hvdd-pex";
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pcie->supplies[i++].supply = "vddio-pex-ctl";
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pcie->supplies[i++].supply = "avdd-plle";
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if (need_pexa) {
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pcie->supplies[i++].supply = "avdd-pexa";
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pcie->supplies[i++].supply = "vdd-pexa";
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}
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if (need_pexb) {
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pcie->supplies[i++].supply = "avdd-pexb";
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pcie->supplies[i++].supply = "vdd-pexb";
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}
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} else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) {
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pcie->num_supplies = 5;
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pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies,
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sizeof(*pcie->supplies),
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GFP_KERNEL);
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if (!pcie->supplies)
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return -ENOMEM;
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pcie->supplies[0].supply = "avdd-pex";
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pcie->supplies[1].supply = "vdd-pex";
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pcie->supplies[2].supply = "avdd-pex-pll";
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pcie->supplies[3].supply = "avdd-plle";
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pcie->supplies[4].supply = "vddio-pex-clk";
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}
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if (of_regulator_bulk_available(pcie->dev->of_node, pcie->supplies,
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pcie->num_supplies))
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return devm_regulator_bulk_get(pcie->dev, pcie->num_supplies,
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pcie->supplies);
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/*
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* If not all regulators are available for this new scheme, assume
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* that the device tree complies with an older version of the device
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* tree binding.
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*/
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dev_info(pcie->dev, "using legacy DT binding for power supplies\n");
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devm_kfree(pcie->dev, pcie->supplies);
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pcie->num_supplies = 0;
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return tegra_pcie_get_legacy_regulators(pcie);
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}
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static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
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{
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const struct tegra_pcie_soc_data *soc = pcie->soc_data;
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struct device_node *np = pcie->dev->of_node, *port;
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struct of_pci_range_parser parser;
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struct of_pci_range range;
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u32 lanes = 0, mask = 0;
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unsigned int lane = 0;
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struct resource res;
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u32 lanes = 0;
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int err;
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if (of_pci_range_parser_init(&parser, np)) {
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@ -1410,20 +1517,6 @@ static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
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return -EINVAL;
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}
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pcie->vdd_supply = devm_regulator_get(pcie->dev, "vdd");
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if (IS_ERR(pcie->vdd_supply))
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return PTR_ERR(pcie->vdd_supply);
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pcie->pex_clk_supply = devm_regulator_get(pcie->dev, "pex-clk");
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if (IS_ERR(pcie->pex_clk_supply))
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return PTR_ERR(pcie->pex_clk_supply);
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||||
|
||||
if (soc->has_avdd_supply) {
|
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pcie->avdd_supply = devm_regulator_get(pcie->dev, "avdd");
|
||||
if (IS_ERR(pcie->avdd_supply))
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||||
return PTR_ERR(pcie->avdd_supply);
|
||||
}
|
||||
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||||
for_each_of_pci_range(&parser, &range) {
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||||
of_pci_range_to_resource(&range, np, &res);
|
||||
|
||||
|
|
@ -1491,8 +1584,13 @@ static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
|
|||
|
||||
lanes |= value << (index << 3);
|
||||
|
||||
if (!of_device_is_available(port))
|
||||
if (!of_device_is_available(port)) {
|
||||
lane += value;
|
||||
continue;
|
||||
}
|
||||
|
||||
mask |= ((1 << value) - 1) << lane;
|
||||
lane += value;
|
||||
|
||||
rp = devm_kzalloc(pcie->dev, sizeof(*rp), GFP_KERNEL);
|
||||
if (!rp)
|
||||
|
|
@ -1523,6 +1621,10 @@ static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
|
|||
return err;
|
||||
}
|
||||
|
||||
err = tegra_pcie_get_regulators(pcie, mask);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -1616,7 +1718,6 @@ static const struct tegra_pcie_soc_data tegra20_pcie_data = {
|
|||
.has_pex_clkreq_en = false,
|
||||
.has_pex_bias_ctrl = false,
|
||||
.has_intr_prsnt_sense = false,
|
||||
.has_avdd_supply = false,
|
||||
.has_cml_clk = false,
|
||||
};
|
||||
|
||||
|
|
@ -1628,7 +1729,6 @@ static const struct tegra_pcie_soc_data tegra30_pcie_data = {
|
|||
.has_pex_clkreq_en = true,
|
||||
.has_pex_bias_ctrl = true,
|
||||
.has_intr_prsnt_sense = true,
|
||||
.has_avdd_supply = true,
|
||||
.has_cml_clk = true,
|
||||
};
|
||||
|
||||
|
|
|
|||
393
drivers/pci/host/pcie-spear13xx.c
Normal file
393
drivers/pci/host/pcie-spear13xx.c
Normal file
|
|
@ -0,0 +1,393 @@
|
|||
/*
|
||||
* PCIe host controller driver for ST Microelectronics SPEAr13xx SoCs
|
||||
*
|
||||
* SPEAr13xx PCIe Glue Layer Source Code
|
||||
*
|
||||
* Copyright (C) 2010-2014 ST Microelectronics
|
||||
* Pratyush Anand <pratyush.anand@st.com>
|
||||
* Mohit Kumar <mohit.kumar@st.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/phy/phy.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/resource.h>
|
||||
|
||||
#include "pcie-designware.h"
|
||||
|
||||
struct spear13xx_pcie {
|
||||
void __iomem *app_base;
|
||||
struct phy *phy;
|
||||
struct clk *clk;
|
||||
struct pcie_port pp;
|
||||
bool is_gen1;
|
||||
};
|
||||
|
||||
struct pcie_app_reg {
|
||||
u32 app_ctrl_0; /* cr0 */
|
||||
u32 app_ctrl_1; /* cr1 */
|
||||
u32 app_status_0; /* cr2 */
|
||||
u32 app_status_1; /* cr3 */
|
||||
u32 msg_status; /* cr4 */
|
||||
u32 msg_payload; /* cr5 */
|
||||
u32 int_sts; /* cr6 */
|
||||
u32 int_clr; /* cr7 */
|
||||
u32 int_mask; /* cr8 */
|
||||
u32 mst_bmisc; /* cr9 */
|
||||
u32 phy_ctrl; /* cr10 */
|
||||
u32 phy_status; /* cr11 */
|
||||
u32 cxpl_debug_info_0; /* cr12 */
|
||||
u32 cxpl_debug_info_1; /* cr13 */
|
||||
u32 ven_msg_ctrl_0; /* cr14 */
|
||||
u32 ven_msg_ctrl_1; /* cr15 */
|
||||
u32 ven_msg_data_0; /* cr16 */
|
||||
u32 ven_msg_data_1; /* cr17 */
|
||||
u32 ven_msi_0; /* cr18 */
|
||||
u32 ven_msi_1; /* cr19 */
|
||||
u32 mst_rmisc; /* cr20 */
|
||||
};
|
||||
|
||||
/* CR0 ID */
|
||||
#define RX_LANE_FLIP_EN_ID 0
|
||||
#define TX_LANE_FLIP_EN_ID 1
|
||||
#define SYS_AUX_PWR_DET_ID 2
|
||||
#define APP_LTSSM_ENABLE_ID 3
|
||||
#define SYS_ATTEN_BUTTON_PRESSED_ID 4
|
||||
#define SYS_MRL_SENSOR_STATE_ID 5
|
||||
#define SYS_PWR_FAULT_DET_ID 6
|
||||
#define SYS_MRL_SENSOR_CHGED_ID 7
|
||||
#define SYS_PRE_DET_CHGED_ID 8
|
||||
#define SYS_CMD_CPLED_INT_ID 9
|
||||
#define APP_INIT_RST_0_ID 11
|
||||
#define APP_REQ_ENTR_L1_ID 12
|
||||
#define APP_READY_ENTR_L23_ID 13
|
||||
#define APP_REQ_EXIT_L1_ID 14
|
||||
#define DEVICE_TYPE_EP (0 << 25)
|
||||
#define DEVICE_TYPE_LEP (1 << 25)
|
||||
#define DEVICE_TYPE_RC (4 << 25)
|
||||
#define SYS_INT_ID 29
|
||||
#define MISCTRL_EN_ID 30
|
||||
#define REG_TRANSLATION_ENABLE 31
|
||||
|
||||
/* CR1 ID */
|
||||
#define APPS_PM_XMT_TURNOFF_ID 2
|
||||
#define APPS_PM_XMT_PME_ID 5
|
||||
|
||||
/* CR3 ID */
|
||||
#define XMLH_LTSSM_STATE_DETECT_QUIET 0x00
|
||||
#define XMLH_LTSSM_STATE_DETECT_ACT 0x01
|
||||
#define XMLH_LTSSM_STATE_POLL_ACTIVE 0x02
|
||||
#define XMLH_LTSSM_STATE_POLL_COMPLIANCE 0x03
|
||||
#define XMLH_LTSSM_STATE_POLL_CONFIG 0x04
|
||||
#define XMLH_LTSSM_STATE_PRE_DETECT_QUIET 0x05
|
||||
#define XMLH_LTSSM_STATE_DETECT_WAIT 0x06
|
||||
#define XMLH_LTSSM_STATE_CFG_LINKWD_START 0x07
|
||||
#define XMLH_LTSSM_STATE_CFG_LINKWD_ACEPT 0x08
|
||||
#define XMLH_LTSSM_STATE_CFG_LANENUM_WAIT 0x09
|
||||
#define XMLH_LTSSM_STATE_CFG_LANENUM_ACEPT 0x0A
|
||||
#define XMLH_LTSSM_STATE_CFG_COMPLETE 0x0B
|
||||
#define XMLH_LTSSM_STATE_CFG_IDLE 0x0C
|
||||
#define XMLH_LTSSM_STATE_RCVRY_LOCK 0x0D
|
||||
#define XMLH_LTSSM_STATE_RCVRY_SPEED 0x0E
|
||||
#define XMLH_LTSSM_STATE_RCVRY_RCVRCFG 0x0F
|
||||
#define XMLH_LTSSM_STATE_RCVRY_IDLE 0x10
|
||||
#define XMLH_LTSSM_STATE_L0 0x11
|
||||
#define XMLH_LTSSM_STATE_L0S 0x12
|
||||
#define XMLH_LTSSM_STATE_L123_SEND_EIDLE 0x13
|
||||
#define XMLH_LTSSM_STATE_L1_IDLE 0x14
|
||||
#define XMLH_LTSSM_STATE_L2_IDLE 0x15
|
||||
#define XMLH_LTSSM_STATE_L2_WAKE 0x16
|
||||
#define XMLH_LTSSM_STATE_DISABLED_ENTRY 0x17
|
||||
#define XMLH_LTSSM_STATE_DISABLED_IDLE 0x18
|
||||
#define XMLH_LTSSM_STATE_DISABLED 0x19
|
||||
#define XMLH_LTSSM_STATE_LPBK_ENTRY 0x1A
|
||||
#define XMLH_LTSSM_STATE_LPBK_ACTIVE 0x1B
|
||||
#define XMLH_LTSSM_STATE_LPBK_EXIT 0x1C
|
||||
#define XMLH_LTSSM_STATE_LPBK_EXIT_TIMEOUT 0x1D
|
||||
#define XMLH_LTSSM_STATE_HOT_RESET_ENTRY 0x1E
|
||||
#define XMLH_LTSSM_STATE_HOT_RESET 0x1F
|
||||
#define XMLH_LTSSM_STATE_MASK 0x3F
|
||||
#define XMLH_LINK_UP (1 << 6)
|
||||
|
||||
/* CR4 ID */
|
||||
#define CFG_MSI_EN_ID 18
|
||||
|
||||
/* CR6 */
|
||||
#define INTA_CTRL_INT (1 << 7)
|
||||
#define INTB_CTRL_INT (1 << 8)
|
||||
#define INTC_CTRL_INT (1 << 9)
|
||||
#define INTD_CTRL_INT (1 << 10)
|
||||
#define MSI_CTRL_INT (1 << 26)
|
||||
|
||||
/* CR19 ID */
|
||||
#define VEN_MSI_REQ_ID 11
|
||||
#define VEN_MSI_FUN_NUM_ID 8
|
||||
#define VEN_MSI_TC_ID 5
|
||||
#define VEN_MSI_VECTOR_ID 0
|
||||
#define VEN_MSI_REQ_EN ((u32)0x1 << VEN_MSI_REQ_ID)
|
||||
#define VEN_MSI_FUN_NUM_MASK ((u32)0x7 << VEN_MSI_FUN_NUM_ID)
|
||||
#define VEN_MSI_TC_MASK ((u32)0x7 << VEN_MSI_TC_ID)
|
||||
#define VEN_MSI_VECTOR_MASK ((u32)0x1F << VEN_MSI_VECTOR_ID)
|
||||
|
||||
#define EXP_CAP_ID_OFFSET 0x70
|
||||
|
||||
#define to_spear13xx_pcie(x) container_of(x, struct spear13xx_pcie, pp)
|
||||
|
||||
static int spear13xx_pcie_establish_link(struct pcie_port *pp)
|
||||
{
|
||||
u32 val;
|
||||
int count = 0;
|
||||
struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
|
||||
struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
|
||||
u32 exp_cap_off = EXP_CAP_ID_OFFSET;
|
||||
|
||||
if (dw_pcie_link_up(pp)) {
|
||||
dev_err(pp->dev, "link already up\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
dw_pcie_setup_rc(pp);
|
||||
|
||||
/*
|
||||
* this controller support only 128 bytes read size, however its
|
||||
* default value in capability register is 512 bytes. So force
|
||||
* it to 128 here.
|
||||
*/
|
||||
dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_DEVCTL, 4, &val);
|
||||
val &= ~PCI_EXP_DEVCTL_READRQ;
|
||||
dw_pcie_cfg_write(pp->dbi_base, exp_cap_off + PCI_EXP_DEVCTL, 4, val);
|
||||
|
||||
dw_pcie_cfg_write(pp->dbi_base, PCI_VENDOR_ID, 2, 0x104A);
|
||||
dw_pcie_cfg_write(pp->dbi_base, PCI_DEVICE_ID, 2, 0xCD80);
|
||||
|
||||
/*
|
||||
* if is_gen1 is set then handle it, so that some buggy card
|
||||
* also works
|
||||
*/
|
||||
if (spear13xx_pcie->is_gen1) {
|
||||
dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_LNKCAP, 4,
|
||||
&val);
|
||||
if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
|
||||
val &= ~((u32)PCI_EXP_LNKCAP_SLS);
|
||||
val |= PCI_EXP_LNKCAP_SLS_2_5GB;
|
||||
dw_pcie_cfg_write(pp->dbi_base, exp_cap_off +
|
||||
PCI_EXP_LNKCAP, 4, val);
|
||||
}
|
||||
|
||||
dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_LNKCTL2, 4,
|
||||
&val);
|
||||
if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
|
||||
val &= ~((u32)PCI_EXP_LNKCAP_SLS);
|
||||
val |= PCI_EXP_LNKCAP_SLS_2_5GB;
|
||||
dw_pcie_cfg_write(pp->dbi_base, exp_cap_off +
|
||||
PCI_EXP_LNKCTL2, 4, val);
|
||||
}
|
||||
}
|
||||
|
||||
/* enable ltssm */
|
||||
writel(DEVICE_TYPE_RC | (1 << MISCTRL_EN_ID)
|
||||
| (1 << APP_LTSSM_ENABLE_ID)
|
||||
| ((u32)1 << REG_TRANSLATION_ENABLE),
|
||||
&app_reg->app_ctrl_0);
|
||||
|
||||
/* check if the link is up or not */
|
||||
while (!dw_pcie_link_up(pp)) {
|
||||
mdelay(100);
|
||||
count++;
|
||||
if (count == 10) {
|
||||
dev_err(pp->dev, "link Fail\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
dev_info(pp->dev, "link up\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg)
|
||||
{
|
||||
struct pcie_port *pp = arg;
|
||||
struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
|
||||
struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
|
||||
unsigned int status;
|
||||
|
||||
status = readl(&app_reg->int_sts);
|
||||
|
||||
if (status & MSI_CTRL_INT) {
|
||||
if (!IS_ENABLED(CONFIG_PCI_MSI))
|
||||
BUG();
|
||||
dw_handle_msi_irq(pp);
|
||||
}
|
||||
|
||||
writel(status, &app_reg->int_clr);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static void spear13xx_pcie_enable_interrupts(struct pcie_port *pp)
|
||||
{
|
||||
struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
|
||||
struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
|
||||
|
||||
/* Enable MSI interrupt */
|
||||
if (IS_ENABLED(CONFIG_PCI_MSI)) {
|
||||
dw_pcie_msi_init(pp);
|
||||
writel(readl(&app_reg->int_mask) |
|
||||
MSI_CTRL_INT, &app_reg->int_mask);
|
||||
}
|
||||
}
|
||||
|
||||
static int spear13xx_pcie_link_up(struct pcie_port *pp)
|
||||
{
|
||||
struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
|
||||
struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
|
||||
|
||||
if (readl(&app_reg->app_status_1) & XMLH_LINK_UP)
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void spear13xx_pcie_host_init(struct pcie_port *pp)
|
||||
{
|
||||
spear13xx_pcie_establish_link(pp);
|
||||
spear13xx_pcie_enable_interrupts(pp);
|
||||
}
|
||||
|
||||
static struct pcie_host_ops spear13xx_pcie_host_ops = {
|
||||
.link_up = spear13xx_pcie_link_up,
|
||||
.host_init = spear13xx_pcie_host_init,
|
||||
};
|
||||
|
||||
static int add_pcie_port(struct pcie_port *pp, struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
int ret;
|
||||
|
||||
pp->irq = platform_get_irq(pdev, 0);
|
||||
if (!pp->irq) {
|
||||
dev_err(dev, "failed to get irq\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
ret = devm_request_irq(dev, pp->irq, spear13xx_pcie_irq_handler,
|
||||
IRQF_SHARED, "spear1340-pcie", pp);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to request irq %d\n", pp->irq);
|
||||
return ret;
|
||||
}
|
||||
|
||||
pp->root_bus_nr = -1;
|
||||
pp->ops = &spear13xx_pcie_host_ops;
|
||||
|
||||
ret = dw_pcie_host_init(pp);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to initialize host\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init spear13xx_pcie_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct spear13xx_pcie *spear13xx_pcie;
|
||||
struct pcie_port *pp;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct resource *dbi_base;
|
||||
int ret;
|
||||
|
||||
spear13xx_pcie = devm_kzalloc(dev, sizeof(*spear13xx_pcie), GFP_KERNEL);
|
||||
if (!spear13xx_pcie) {
|
||||
dev_err(dev, "no memory for SPEAr13xx pcie\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
spear13xx_pcie->phy = devm_phy_get(dev, "pcie-phy");
|
||||
if (IS_ERR(spear13xx_pcie->phy)) {
|
||||
ret = PTR_ERR(spear13xx_pcie->phy);
|
||||
if (ret == -EPROBE_DEFER)
|
||||
dev_info(dev, "probe deferred\n");
|
||||
else
|
||||
dev_err(dev, "couldn't get pcie-phy\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
phy_init(spear13xx_pcie->phy);
|
||||
|
||||
spear13xx_pcie->clk = devm_clk_get(dev, NULL);
|
||||
if (IS_ERR(spear13xx_pcie->clk)) {
|
||||
dev_err(dev, "couldn't get clk for pcie\n");
|
||||
return PTR_ERR(spear13xx_pcie->clk);
|
||||
}
|
||||
ret = clk_prepare_enable(spear13xx_pcie->clk);
|
||||
if (ret) {
|
||||
dev_err(dev, "couldn't enable clk for pcie\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
pp = &spear13xx_pcie->pp;
|
||||
|
||||
pp->dev = dev;
|
||||
|
||||
dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
pp->dbi_base = devm_ioremap_resource(dev, dbi_base);
|
||||
if (IS_ERR(pp->dbi_base)) {
|
||||
dev_err(dev, "couldn't remap dbi base %p\n", dbi_base);
|
||||
ret = PTR_ERR(pp->dbi_base);
|
||||
goto fail_clk;
|
||||
}
|
||||
spear13xx_pcie->app_base = pp->dbi_base + 0x2000;
|
||||
|
||||
if (of_property_read_bool(np, "st,pcie-is-gen1"))
|
||||
spear13xx_pcie->is_gen1 = true;
|
||||
|
||||
ret = add_pcie_port(pp, pdev);
|
||||
if (ret < 0)
|
||||
goto fail_clk;
|
||||
|
||||
platform_set_drvdata(pdev, spear13xx_pcie);
|
||||
return 0;
|
||||
|
||||
fail_clk:
|
||||
clk_disable_unprepare(spear13xx_pcie->clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct of_device_id spear13xx_pcie_of_match[] = {
|
||||
{ .compatible = "st,spear1340-pcie", },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, spear13xx_pcie_of_match);
|
||||
|
||||
static struct platform_driver spear13xx_pcie_driver __initdata = {
|
||||
.probe = spear13xx_pcie_probe,
|
||||
.driver = {
|
||||
.name = "spear-pcie",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = of_match_ptr(spear13xx_pcie_of_match),
|
||||
},
|
||||
};
|
||||
|
||||
/* SPEAr13xx PCIe driver does not allow module unload */
|
||||
|
||||
static int __init pcie_init(void)
|
||||
{
|
||||
return platform_driver_register(&spear13xx_pcie_driver);
|
||||
}
|
||||
module_init(pcie_init);
|
||||
|
||||
MODULE_DESCRIPTION("ST Microelectronics SPEAr13xx PCIe host controller driver");
|
||||
MODULE_AUTHOR("Pratyush Anand <[email protected]>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in a new issue