From 10cfeb84a4f8f299646ed433db00e9894610d10a Mon Sep 17 00:00:00 2001
From: Chaoli Zhou <zchaoli@codeaurora.org>
Date: Wed, 29 Jan 2020 17:55:48 +0800
Subject: [PATCH] qcacmn: Pass phy address PCIE_PCIE_SCRATCH_2 to IPA

Currently, the IPA GSI can't update the index to copy
engine 5 write index register since such kind of
register address is above 512k, so as a workaround,
we use PCIE_PCIE_SCRATCH_2 to replace copy engine 5
write index register for IPA update the index. And then
WLAN firmware will poll this register to check if this
index update or not, if updtae, WLAN firmware will be
as agent to update the index to real copy engine 5 write
index register, and then the data from IPA to WLAN will
work. Before the real fix is ready, we use this method
for workaround.

Change-Id: I383a7d52f5685b633f1bd44659b11f30231c8ca8
---
 hif/src/ce/ce_service.c | 45 ++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 44 insertions(+), 1 deletion(-)

diff --git a/hif/src/ce/ce_service.c b/hif/src/ce/ce_service.c
index 115342ac8d61..68d841a23d2e 100644
--- a/hif/src/ce/ce_service.c
+++ b/hif/src/ce/ce_service.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2019 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2013-2020 The Linux Foundation. All rights reserved.
  *
  * Permission to use, copy, modify, and/or distribute this software for
  * any purpose with or without fee is hereby granted, provided that the
@@ -1394,6 +1394,7 @@ bool ce_check_rx_pending(struct CE_state *CE_state)
 qdf_export_symbol(ce_check_rx_pending);
 
 #ifdef IPA_OFFLOAD
+#ifdef GENOA_IPA_WORKAROUND
 /**
  * ce_ipa_get_resource() - get uc resource on copyengine
  * @ce: copyengine context
@@ -1439,12 +1440,54 @@ void ce_ipa_get_resource(struct CE_handle *ce,
 	/* Get BAR address */
 	hif_read_phy_mem_base(CE_state->scn, &phy_mem_base);
 
+	*ce_sr = CE_state->scn->ipa_ce_ring;
+	*ce_sr_ring_size = (uint32_t)(CE_state->src_ring->nentries *
+		sizeof(struct CE_src_desc));
+	/* 0x0002005c is the offset address of PCIE_PCIE_SCRATCH_2 register */
+	*ce_reg_paddr = phy_mem_base + 0x2005C;
+
+}
+
+#else
+void ce_ipa_get_resource(struct CE_handle *ce,
+			 qdf_shared_mem_t **ce_sr,
+			 uint32_t *ce_sr_ring_size,
+			 qdf_dma_addr_t *ce_reg_paddr)
+{
+	struct CE_state *CE_state = (struct CE_state *)ce;
+	uint32_t ring_loop;
+	struct CE_src_desc *ce_desc;
+	qdf_dma_addr_t phy_mem_base;
+	struct hif_softc *scn = CE_state->scn;
+
+	if (CE_UNUSED == CE_state->state) {
+		*qdf_mem_get_dma_addr_ptr(scn->qdf_dev,
+			&CE_state->scn->ipa_ce_ring->mem_info) = 0;
+		*ce_sr_ring_size = 0;
+		return;
+	}
+
+	/* Update default value for descriptor */
+	for (ring_loop = 0; ring_loop < CE_state->src_ring->nentries;
+	     ring_loop++) {
+		ce_desc = (struct CE_src_desc *)
+			  ((char *)CE_state->src_ring->base_addr_owner_space +
+			   ring_loop * (sizeof(struct CE_src_desc)));
+		CE_IPA_RING_INIT(ce_desc);
+	}
+
+	/* Get BAR address */
+	hif_read_phy_mem_base(CE_state->scn, &phy_mem_base);
+
 	*ce_sr = CE_state->scn->ipa_ce_ring;
 	*ce_sr_ring_size = (uint32_t)(CE_state->src_ring->nentries *
 		sizeof(struct CE_src_desc));
 	*ce_reg_paddr = phy_mem_base + CE_BASE_ADDRESS(CE_state->id) +
 			SR_WR_INDEX_ADDRESS;
+
 }
+
+#endif
 #endif /* IPA_OFFLOAD */
 
 #ifdef HIF_CE_DEBUG_DATA_BUF