From 840bb02b81a3bc19d3e3c6454e74b4ca6e5a7194 Mon Sep 17 00:00:00 2001 From: Hongwei Ren Date: Fri, 16 Apr 2021 18:21:30 +0530 Subject: [PATCH 1/5] ARM: dts: msm: Add dt nodes for spi, i2c, uart for scuba add dtsi nodes for spi, i2c, uart for scuba. Change-Id: If8e200b7b2bc0630eb827685e559c53e9a5a9ebf --- qcom/qrb2210-rb1-qupv3.dtsi | 263 ++++++++++++++++++++++++++++++++++++ qcom/qrb2210-rb1.dtsi | 4 +- 2 files changed, 265 insertions(+), 2 deletions(-) create mode 100644 qcom/qrb2210-rb1-qupv3.dtsi diff --git a/qcom/qrb2210-rb1-qupv3.dtsi b/qcom/qrb2210-rb1-qupv3.dtsi new file mode 100644 index 000000000000..42d875459550 --- /dev/null +++ b/qcom/qrb2210-rb1-qupv3.dtsi @@ -0,0 +1,263 @@ +#include + +&soc { + /* QUPv3 SE Instances + * Qup0 0: SE 0 + * Qup0 1: SE 1 + * Qup0 2: SE 2 + * Qup0 3: SE 3 + * Qup0 4: SE 4 + * Qup0 5: SE 5 + */ + + /* QUPv3_0 wrapper instance */ + qupv3_0: qcom,qupv3_0_geni_se@4ac0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0x4ac0000 0x2000>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-bus-ids = + , + ; + qcom,vote-for-bw; + iommus = <&apps_smmu 0xe3 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + status = "ok"; + }; + + /* GPI Instance */ + gpi_dma0: qcom,gpi-dma@4a00000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0x4a00000 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0xf6 0x0>; + qcom,max-num-gpii = <10>; + interrupts = , + , + , + , + , + , + , + , + , + ; + qcom,gpii-mask = <0x1f>; + qcom,ev-factor = <2>; + qcom,iommu-dma-addr-pool = <0x100000 0x100000>; + qcom,gpi-ee-offset = <0x10000>; + status = "ok"; + }; + + /* Debug UART Instance */ + qupv3_se4_2uart: qcom,qup_uart@4a90000 { + compatible = "qcom,msm-geni-console"; + reg = <0x4a90000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_2uart_active>; + pinctrl-1 = <&qupv3_se4_2uart_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se0_i2c: i2c@4a80000 { + compatible = "qcom,i2c-geni"; + reg = <0x4a80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_i2c_active>; + pinctrl-1 = <&qupv3_se0_i2c_sleep>; + dmas = <&gpi_dma0 0 0 3 64 0>, + <&gpi_dma0 1 0 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se0_spi: spi@4a80000 { + compatible = "qcom,spi-geni"; + reg = <0x4a80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_spi_active>; + pinctrl-1 = <&qupv3_se0_spi_sleep>; + dmas = <&gpi_dma0 0 0 1 64 0>, + <&gpi_dma0 1 0 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se1_i2c: i2c@4a84000 { + compatible = "qcom,i2c-geni"; + reg = <0x4a84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_i2c_active>; + pinctrl-1 = <&qupv3_se1_i2c_sleep>; + dmas = <&gpi_dma0 0 1 3 64 0>, + <&gpi_dma0 1 1 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se1_spi: spi@4a84000 { + compatible = "qcom,spi-geni"; + reg = <0x4a84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_spi_active>; + pinctrl-1 = <&qupv3_se1_spi_sleep>; + dmas = <&gpi_dma0 0 1 1 64 0>, + <&gpi_dma0 1 1 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se2_i2c: i2c@4a88000 { + compatible = "qcom,i2c-geni"; + reg = <0x4a88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_i2c_active>; + pinctrl-1 = <&qupv3_se2_i2c_sleep>; + dmas = <&gpi_dma0 0 2 3 64 0>, + <&gpi_dma0 1 2 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se2_spi: spi@4a88000 { + compatible = "qcom,spi-geni"; + reg = <0x4a88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_spi_active>; + pinctrl-1 = <&qupv3_se2_spi_sleep>; + dmas = <&gpi_dma0 0 2 1 64 0>, + <&gpi_dma0 1 2 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + /* HS UART Instance */ + qupv3_se3_4uart: qcom,qup_uart@4a8c000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0x4a8c000 0x4000>; + reg-names = "se_phys"; + interrupts-extended = <&intc GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 11 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "active", "sleep", "shutdown"; + pinctrl-0 = <&qupv3_se3_default_ctsrtsrx>, + <&qupv3_se3_default_tx>; + pinctrl-1 = <&qupv3_se3_ctsrx>, <&qupv3_se3_rts>, + <&qupv3_se3_tx>; + pinctrl-2 = <&qupv3_se3_ctsrx>, <&qupv3_se3_rts>, + <&qupv3_se3_tx>; + pinctrl-3 = <&qupv3_se3_default_ctsrtsrx>, + <&qupv3_se3_default_tx>; + qcom,wakeup-byte = <0xFD>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se5_i2c: i2c@4a94000 { + compatible = "qcom,i2c-geni"; + reg = <0x4a94000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_i2c_active>; + pinctrl-1 = <&qupv3_se5_i2c_sleep>; + dmas = <&gpi_dma0 0 5 3 64 0>, + <&gpi_dma0 1 5 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se5_spi: spi@4a94000 { + compatible = "qcom,spi-geni"; + reg = <0x4a94000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_spi_active>; + pinctrl-1 = <&qupv3_se5_spi_sleep>; + dmas = <&gpi_dma0 0 5 1 64 0>, + <&gpi_dma0 1 5 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; +}; diff --git a/qcom/qrb2210-rb1.dtsi b/qcom/qrb2210-rb1.dtsi index 87850bf65bcb..9fb48b4af2dc 100644 --- a/qcom/qrb2210-rb1.dtsi +++ b/qcom/qrb2210-rb1.dtsi @@ -29,8 +29,8 @@ }; aliases { - swr0 = &swr0; - swr1 = &swr1; + serial0 = &qupv3_se4_2uart; + hsuart0 = &qupv3_se3_4uart; }; cpus { From 76e91b4aa6e5725c4b5b45218c4fbd42c7b80264 Mon Sep 17 00:00:00 2001 From: Hongwei Ren Date: Fri, 16 Apr 2021 18:28:04 +0530 Subject: [PATCH 2/5] ARM: dts: msm: Add eMMC, SD card support for SCUBA Add eMMC, SD card support for scuba-iot. Change-Id: If37e9e04aae54753484520f3b4dbbb0fa55b832d --- qcom/qrb2210-rb1-idp.dtsi | 36 ++++++ qcom/qrb2210-rb1-pinctrl.dtsi | 228 +++++++++++++++------------------- qcom/qrb2210-rb1.dtsi | 152 +++++++++++++++++++++++ 3 files changed, 285 insertions(+), 131 deletions(-) diff --git a/qcom/qrb2210-rb1-idp.dtsi b/qcom/qrb2210-rb1-idp.dtsi index 5f0cc45e0530..18399c7871d2 100644 --- a/qcom/qrb2210-rb1-idp.dtsi +++ b/qcom/qrb2210-rb1-idp.dtsi @@ -12,6 +12,42 @@ }; }; +&sdhc_1 { + vdd-supply = <&L20A>; + qcom,vdd-voltage-level = <2856000 2856000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L14A>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&L21A>; + qcom,vdd-voltage-level = <2960000 3300000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&L4A>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 22000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + cd-gpios = <&tlmm 88 GPIO_ACTIVE_LOW>; + + status = "ok"; +}; + &pm2250_qg { qcom,battery-data = <&scuba_batterydata>; qcom,qg-iterm-ma = <150>; diff --git a/qcom/qrb2210-rb1-pinctrl.dtsi b/qcom/qrb2210-rb1-pinctrl.dtsi index e292ad133313..901f47d21ad1 100644 --- a/qcom/qrb2210-rb1-pinctrl.dtsi +++ b/qcom/qrb2210-rb1-pinctrl.dtsi @@ -37,139 +37,105 @@ }; }; /* SDC pin type */ - sdc1_clk_on: sdc1_clk_on { - config { + sdc1_on: sdc1_on { + clk { pins = "sdc1_clk"; - bias-disable; /* NO pull */ - drive-strength = <16>; /* 16 MA */ - }; - }; - - sdc1_clk_off: sdc1_clk_off { - config { - pins = "sdc1_clk"; - bias-disable; /* NO pull */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - sdc1_cmd_on: sdc1_cmd_on { - config { - pins = "sdc1_cmd"; - bias-pull-up; /* pull up */ - drive-strength = <14>; /* 14 MA */ - }; - }; - - sdc1_cmd_off: sdc1_cmd_off { - config { - pins = "sdc1_cmd"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - sdc1_data_on: sdc1_data_on { - config { - pins = "sdc1_data"; - bias-pull-up; /* pull up */ - drive-strength = <14>; /* 14 MA */ - }; - }; - - sdc1_data_off: sdc1_data_off { - config { - pins = "sdc1_data"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - sdc1_rclk_on: sdc1_rclk_on { - config { - pins = "sdc1_rclk"; - bias-pull-down; /* pull down */ - }; - }; - - sdc1_rclk_off: sdc1_rclk_off { - config { - pins = "sdc1_rclk"; - bias-pull-down; /* pull down */ - }; - }; - - sdc2_clk_on: sdc2_clk_on { - config { - pins = "sdc2_clk"; - bias-disable; /* NO pull */ - drive-strength = <16>; /* 16 MA */ - }; - }; - - sdc2_clk_off: sdc2_clk_off { - config { - pins = "sdc2_clk"; - bias-disable; /* NO pull */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - sdc2_cmd_on: sdc2_cmd_on { - config { - pins = "sdc2_cmd"; - bias-pull-up; /* pull up */ - drive-strength = <14>; /* 14 MA */ - }; - }; - - sdc2_cmd_off: sdc2_cmd_off { - config { - pins = "sdc2_cmd"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - sdc2_data_on: sdc2_data_on { - config { - pins = "sdc2_data"; - bias-pull-up; /* pull up */ - drive-strength = <14>; /* 14 MA */ - }; - }; - - sdc2_data_off: sdc2_data_off { - config { - pins = "sdc2_data"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - sdc2_cd_on: cd_on { - mux { - pins = "gpio88"; - function = "gpio"; - }; - - config { - pins = "gpio88"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - sdc2_cd_off: cd_off { - mux { - pins = "gpio88"; - function = "gpio"; - }; - - config { - pins = "gpio88"; - drive-strength = <2>; bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_off: sdc1_off { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_on: sdc2_on { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sd-cd { + pins = "gpio88"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_off: sdc2_off { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + + sd-cd { + pins = "gpio88"; + bias-disable; + drive-strength = <2>; }; }; diff --git a/qcom/qrb2210-rb1.dtsi b/qcom/qrb2210-rb1.dtsi index 9fb48b4af2dc..89dee2890d18 100644 --- a/qcom/qrb2210-rb1.dtsi +++ b/qcom/qrb2210-rb1.dtsi @@ -31,6 +31,8 @@ aliases { serial0 = &qupv3_se4_2uart; hsuart0 = &qupv3_se3_4uart; + sdhc1 = &sdhc_1; /*SDC1 eMMC slot*/ + sdhc2 = &sdhc_2; /* SDC2 SD card slot */ }; cpus { @@ -487,6 +489,156 @@ thermal_zones: thermal-zones { }; + sdhc_1: sdhci@4744000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x04744000 0x1000>, <0x04745000 0x1000>; + reg-names = "hc_mem", "cqhci_mem"; + + iommus = <&apps_smmu 0xC0 0x0>; + qcom,iommu-dma = "bypass"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "core", "iface", "ice_core"; + + qcom,ice-clk-rates = <300000000 100000000>; + + interconnects = <&system_noc MASTER_SDCC_1 &bimc SLAVE_EBI_CH0>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_SDCC_1>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + qcom,msm-bus,name = "sdhc1"; + qcom,msm-bus,num-cases = <9>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* No vote */ + <78 512 0 0>, <1 606 0 0>, + /* 400 KB/s*/ + <78 512 1046 1600>, + <1 606 1600 1600>, + /* 20 MB/s */ + <78 512 20480 80000>, + <1 606 80000 80000>, + /* 25 MB/s */ + <78 512 25600 250000>, + <1 606 50000 133320>, + /* 50 MB/s */ + <78 512 51200 250000>, + <1 606 65000 133320>, + /* 100 MB/s */ + <78 512 102400 250000>, + <1 606 65000 133320>, + /* 200 MB/s */ + <78 512 204800 800000>, + <1 606 200000 300000>, + /* 400 MB/s */ + <78 512 204800 800000>, + <1 606 200000 300000>, + /* Max. bandwidth */ + <78 512 1338562 4096000>, + <1 606 1338562 4096000>; + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 + 100750000 200000000 400000000 4294967295>; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x000f642c 0x0 0x0 0x00010800 0x80040868>; + + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + + bus-width = <8>; + non-removable; + supports-cqe; + + no-sd; + no-sdio; + max-frequency = <192000000>; + + qcom,devfreq,freq-table = <50000000 200000000>; + qcom,scaling-lower-bus-speed-mode = "DDR52"; + + status = "disabled"; + + qos0 { + mask = <0x0f>; + vote = <43>; + }; + }; + + sdhc_2: sdhci@4784000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x4784000 0x1000>; + reg-names = "hc_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>; + clock-names = "core", "iface"; + + interconnects = <&system_noc MASTER_SDCC_2 &bimc SLAVE_EBI_CH0>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_SDCC_2>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + qcom,msm-bus,name = "sdhc2"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* No vote */ + <81 512 0 0>, <1 608 0 0>, + /* 400 KB/s*/ + <81 512 1046 3200>, + <1 608 1600 1600>, + /* 20 MB/s */ + <81 512 52286 250000>, + <1 608 80000 133320>, + /* 25 MB/s */ + <81 512 65360 250000>, + <1 608 100000 133320>, + /* 50 MB/s */ + <81 512 130718 250000>, + <1 608 133320 133320>, + /* 100 MB/s */ + <81 512 261438 250000>, + <1 608 150000 133320>, + /* 200 MB/s */ + <81 512 261438 800000>, + <1 608 300000 300000>, + /* Max. bandwidth */ + <81 512 1338562 4096000>, + <1 608 1338562 4096000>; + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 + 100750000 200000000 4294967295>; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x0007642c 0x0 0x0 0x00010800 0x80040868>; + + bus-width = <4>; + + iommus = <&apps_smmu 0xA0 0x0>; + qcom,iommu-dma = "bypass"; + + no-mmc; + no-sdio; + max-frequency = <202000000>; + + qcom,devfreq,freq-table = <50000000 202000000>; + + status = "disabled"; + + qos0 { + mask = <0x0f>; + vote = <43>; + }; + }; + qfprom: qfprom@1b40000 { compatible = "qcom,qfprom"; reg = <0x1b40000 0x7000>; From 8006e6d1e255dea55843a3e00e26070c999dc860 Mon Sep 17 00:00:00 2001 From: Hongwei Ren Date: Fri, 16 Apr 2021 18:36:08 +0530 Subject: [PATCH 3/5] ARM: dts: msm: Update kgsl smmu clock for scuba Update clock and vdd for KGSL smmu for scuba. Change-Id: Id0f9dd5661963070b10e9ed008b5143215dff493 --- qcom/msm-arm-smmu-qrb2210-rb1.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/qcom/msm-arm-smmu-qrb2210-rb1.dtsi b/qcom/msm-arm-smmu-qrb2210-rb1.dtsi index bb960362ef1a..9bd8921aef7a 100644 --- a/qcom/msm-arm-smmu-qrb2210-rb1.dtsi +++ b/qcom/msm-arm-smmu-qrb2210-rb1.dtsi @@ -12,6 +12,15 @@ qcom,use-3-lvl-tables; #global-interrupts = <1>; qcom,regulator-names = "vdd"; + vdd-supply = <&gpu_cx_gdsc>; + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + clock-names = "gcc_gpu_memnoc_gfx", + "gcc_gpu_snoc_dvm_gfx", + "gpu_cc_ahb", + "gpu_cc_hlos1_vote_gpu_smmu_clk"; #size-cells = <1>; ranges; interrupts = , @@ -148,6 +157,7 @@ qcom,stream-id-range = <0x400 0x400>; interrupts = ; qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc>; qcom,msm-bus,name = "apps_smmu"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,active-only; @@ -163,6 +173,7 @@ qcom,stream-id-range = <0x800 0x400>; interrupts = ; qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc>; qcom,msm-bus,name = "apps_smmu"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,active-only; From 33629e60bf24903edb186b7a251ca8fe692623f2 Mon Sep 17 00:00:00 2001 From: Hongwei Ren Date: Fri, 16 Apr 2021 18:40:36 +0530 Subject: [PATCH 4/5] ARM: dts: msm: Update SMMU Interconnect for scuba iot Update SMMU Interconnect for scuba iot. Change-Id: I72b30a9225bc39abd66316ce3ea9866e4f417607 --- qcom/msm-arm-smmu-qrb2210-rb1.dtsi | 41 +++++++++++++++-------------- qcom/qrb2210-rb1.dtsi | 42 ++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+), 20 deletions(-) diff --git a/qcom/msm-arm-smmu-qrb2210-rb1.dtsi b/qcom/msm-arm-smmu-qrb2210-rb1.dtsi index 9bd8921aef7a..39747390a54a 100644 --- a/qcom/msm-arm-smmu-qrb2210-rb1.dtsi +++ b/qcom/msm-arm-smmu-qrb2210-rb1.dtsi @@ -124,10 +124,10 @@ , , ; - qcom,msm-bus,name = "apps_smmu"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,active-only; - qcom,msm-bus,num-paths = <1>; + + interconnects = <&bimc MASTER_AMPSS_M0 + &system_noc SLAVE_TCU>; + qcom,active-only; qcom,actlr = /* For rt TBU +3 deep PF */ @@ -142,10 +142,11 @@ reg-names = "base", "status-reg"; qcom,stream-id-range = <0x0 0x400>; interrupts = ; - qcom,msm-bus,name = "apps_smmu"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,active-only; - qcom,msm-bus,num-paths = <2>; + interconnects = <&bimc MASTER_AMPSS_M0 + &config_noc SLAVE_IMEM_CFG>, + <&bimc MASTER_AMPSS_M0 + &system_noc SLAVE_TCU>; + qcom,active-only; }; @@ -155,14 +156,14 @@ <0xc782208 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x400 0x400>; - interrupts = ; qcom,regulator-names = "vdd"; vdd-supply = <&hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc>; - qcom,msm-bus,name = "apps_smmu"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,active-only; - qcom,msm-bus,num-paths = <2>; - + interrupts = ; + interconnects = <&mmrt_virt MASTER_MDP_PORT0 + &bimc SLAVE_EBI_CH0>, + <&bimc MASTER_AMPSS_M0 + &system_noc SLAVE_TCU>; + qcom,active-only; }; mm_nrt_tbu: mm_nrt_tbu@0xc78d000 { @@ -171,14 +172,14 @@ <0xc782210 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x800 0x400>; - interrupts = ; qcom,regulator-names = "vdd"; vdd-supply = <&hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc>; - qcom,msm-bus,name = "apps_smmu"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,active-only; - qcom,msm-bus,num-paths = <2>; - + interrupts = ; + interconnects = <&mmnrt_virt MASTER_CAMNOC_SF + &bimc SLAVE_EBI_CH0>, + <&bimc MASTER_AMPSS_M0 + &system_noc SLAVE_TCU>; + qcom,active-only; }; }; diff --git a/qcom/qrb2210-rb1.dtsi b/qcom/qrb2210-rb1.dtsi index 89dee2890d18..8538e991b26d 100644 --- a/qcom/qrb2210-rb1.dtsi +++ b/qcom/qrb2210-rb1.dtsi @@ -1289,6 +1289,44 @@ dcc: dcc_v2@1be2000 { "qcom,smp2p-early-crash-ind"; }; }; + + clk_virt: interconnect { + compatible = "qcom,scuba-clk_virt"; + #interconnect-cells = <1>; + }; + + mmnrt_virt: interconnect@0 { + compatible = "qcom,scuba-mmnrt_virt"; + #interconnect-cells = <1>; + }; + + mmrt_virt: interconnect@1 { + compatible = "qcom,scuba-mmrt_virt"; + #interconnect-cells = <1>; + }; + + system_noc: interconnect@1880000 { + reg = <0x01880000 0x60200>; + compatible = "qcom,scuba-system_noc"; + #interconnect-cells = <1>; + }; + + config_noc: interconnect@1900000 { + reg = <0x01900000 0x8200>; + compatible = "qcom,scuba-config_noc"; + #interconnect-cells = <1>; + }; + + bimc: interconnect@4480000 { + reg = <0x04480000 0x80000>; + compatible = "qcom,scuba-bimc"; + #interconnect-cells = <1>; + }; + + qcom-secure-buffer { + compatible = "qcom,secure-buffer"; + }; + }; #include "pm2250.dtsi" @@ -1584,3 +1622,7 @@ dcc: dcc_v2@1be2000 { }; }; }; + +&qupv3_se4_2uart { + status = "ok"; +}; From b915ad2e054788b93c9a747ddf5f3fef496d9a5a Mon Sep 17 00:00:00 2001 From: Hongwei Ren Date: Fri, 16 Apr 2021 18:43:23 +0530 Subject: [PATCH 5/5] ARM: dts: msm: add stub interconnect devices for Scuba Add stub interconnect devices for cnoc, snoc, bimc, qup_virt, mmnrt_virt and mmrt_virt. This will allow consumers to get their path and set bandwidth constraints on them. Change-Id: I4d7b831a26a2652a81b47bfeba230c0090955188 --- qcom/qrb2210-rb1.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/qrb2210-rb1.dtsi b/qcom/qrb2210-rb1.dtsi index 8538e991b26d..8a29cb7466e9 100644 --- a/qcom/qrb2210-rb1.dtsi +++ b/qcom/qrb2210-rb1.dtsi @@ -1,4 +1,6 @@ #include +#include +#include #include #include #include