From b2225a04ac7c95ac24c8bb9d64b497ed75477f6e Mon Sep 17 00:00:00 2001
From: Santosh Dronamraju <sdronamr@codeaurora.org>
Date: Tue, 30 Mar 2021 06:01:39 +0530
Subject: [PATCH] soc: qcom: Add support for EMMC storage type

Add support for parsing EMMC specific crypto engine type
in crypto qti tz driver.

Test:
Device booted upto UI with File Based Encryption enabled.

Change-Id: Id6354e69dc32a2c68ba81450e8a9c0e015779f4f
Signed-off-by: Santosh Dronamraju <sdronamr@codeaurora.org>
---
 drivers/soc/qcom/crypto-qti-tz.c | 38 +++++++++++++++++++++++++++-----
 1 file changed, 33 insertions(+), 5 deletions(-)

diff --git a/drivers/soc/qcom/crypto-qti-tz.c b/drivers/soc/qcom/crypto-qti-tz.c
index 5a675210db52..ac74805ce242 100644
--- a/drivers/soc/qcom/crypto-qti-tz.c
+++ b/drivers/soc/qcom/crypto-qti-tz.c
@@ -2,7 +2,7 @@
 /*
  * Crypto TZ library for storage encryption.
  *
- * Copyright (c) 2020, Linux Foundation. All rights reserved.
+ * Copyright (c) 2020-2021, Linux Foundation. All rights reserved.
  */
 
 #include <asm/cacheflush.h>
@@ -10,6 +10,7 @@
 #include <linux/qtee_shmbridge.h>
 #include <linux/crypto-qti-common.h>
 #include <linux/module.h>
+#include <linux/of.h>
 #include "crypto-qti-platform.h"
 
 #define ICE_CIPHER_MODE_XTS_256 3
@@ -17,6 +18,24 @@
 #define SDCC_CE 20
 #define UFS_CARD_CE 30
 
+static bool is_boot_dev_type_emmc(void)
+{
+	struct device_node *np;
+	const char *bootparams;
+
+	np = of_find_node_by_path("/chosen");
+	of_property_read_string(np, "bootargs", &bootparams);
+	if (!bootparams)
+		pr_err("%s: failed to get bootargs property\n", __func__);
+	else if (strnstr(bootparams, "androidboot.bootdevice",
+			strlen(bootparams)) &&
+			strnstr(bootparams, "sdhci", strlen(bootparams)))
+		return true;
+
+	return false;
+
+}
+
 int crypto_qti_program_key(struct crypto_vops_qti_entry *ice_entry,
 			   const struct blk_crypto_key *key, unsigned int slot,
 			   unsigned int data_unit_mask, int capid)
@@ -31,9 +50,14 @@ int crypto_qti_program_key(struct crypto_vops_qti_entry *ice_entry,
 	memcpy(shm.vaddr, key->raw, key->size);
 	qtee_shmbridge_flush_shm_buf(&shm);
 
-	err = qcom_scm_config_set_ice_key(slot, shm.paddr, key->size,
-					ICE_CIPHER_MODE_XTS_256,
-					data_unit_mask, UFS_CE);
+	if (is_boot_dev_type_emmc())
+		err = qcom_scm_config_set_ice_key(slot, shm.paddr, key->size,
+						ICE_CIPHER_MODE_XTS_256,
+						data_unit_mask, SDCC_CE);
+	else
+		err = qcom_scm_config_set_ice_key(slot, shm.paddr, key->size,
+						ICE_CIPHER_MODE_XTS_256,
+						data_unit_mask, UFS_CE);
 	if (err)
 		pr_err("%s:SCM call Error: 0x%x slot %d\n",
 				__func__, err, slot);
@@ -50,7 +74,11 @@ int crypto_qti_invalidate_key(struct crypto_vops_qti_entry *ice_entry,
 {
 	int err = 0;
 
-	err = qcom_scm_clear_ice_key(slot, UFS_CE);
+	if (is_boot_dev_type_emmc())
+		err = qcom_scm_clear_ice_key(slot, SDCC_CE);
+	else
+		err = qcom_scm_clear_ice_key(slot, UFS_CE);
+
 	if (err)
 		pr_err("%s:SCM call Error: 0x%x\n", __func__, err);