diff --git a/bindings/pci/pci-msm.txt b/bindings/pci/pci-msm.txt
index 6c6285f4e714..6f3e41eac5bc 100644
--- a/bindings/pci/pci-msm.txt
+++ b/bindings/pci/pci-msm.txt
@@ -290,6 +290,13 @@ interconnects:
 	Definition: L1.2 LTR threshold value to be multipled with scale to
 		define L1.2 latency tolerance reporting (LTR)
 
+- qcom,eq-fmdc-t-min-phase23:
+	Usage: optional
+	Value type: <u32>
+	Definition: Determines minimum time (ms) to remain in equalization
+		master phase before checking for convergence of the
+		coefficients.
+
 - qcom,slv-addr-space-size:
 	Usage: required
 	Value type: <u32>
@@ -519,6 +526,7 @@ Example
 		qcom,no-l1-supported;
 		qcom,no-l1ss-supported;
 		qcom,no-aux-clk-sync;
+		qcom,eq-fmdc-t-min-phase23 = <1>; /* 1ms */
 		qcom,slv-addr-space-size = <0x1000000>; /* 16MB */
 		qcom,wr-halt-size = <0xa>; /* 1KB */
 		qcom,tlp-rd-size = <0x5>; /* 4KB */
diff --git a/qcom/sdxlemur-pcie.dtsi b/qcom/sdxlemur-pcie.dtsi
index 8df0c684343a..5d7bf48210b2 100644
--- a/qcom/sdxlemur-pcie.dtsi
+++ b/qcom/sdxlemur-pcie.dtsi
@@ -46,15 +46,30 @@
 		vreg-1p8-supply = <&pmx65_l1>;
 		vreg-0p9-supply = <&pmx65_l4>;
 		vreg-cx-supply = <&VDD_CX_LEVEL>;
+		vreg-mx-supply = <&VDD_MXA_LEVEL>;
+
 		qcom,vreg-1p8-voltage-level = <1200000 1200000 30000>;
 		qcom,vreg-0p9-voltage-level = <912000 912000 132000>;
 		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
 						RPMH_REGULATOR_LEVEL_LOW_SVS 0>;
-		qcom,bw-scale =
-			<RPMH_REGULATOR_LEVEL_LOW_SVS 100000000 /* Gen1 */
-			RPMH_REGULATOR_LEVEL_LOW_SVS 100000000 /* Gen2 */
-			RPMH_REGULATOR_LEVEL_LOW_SVS 100000000 /* Gen3 */
-			RPMH_REGULATOR_LEVEL_LOW_SVS 100000000>; /* Gen4 */
+		qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
+						RPMH_REGULATOR_LEVEL_NOM 0>;
+		qcom,bw-scale = /* Gen1 */
+				<RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				100000000
+				/* Gen2 */
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				100000000
+				/* Gen3 */
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				100000000
+				/* Gen4 */
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_NOM
+				100000000>;
 
 		interconnect-names = "icc_path";
 		interconnects = <&system_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
@@ -92,6 +107,7 @@
 			<0x100 &apps_smmu 0x0201 0x1>;
 
 		qcom,aux-clk-freq = <17>; /* 16.6 MHz */
+		qcom,eq-fmdc-t-min-phase23 = <1>;
 		qcom,slv-addr-space-size = <0x40000000>;
 		qcom,ep-latency = <10>;