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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-12 07:37:31 -04:00
Merge "ARM: dts: msm: Add primary and secondary USB nodes on Direwolf"
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qctecmdr
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2 changed files with 196 additions and 0 deletions
188
qcom/direwolf-usb.dtsi
Normal file
188
qcom/direwolf-usb.dtsi
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@ -0,0 +1,188 @@
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&soc {
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usb0: ssusb@a600000 {
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compatible = "qcom,dwc-usb3-msm";
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reg = <0xa600000 0x100000>;
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reg-names = "core_base";
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iommus = <&apps_smmu 0x0820 0x0>;
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qcom,iommu-dma = "atomic";
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qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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dma-ranges;
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interrupts-extended = <&pdc 14 IRQ_TYPE_EDGE_RISING>,
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<&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
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<&pdc 138 IRQ_TYPE_LEVEL_HIGH>,
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<&pdc 15 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
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"ss_phy_irq", "dm_hs_phy_irq";
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qcom,use-pdc-interrupts;
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USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;
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clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
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<&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
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<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
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<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
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<&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
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<&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
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<&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
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<&gcc GCC_SYS_NOC_USB_AXI_CLK>;
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clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
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"utmi_clk", "sleep_clk", "noc_aggr_clk",
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"noc_aggr_north_clk", "noc_aggr_south_clk",
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"noc_sys_clk";
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resets = <&gcc GCC_USB30_PRIM_BCR>;
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reset-names = "core_reset";
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qcom,core-clk-rate = <200000000>;
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qcom,core-clk-rate-hs = <66666667>;
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qcom,dwc-usb3-msm-tx-fifo-size = <27696>;
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interconnect-names = "usb-ddr", "ddr-usb";
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interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>,
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<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>;
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dwc3@a600000 {
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compatible = "snps,dwc3";
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reg = <0xa600000 0xd93c>;
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interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>;
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usb-phy = <&usb2_phy0>, <&usb_nop_phy>;
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linux,sysdev_is_parent;
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snps,disable-clk-gating;
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snps,has-lpm-erratum;
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snps,hird-threshold = /bits/ 8 <0x0>;
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snps,ssp-u3-u0-quirk;
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snps,is-utmi-l1-suspend;
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snps,dis-u1-entry-quirk;
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snps,dis-u2-entry-quirk;
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tx-fifo-resize;
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maximum-speed = "high-speed";
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dr_mode = "otg";
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};
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};
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/* Primary USB port related High Speed PHY */
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usb2_phy0: hsphy@88e5000 {
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compatible = "qcom,usb-hsphy-snps-femto";
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reg = <0x88e5000 0x120>;
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reg-names = "hsusb_phy_base";
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vdd-supply = <&L5A0>;
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vdda18-supply = <&L7A0>;
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vdda33-supply = <&L13A0>;
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qcom,vdd-voltage-level = <0 912000 912000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "ref_clk_src";
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resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
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reset-names = "phy_reset";
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qcom,param-override-seq =
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<0xe6 0x6c /* override_x0 */
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0x0b 0x70 /* override_x1 */
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0x17 0x74>; /* override x2 */
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};
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usb_nop_phy: usb_nop_phy {
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compatible = "usb-nop-xceiv";
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};
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usb1: ssusb@a800000 {
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compatible = "qcom,dwc-usb3-msm";
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reg = <0xa800000 0x100000>;
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reg-names = "core_base";
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iommus = <&apps_smmu 0x0860 0x0>;
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qcom,iommu-dma = "atomic";
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qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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dma-ranges;
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interrupts-extended = <&pdc 12 IRQ_TYPE_EDGE_RISING>,
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<&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
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<&pdc 136 IRQ_TYPE_LEVEL_HIGH>,
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<&pdc 13 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
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"ss_phy_irq", "dm_hs_phy_irq";
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qcom,use-pdc-interrupts;
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USB3_GDSC-supply = <&gcc_usb30_sec_gdsc>;
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clocks = <&gcc GCC_USB30_SEC_MASTER_CLK>,
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<&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
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<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
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<&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_SEC_SLEEP_CLK>,
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<&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
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<&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
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<&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
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<&gcc GCC_SYS_NOC_USB_AXI_CLK>;
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clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
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"utmi_clk", "sleep_clk", "noc_aggr_clk",
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"noc_aggr_north_clk", "noc_aggr_south_clk",
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"noc_sys_clk";
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resets = <&gcc GCC_USB30_SEC_BCR>;
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reset-names = "core_reset";
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qcom,core-clk-rate = <200000000>;
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qcom,core-clk-rate-hs = <66666667>;
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qcom,dwc-usb3-msm-tx-fifo-size = <27696>;
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qcom,default-mode-host;
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interconnect-names = "usb-ddr", "ddr-usb";
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interconnects = <&aggre1_noc MASTER_USB3_1 &mc_virt SLAVE_EBI1>,
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<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_1>;
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dwc3@a800000 {
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compatible = "snps,dwc3";
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reg = <0xa800000 0xd93c>;
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interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>;
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usb-phy = <&usb2_phy1>, <&usb_nop_phy>;
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linux,sysdev_is_parent;
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snps,disable-clk-gating;
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snps,has-lpm-erratum;
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snps,hird-threshold = /bits/ 8 <0x0>;
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snps,ssp-u3-u0-quirk;
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snps,is-utmi-l1-suspend;
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snps,dis-u1-entry-quirk;
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snps,dis-u2-entry-quirk;
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tx-fifo-resize;
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maximum-speed = "high-speed";
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dr_mode = "otg";
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};
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};
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/* Secondary USB port related High Speed PHY */
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usb2_phy1: hsphy@8902000 {
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compatible = "qcom,usb-hsphy-snps-femto";
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reg = <0x8902000 0x120>;
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reg-names = "hsusb_phy_base";
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vdd-supply = <&L1C0>;
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vdda18-supply = <&L7C0>;
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vdda33-supply = <&L2C0>;
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qcom,vdd-voltage-level = <0 912000 912000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "ref_clk_src";
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resets = <&gcc GCC_USB2_PHY_SEC_BCR>;
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reset-names = "phy_reset";
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qcom,param-override-seq =
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<0xe6 0x6c /* override_x0 */
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0x0b 0x70 /* override_x1 */
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0x17 0x74>; /* override x2 */
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};
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};
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@ -30,6 +30,8 @@
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aliases {
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ufshc1 = &ufshc_mem; /* Embedded UFS slot */
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serial0 = &qupv3_se17_2uart;
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hsuart0 = &qupv3_se2_4uart;
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};
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cpus {
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@ -1629,6 +1631,8 @@
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#include "direwolf-gdsc.dtsi"
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#include "direwolf-ion.dtsi"
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#include "msm-arm-smmu-direwolf.dtsi"
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#include "direwolf-qupv3.dtsi"
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#include "direwolf-usb.dtsi"
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&gcc_emac0_gdsc {
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status = "ok"
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@ -1725,3 +1729,7 @@
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&hlos1_vote_turing_mmu_tbu3_gdsc {
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status = "ok"
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};
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&qupv3_se17_2uart {
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status = "ok"
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};
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