From 3b821d84425756e32995eec85c213d8bc834b82e Mon Sep 17 00:00:00 2001 From: Raghavendra Rao Ananta Date: Tue, 4 Aug 2020 14:34:57 -0700 Subject: [PATCH] soc: qcom: llcc: Add support for CPU TLB System Cache Id Enable the CPU TLB System Cache Id by adding CPUHWT entry to the Lahaina's LLCC SCT list and move the priority of LCC_DISP to 2. Change-Id: I0184d4f997961782d51ed98c18e19e3bbc67759a Signed-off-by: Raghavendra Rao Ananta --- drivers/soc/qcom/llcc-lahaina.c | 3 ++- include/linux/soc/qcom/llcc-qcom.h | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/soc/qcom/llcc-lahaina.c b/drivers/soc/qcom/llcc-lahaina.c index a49d579ad7ad..612d84384712 100644 --- a/drivers/soc/qcom/llcc-lahaina.c +++ b/drivers/soc/qcom/llcc-lahaina.c @@ -60,7 +60,7 @@ static struct llcc_slice_config lahaina_data[] = { SCT_ENTRY(LLCC_GPUHTW, 11, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), SCT_ENTRY(LLCC_GPU, 12, 1024, 1, 0, 0xFFF, 0x0, 0, 0, 0, 1, 1, 0), SCT_ENTRY(LLCC_MMUHWT, 13, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 1), - SCT_ENTRY(LLCC_DISP, 16, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), + SCT_ENTRY(LLCC_DISP, 16, 3072, 2, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), SCT_ENTRY(LLCC_MDMPNG, 21, 1024, 0, 1, 0xF, 0x0, 0, 0, 0, 0, 1, 0), SCT_ENTRY(LLCC_AUDHW, 22, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), SCT_ENTRY(LLCC_CVP, 28, 512, 3, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), @@ -69,6 +69,7 @@ static struct llcc_slice_config lahaina_data[] = { SCT_ENTRY(LLCC_WRTCH, 31, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 1), SCT_ENTRY(LLCC_CVPFW, 17, 512, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), SCT_ENTRY(LLCC_CPUSS1, 3, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), + SCT_ENTRY(LLCC_CPUHWT, 5, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 1), }; static int lahaina_qcom_llcc_probe(struct platform_device *pdev) diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h index beb342a9ddb5..c36ff29b3701 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. * */ @@ -33,6 +33,7 @@ #define LLCC_WRTCH 31 #define LLCC_CVPFW 32 #define LLCC_CPUSS1 33 +#define LLCC_CPUHWT 36 /** * llcc_slice_desc - Cache slice descriptor