From c03a607b0c4b230df874fe1847422d68d9f79468 Mon Sep 17 00:00:00 2001 From: Aniket Randive Date: Mon, 20 Apr 2020 20:49:11 +0530 Subject: [PATCH 1/4] ARM: dts: msm: Add macros for QMP USB register offsets on SA8155 Add macro definitions in a dt-bindings header file for all the QMP USB DP and USB UNI PHY register offsets. Change-Id: Id04ab6faede01471196d06d6729f97fb1076119f Signed-off-by: Aniket Randive --- .../dt-bindings/phy/qcom,sm8150-qmp-usb3.h | 1315 +++++++++++++++++ 1 file changed, 1315 insertions(+) create mode 100644 include/dt-bindings/phy/qcom,sm8150-qmp-usb3.h diff --git a/include/dt-bindings/phy/qcom,sm8150-qmp-usb3.h b/include/dt-bindings/phy/qcom,sm8150-qmp-usb3.h new file mode 100644 index 000000000000..cd4970cc2e3f --- /dev/null +++ b/include/dt-bindings/phy/qcom,sm8150-qmp-usb3.h @@ -0,0 +1,1315 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ +#ifndef _DT_BINDINGS_PHY_QCOM_SM8150_QMP_USB_H +#define _DT_BINDINGS_PHY_QCOM_SM8150_QMP_USB_H + +/* USB3-DP Combo PHY register offsets */ +#define USB3_DP_COM_PHY_MODE_CTRL 0x0000 +#define USB3_DP_COM_SW_RESET 0x0004 +#define USB3_DP_COM_POWER_DOWN_CTRL 0x0008 +#define USB3_DP_COM_SWI_CTRL 0x000C +#define USB3_DP_COM_TYPEC_CTRL 0x0010 +#define USB3_DP_COM_TYPEC_PWRDN_CTRL 0x0014 +#define USB3_DP_COM_DP_BIST_CFG_0 0x0018 +#define USB3_DP_COM_RESET_OVRD_CTRL 0x001C +#define USB3_DP_COM_DBG_CLK_MUX_CTRL 0x0020 +#define USB3_DP_COM_TYPEC_STATUS 0x0024 +#define USB3_DP_COM_PLACEHOLDER_STATUS 0x0028 +#define USB3_DP_COM_REVISION_ID0 0x002C +#define USB3_DP_COM_REVISION_ID1 0x0030 +#define USB3_DP_COM_REVISION_ID2 0x0034 +#define USB3_DP_COM_REVISION_ID3 0x0038 +#define USB3_DP_QSERDES_COM_ATB_SEL1 0x1000 +#define USB3_DP_QSERDES_COM_ATB_SEL2 0x1004 +#define USB3_DP_QSERDES_COM_FREQ_UPDATE 0x1008 +#define USB3_DP_QSERDES_COM_BG_TIMER 0x100C +#define USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x1010 +#define USB3_DP_QSERDES_COM_SSC_ADJ_PER1 0x1014 +#define USB3_DP_QSERDES_COM_SSC_ADJ_PER2 0x1018 +#define USB3_DP_QSERDES_COM_SSC_PER1 0x101C +#define USB3_DP_QSERDES_COM_SSC_PER2 0x1020 +#define USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0x1024 +#define USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x1028 +#define USB3_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE0 0x102C +#define USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0x1030 +#define USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x1034 +#define USB3_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE1 0x1038 +#define USB3_DP_QSERDES_COM_POST_DIV 0x103C +#define USB3_DP_QSERDES_COM_POST_DIV_MUX 0x1040 +#define USB3_DP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x1044 +#define USB3_DP_QSERDES_COM_CLK_ENABLE1 0x1048 +#define USB3_DP_QSERDES_COM_SYS_CLK_CTRL 0x104C +#define USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x1050 +#define USB3_DP_QSERDES_COM_PLL_EN 0x1054 +#define USB3_DP_QSERDES_COM_PLL_IVCO 0x1058 +#define USB3_DP_QSERDES_COM_CMN_IETRIM 0x105C +#define USB3_DP_QSERDES_COM_CMN_IPTRIM 0x1060 +#define USB3_DP_QSERDES_COM_EP_CLOCK_DETECT_CTRL 0x1064 +#define USB3_DP_QSERDES_COM_SYSCLK_DET_COMP_STATUS 0x1068 +#define USB3_DP_QSERDES_COM_CLK_EP_DIV_MODE0 0x106C +#define USB3_DP_QSERDES_COM_CLK_EP_DIV_MODE1 0x1070 +#define USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x1074 +#define USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x1078 +#define USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x107C +#define USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1 0x1080 +#define USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x1084 +#define USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1 0x1088 +#define USB3_DP_QSERDES_COM_PLL_CNTRL 0x108C +#define USB3_DP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x1090 +#define USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x1094 +#define USB3_DP_QSERDES_COM_CML_SYSCLK_SEL 0x1098 +#define USB3_DP_QSERDES_COM_RESETSM_CNTRL 0x109C +#define USB3_DP_QSERDES_COM_RESETSM_CNTRL2 0x10A0 +#define USB3_DP_QSERDES_COM_LOCK_CMP_EN 0x10A4 +#define USB3_DP_QSERDES_COM_LOCK_CMP_CFG 0x10A8 +#define USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x10AC +#define USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x10B0 +#define USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1 0x10B4 +#define USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1 0x10B8 +#define USB3_DP_QSERDES_COM_DEC_START_MODE0 0x10BC +#define USB3_DP_QSERDES_COM_DEC_START_MSB_MODE0 0x10C0 +#define USB3_DP_QSERDES_COM_DEC_START_MODE1 0x10C4 +#define USB3_DP_QSERDES_COM_DEC_START_MSB_MODE1 0x10C8 +#define USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0x10CC +#define USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0x10D0 +#define USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x10D4 +#define USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0x10D8 +#define USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0x10DC +#define USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x10E0 +#define USB3_DP_QSERDES_COM_INTEGLOOP_INITVAL 0x10E4 +#define USB3_DP_QSERDES_COM_INTEGLOOP_EN 0x10E8 +#define USB3_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x10EC +#define USB3_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10F0 +#define USB3_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x10F4 +#define USB3_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x10F8 +#define USB3_DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0 0x10FC +#define USB3_DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1 0x1100 +#define USB3_DP_QSERDES_COM_VCOCAL_DEADMAN_CTRL 0x1104 +#define USB3_DP_QSERDES_COM_VCO_TUNE_CTRL 0x1108 +#define USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x110C +#define USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x1110 +#define USB3_DP_QSERDES_COM_VCO_TUNE2_MODE0 0x1114 +#define USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x1118 +#define USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x111C +#define USB3_DP_QSERDES_COM_VCO_TUNE_INITVAL1 0x1120 +#define USB3_DP_QSERDES_COM_VCO_TUNE_INITVAL2 0x1124 +#define USB3_DP_QSERDES_COM_VCO_TUNE_MINVAL1 0x1128 +#define USB3_DP_QSERDES_COM_VCO_TUNE_MINVAL2 0x112C +#define USB3_DP_QSERDES_COM_VCO_TUNE_MAXVAL1 0x1130 +#define USB3_DP_QSERDES_COM_VCO_TUNE_MAXVAL2 0x1134 +#define USB3_DP_QSERDES_COM_VCO_TUNE_TIMER1 0x1138 +#define USB3_DP_QSERDES_COM_VCO_TUNE_TIMER2 0x113C +#define USB3_DP_QSERDES_COM_CMN_STATUS 0x1140 +#define USB3_DP_QSERDES_COM_RESET_SM_STATUS 0x1144 +#define USB3_DP_QSERDES_COM_RESTRIM_CODE_STATUS 0x1148 +#define USB3_DP_QSERDES_COM_PLLCAL_CODE1_STATUS 0x114C +#define USB3_DP_QSERDES_COM_PLLCAL_CODE2_STATUS 0x1150 +#define USB3_DP_QSERDES_COM_CLK_SELECT 0x1154 +#define USB3_DP_QSERDES_COM_HSCLK_SEL 0x1158 +#define USB3_DP_QSERDES_COM_HSCLK_HS_SWITCH_SEL 0x115C +#define USB3_DP_QSERDES_COM_INTEGLOOP_BINCODE_STATUS 0x1160 +#define USB3_DP_QSERDES_COM_PLL_ANALOG 0x1164 +#define USB3_DP_QSERDES_COM_CORECLK_DIV_MODE0 0x1168 +#define USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x116C +#define USB3_DP_QSERDES_COM_SW_RESET 0x1170 +#define USB3_DP_QSERDES_COM_CORE_CLK_EN 0x1174 +#define USB3_DP_QSERDES_COM_C_READY_STATUS 0x1178 +#define USB3_DP_QSERDES_COM_CMN_CONFIG 0x117C +#define USB3_DP_QSERDES_COM_CMN_RATE_OVERRIDE 0x1180 +#define USB3_DP_QSERDES_COM_SVS_MODE_CLK_SEL 0x1184 +#define USB3_DP_QSERDES_COM_DEBUG_BUS0 0x1188 +#define USB3_DP_QSERDES_COM_DEBUG_BUS1 0x118C +#define USB3_DP_QSERDES_COM_DEBUG_BUS2 0x1190 +#define USB3_DP_QSERDES_COM_DEBUG_BUS3 0x1194 +#define USB3_DP_QSERDES_COM_DEBUG_BUS_SEL 0x1198 +#define USB3_DP_QSERDES_COM_CMN_MISC1 0x119C +#define USB3_DP_QSERDES_COM_CMN_MISC2 0x11A0 +#define USB3_DP_QSERDES_COM_CMN_MODE 0x11A4 +#define USB3_DP_QSERDES_COM_VCO_DC_LEVEL_CTRL 0x11A8 +#define USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x11AC +#define USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x11B0 +#define USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x11B4 +#define USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x11B8 +#define USB3_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11BC +#define USB3_DP_QSERDES_TXA_BIST_MODE_LANENO 0x1200 +#define USB3_DP_QSERDES_TXA_BIST_INVERT 0x1204 +#define USB3_DP_QSERDES_TXA_CLKBUF_ENABLE 0x1208 +#define USB3_DP_QSERDES_TXA_TX_EMP_POST1_LVL 0x120C +#define USB3_DP_QSERDES_TXA_TX_IDLE_LVL_LARGE_AMP 0x1210 +#define USB3_DP_QSERDES_TXA_TX_DRV_LVL 0x1214 +#define USB3_DP_QSERDES_TXA_TX_DRV_LVL_OFFSET 0x1218 +#define USB3_DP_QSERDES_TXA_RESET_TSYNC_EN 0x121C +#define USB3_DP_QSERDES_TXA_PRE_STALL_LDO_BOOST_EN 0x1220 +#define USB3_DP_QSERDES_TXA_TX_BAND 0x1224 +#define USB3_DP_QSERDES_TXA_SLEW_CNTL 0x1228 +#define USB3_DP_QSERDES_TXA_INTERFACE_SELECT 0x122C +#define USB3_DP_QSERDES_TXA_LPB_EN 0x1230 +#define USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x1234 +#define USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x1238 +#define USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x123C +#define USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x1240 +#define USB3_DP_QSERDES_TXA_PERL_LENGTH1 0x1244 +#define USB3_DP_QSERDES_TXA_PERL_LENGTH2 0x1248 +#define USB3_DP_QSERDES_TXA_SERDES_BYP_EN_OUT 0x124C +#define USB3_DP_QSERDES_TXA_DEBUG_BUS_SEL 0x1250 +#define USB3_DP_QSERDES_TXA_TRANSCEIVER_BIAS_EN 0x1254 +#define USB3_DP_QSERDES_TXA_HIGHZ_DRVR_EN 0x1258 +#define USB3_DP_QSERDES_TXA_TX_POL_INV 0x125C +#define USB3_DP_QSERDES_TXA_PARRATE_REC_DETECT_IDLE_EN 0x1260 +#define USB3_DP_QSERDES_TXA_BIST_PATTERN1 0x1264 +#define USB3_DP_QSERDES_TXA_BIST_PATTERN2 0x1268 +#define USB3_DP_QSERDES_TXA_BIST_PATTERN3 0x126C +#define USB3_DP_QSERDES_TXA_BIST_PATTERN4 0x1270 +#define USB3_DP_QSERDES_TXA_BIST_PATTERN5 0x1274 +#define USB3_DP_QSERDES_TXA_BIST_PATTERN6 0x1278 +#define USB3_DP_QSERDES_TXA_BIST_PATTERN7 0x127C +#define USB3_DP_QSERDES_TXA_BIST_PATTERN8 0x1280 +#define USB3_DP_QSERDES_TXA_LANE_MODE_1 0x1284 +#define USB3_DP_QSERDES_TXA_LANE_MODE_2 0x1288 +#define USB3_DP_QSERDES_TXA_LANE_MODE_3 0x128C +#define USB3_DP_QSERDES_TXA_ATB_SEL1 0x1290 +#define USB3_DP_QSERDES_TXA_ATB_SEL2 0x1294 +#define USB3_DP_QSERDES_TXA_RCV_DETECT_LVL 0x1298 +#define USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x129C +#define USB3_DP_QSERDES_TXA_PRBS_SEED1 0x12A0 +#define USB3_DP_QSERDES_TXA_PRBS_SEED2 0x12A4 +#define USB3_DP_QSERDES_TXA_PRBS_SEED3 0x12A8 +#define USB3_DP_QSERDES_TXA_PRBS_SEED4 0x12AC +#define USB3_DP_QSERDES_TXA_RESET_GEN 0x12B0 +#define USB3_DP_QSERDES_TXA_RESET_GEN_MUXES 0x12B4 +#define USB3_DP_QSERDES_TXA_TRAN_DRVR_EMP_EN 0x12B8 +#define USB3_DP_QSERDES_TXA_TX_INTERFACE_MODE 0x12BC +#define USB3_DP_QSERDES_TXA_PWM_CTRL 0x12C0 +#define USB3_DP_QSERDES_TXA_PWM_ENCODED_OR_DATA 0x12C4 +#define USB3_DP_QSERDES_TXA_PWM_GEAR_1_DIVIDER_BAND2 0x12C8 +#define USB3_DP_QSERDES_TXA_PWM_GEAR_2_DIVIDER_BAND2 0x12CC +#define USB3_DP_QSERDES_TXA_PWM_GEAR_3_DIVIDER_BAND2 0x12D0 +#define USB3_DP_QSERDES_TXA_PWM_GEAR_4_DIVIDER_BAND2 0x12D4 +#define USB3_DP_QSERDES_TXA_PWM_GEAR_1_DIVIDER_BAND0_1 0x12D8 +#define USB3_DP_QSERDES_TXA_PWM_GEAR_2_DIVIDER_BAND0_1 0x12DC +#define USB3_DP_QSERDES_TXA_PWM_GEAR_3_DIVIDER_BAND0_1 0x12E0 +#define USB3_DP_QSERDES_TXA_PWM_GEAR_4_DIVIDER_BAND0_1 0x12E4 +#define USB3_DP_QSERDES_TXA_VMODE_CTRL1 0x12E8 +#define USB3_DP_QSERDES_TXA_ALOG_OBSV_BUS_CTRL_1 0x12EC +#define USB3_DP_QSERDES_TXA_BIST_STATUS 0x12F0 +#define USB3_DP_QSERDES_TXA_BIST_ERROR_COUNT1 0x12F4 +#define USB3_DP_QSERDES_TXA_BIST_ERROR_COUNT2 0x12F8 +#define USB3_DP_QSERDES_TXA_ALOG_OBSV_BUS_STATUS_1 0x12FC +#define USB3_DP_QSERDES_TXA_LANE_DIG_CONFIG 0x1300 +#define USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x1304 +#define USB3_DP_QSERDES_TXA_PRE_EMPH 0x1308 +#define USB3_DP_QSERDES_TXA_SW_RESET 0x130C +#define USB3_DP_QSERDES_TXA_DIG_BKUP_CTRL 0x1310 +#define USB3_DP_QSERDES_TXA_DEBUG_BUS0 0x1314 +#define USB3_DP_QSERDES_TXA_DEBUG_BUS1 0x1318 +#define USB3_DP_QSERDES_TXA_DEBUG_BUS2 0x131C +#define USB3_DP_QSERDES_TXA_DEBUG_BUS3 0x1320 +#define USB3_DP_QSERDES_TXA_READ_EQCODE 0x1324 +#define USB3_DP_QSERDES_TXA_READ_OFFSETCODE 0x1328 +#define USB3_DP_QSERDES_TXA_IA_ERROR_COUNTER_LOW 0x132C +#define USB3_DP_QSERDES_TXA_IA_ERROR_COUNTER_HIGH 0x1330 +#define USB3_DP_QSERDES_TXA_VGA_READ_CODE 0x1334 +#define USB3_DP_QSERDES_TXA_VTH_READ_CODE 0x1338 +#define USB3_DP_QSERDES_TXA_DFE_TAP1_READ_CODE 0x133C +#define USB3_DP_QSERDES_TXA_DFE_TAP2_READ_CODE 0x1340 +#define USB3_DP_QSERDES_TXA_IDAC_STATUS_I 0x1344 +#define USB3_DP_QSERDES_TXA_IDAC_STATUS_IBAR 0x1348 +#define USB3_DP_QSERDES_TXA_IDAC_STATUS_Q 0x134C +#define USB3_DP_QSERDES_TXA_IDAC_STATUS_QBAR 0x1350 +#define USB3_DP_QSERDES_TXA_IDAC_STATUS_A 0x1354 +#define USB3_DP_QSERDES_TXA_IDAC_STATUS_ABAR 0x1358 +#define USB3_DP_QSERDES_TXA_IDAC_STATUS_SM_ON 0x135C +#define USB3_DP_QSERDES_TXA_IDAC_STATUS_CAL_DONE 0x1360 +#define USB3_DP_QSERDES_TXA_IDAC_STATUS_SIGNERROR 0x1364 +#define USB3_DP_QSERDES_TXA_DCC_CAL_STATUS 0x1368 +#define USB3_DP_QSERDES_RXA_UCDR_FO_GAIN_HALF 0x1400 +#define USB3_DP_QSERDES_RXA_UCDR_FO_GAIN_QUARTER 0x1404 +#define USB3_DP_QSERDES_RXA_UCDR_FO_GAIN 0x1408 +#define USB3_DP_QSERDES_RXA_UCDR_SO_GAIN_HALF 0x140C +#define USB3_DP_QSERDES_RXA_UCDR_SO_GAIN_QUARTER 0x1410 +#define USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x1414 +#define USB3_DP_QSERDES_RXA_UCDR_SVS_FO_GAIN_HALF 0x1418 +#define USB3_DP_QSERDES_RXA_UCDR_SVS_FO_GAIN_QUARTER 0x141C +#define USB3_DP_QSERDES_RXA_UCDR_SVS_FO_GAIN 0x1420 +#define USB3_DP_QSERDES_RXA_UCDR_SVS_SO_GAIN_HALF 0x1424 +#define USB3_DP_QSERDES_RXA_UCDR_SVS_SO_GAIN_QUARTER 0x1428 +#define USB3_DP_QSERDES_RXA_UCDR_SVS_SO_GAIN 0x142C +#define USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x1430 +#define USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x1434 +#define USB3_DP_QSERDES_RXA_UCDR_FO_TO_SO_DELAY 0x1438 +#define USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0x143C +#define USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x1440 +#define USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x1444 +#define USB3_DP_QSERDES_RXA_UCDR_PI_CTRL2 0x1448 +#define USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x144C +#define USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x1450 +#define USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x1454 +#define USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x1458 +#define USB3_DP_QSERDES_RXA_AUX_CONTROL 0x145C +#define USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0x1460 +#define USB3_DP_QSERDES_RXA_RCLK_AUXDATA_SEL 0x1464 +#define USB3_DP_QSERDES_RXA_AC_JTAG_ENABLE 0x1468 +#define USB3_DP_QSERDES_RXA_AC_JTAG_INITP 0x146C +#define USB3_DP_QSERDES_RXA_AC_JTAG_INITN 0x1470 +#define USB3_DP_QSERDES_RXA_AC_JTAG_LVL 0x1474 +#define USB3_DP_QSERDES_RXA_AC_JTAG_MODE 0x1478 +#define USB3_DP_QSERDES_RXA_AC_JTAG_RESET 0x147C +#define USB3_DP_QSERDES_RXA_RX_TERM_BW 0x1480 +#define USB3_DP_QSERDES_RXA_RX_RCVR_IQ_EN 0x1484 +#define USB3_DP_QSERDES_RXA_RX_IDAC_I_DC_OFFSETS 0x1488 +#define USB3_DP_QSERDES_RXA_RX_IDAC_IBAR_DC_OFFSETS 0x148C +#define USB3_DP_QSERDES_RXA_RX_IDAC_Q_DC_OFFSETS 0x1490 +#define USB3_DP_QSERDES_RXA_RX_IDAC_QBAR_DC_OFFSETS 0x1494 +#define USB3_DP_QSERDES_RXA_RX_IDAC_A_DC_OFFSETS 0x1498 +#define USB3_DP_QSERDES_RXA_RX_IDAC_ABAR_DC_OFFSETS 0x149C +#define USB3_DP_QSERDES_RXA_RX_IDAC_EN 0x14A0 +#define USB3_DP_QSERDES_RXA_RX_IDAC_ENABLES 0x14A4 +#define USB3_DP_QSERDES_RXA_RX_IDAC_SIGN 0x14A8 +#define USB3_DP_QSERDES_RXA_RX_HIGHZ_HIGHRATE 0x14AC +#define USB3_DP_QSERDES_RXA_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x14B0 +#define USB3_DP_QSERDES_RXA_DFE_1 0x14B4 +#define USB3_DP_QSERDES_RXA_DFE_2 0x14B8 +#define USB3_DP_QSERDES_RXA_DFE_3 0x14BC +#define USB3_DP_QSERDES_RXA_DFE_4 0x14C0 +#define USB3_DP_QSERDES_RXA_TX_ADAPT_PRE_THRESH1 0x14C4 +#define USB3_DP_QSERDES_RXA_TX_ADAPT_PRE_THRESH2 0x14C8 +#define USB3_DP_QSERDES_RXA_TX_ADAPT_POST_THRESH 0x14CC +#define USB3_DP_QSERDES_RXA_TX_ADAPT_MAIN_THRESH 0x14D0 +#define USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x14D4 +#define USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x14D8 +#define USB3_DP_QSERDES_RXA_GM_CAL 0x14DC +#define USB3_DP_QSERDES_RXA_RX_VGA_GAIN2_LSB 0x14E0 +#define USB3_DP_QSERDES_RXA_RX_VGA_GAIN2_MSB 0x14E4 +#define USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL1 0x14E8 +#define USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x14EC +#define USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x14F0 +#define USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x14F4 +#define USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0x14F8 +#define USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x14FC +#define USB3_DP_QSERDES_RXA_RX_IDAC_MEASURE_TIME 0x1500 +#define USB3_DP_QSERDES_RXA_RX_IDAC_ACCUMULATOR 0x1504 +#define USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_LSB 0x1508 +#define USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_MSB 0x150C +#define USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1510 +#define USB3_DP_QSERDES_RXA_RX_OFFSET_ADAPTOR_CNTRL2 0x1514 +#define USB3_DP_QSERDES_RXA_SIGDET_ENABLES 0x1518 +#define USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x151C +#define USB3_DP_QSERDES_RXA_SIGDET_LVL 0x1520 +#define USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x1524 +#define USB3_DP_QSERDES_RXA_RX_BAND 0x1528 +#define USB3_DP_QSERDES_RXA_CDR_FREEZE_UP_DN 0x152C +#define USB3_DP_QSERDES_RXA_CDR_RESET_OVERRIDE 0x1530 +#define USB3_DP_QSERDES_RXA_RX_INTERFACE_MODE 0x1534 +#define USB3_DP_QSERDES_RXA_JITTER_GEN_MODE 0x1538 +#define USB3_DP_QSERDES_RXA_SJ_AMP1 0x153C +#define USB3_DP_QSERDES_RXA_SJ_AMP2 0x1540 +#define USB3_DP_QSERDES_RXA_SJ_PER1 0x1544 +#define USB3_DP_QSERDES_RXA_SJ_PER2 0x1548 +#define USB3_DP_QSERDES_RXA_PPM_OFFSET1 0x154C +#define USB3_DP_QSERDES_RXA_PPM_OFFSET2 0x1550 +#define USB3_DP_QSERDES_RXA_SIGN_PPM_PERIOD1 0x1554 +#define USB3_DP_QSERDES_RXA_SIGN_PPM_PERIOD2 0x1558 +#define USB3_DP_QSERDES_RXA_RX_PWM_ENABLE_AND_DATA 0x155C +#define USB3_DP_QSERDES_RXA_RX_PWM_GEAR1_TIMEOUT_COUNT 0x1560 +#define USB3_DP_QSERDES_RXA_RX_PWM_GEAR2_TIMEOUT_COUNT 0x1564 +#define USB3_DP_QSERDES_RXA_RX_PWM_GEAR3_TIMEOUT_COUNT 0x1568 +#define USB3_DP_QSERDES_RXA_RX_PWM_GEAR4_TIMEOUT_COUNT 0x156C +#define USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0x1570 +#define USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0x1574 +#define USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0x1578 +#define USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x157C +#define USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0x1580 +#define USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0x1584 +#define USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0x1588 +#define USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0x158C +#define USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x1590 +#define USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0x1594 +#define USB3_DP_QSERDES_RXA_RX_MODE_10_LOW 0x1598 +#define USB3_DP_QSERDES_RXA_RX_MODE_10_HIGH 0x159C +#define USB3_DP_QSERDES_RXA_RX_MODE_10_HIGH2 0x15A0 +#define USB3_DP_QSERDES_RXA_RX_MODE_10_HIGH3 0x15A4 +#define USB3_DP_QSERDES_RXA_RX_MODE_10_HIGH4 0x15A8 +#define USB3_DP_QSERDES_RXA_PHPRE_CTRL 0x15AC +#define USB3_DP_QSERDES_RXA_PHPRE_INITVAL 0x15B0 +#define USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x15B4 +#define USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x15B8 +#define USB3_DP_QSERDES_RXA_DCC_CTRL1 0x15BC +#define USB3_DP_QSERDES_RXA_DCC_CTRL2 0x15C0 +#define USB3_DP_QSERDES_RXA_VTH_CODE 0x15C4 +#define USB3_DP_QSERDES_RXA_VTH_MIN_THRESH 0x15C8 +#define USB3_DP_QSERDES_RXA_VTH_MAX_THRESH 0x15CC +#define USB3_DP_QSERDES_RXA_ALOG_OBSV_BUS_CTRL_1 0x15D0 +#define USB3_DP_QSERDES_RXA_PI_CTRL1 0x15D4 +#define USB3_DP_QSERDES_RXA_PI_CTRL2 0x15D8 +#define USB3_DP_QSERDES_RXA_PI_QUAD 0x15DC +#define USB3_DP_QSERDES_RXA_IDATA1 0x15E0 +#define USB3_DP_QSERDES_RXA_IDATA2 0x15E4 +#define USB3_DP_QSERDES_RXA_AUX_DATA1 0x15E8 +#define USB3_DP_QSERDES_RXA_AUX_DATA2 0x15EC +#define USB3_DP_QSERDES_RXA_AC_JTAG_OUTP 0x15F0 +#define USB3_DP_QSERDES_RXA_AC_JTAG_OUTN 0x15F4 +#define USB3_DP_QSERDES_RXA_RX_SIGDET 0x15F8 +#define USB3_DP_QSERDES_RXA_ALOG_OBSV_BUS_STATUS_1 0x15FC +#define USB3_DP_QSERDES_TXB_BIST_MODE_LANENO 0x1600 +#define USB3_DP_QSERDES_TXB_BIST_INVERT 0x1604 +#define USB3_DP_QSERDES_TXB_CLKBUF_ENABLE 0x1608 +#define USB3_DP_QSERDES_TXB_TX_EMP_POST1_LVL 0x160C +#define USB3_DP_QSERDES_TXB_TX_IDLE_LVL_LARGE_AMP 0x1610 +#define USB3_DP_QSERDES_TXB_TX_DRV_LVL 0x1614 +#define USB3_DP_QSERDES_TXB_TX_DRV_LVL_OFFSET 0x1618 +#define USB3_DP_QSERDES_TXB_RESET_TSYNC_EN 0x161C +#define USB3_DP_QSERDES_TXB_PRE_STALL_LDO_BOOST_EN 0x1620 +#define USB3_DP_QSERDES_TXB_TX_BAND 0x1624 +#define USB3_DP_QSERDES_TXB_SLEW_CNTL 0x1628 +#define USB3_DP_QSERDES_TXB_INTERFACE_SELECT 0x162C +#define USB3_DP_QSERDES_TXB_LPB_EN 0x1630 +#define USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x1634 +#define USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x1638 +#define USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x163C +#define USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x1640 +#define USB3_DP_QSERDES_TXB_PERL_LENGTH1 0x1644 +#define USB3_DP_QSERDES_TXB_PERL_LENGTH2 0x1648 +#define USB3_DP_QSERDES_TXB_SERDES_BYP_EN_OUT 0x164C +#define USB3_DP_QSERDES_TXB_DEBUG_BUS_SEL 0x1650 +#define USB3_DP_QSERDES_TXB_TRANSCEIVER_BIAS_EN 0x1654 +#define USB3_DP_QSERDES_TXB_HIGHZ_DRVR_EN 0x1658 +#define USB3_DP_QSERDES_TXB_TX_POL_INV 0x165C +#define USB3_DP_QSERDES_TXB_PARRATE_REC_DETECT_IDLE_EN 0x1660 +#define USB3_DP_QSERDES_TXB_BIST_PATTERN1 0x1664 +#define USB3_DP_QSERDES_TXB_BIST_PATTERN2 0x1668 +#define USB3_DP_QSERDES_TXB_BIST_PATTERN3 0x166C +#define USB3_DP_QSERDES_TXB_BIST_PATTERN4 0x1670 +#define USB3_DP_QSERDES_TXB_BIST_PATTERN5 0x1674 +#define USB3_DP_QSERDES_TXB_BIST_PATTERN6 0x1678 +#define USB3_DP_QSERDES_TXB_BIST_PATTERN7 0x167C +#define USB3_DP_QSERDES_TXB_BIST_PATTERN8 0x1680 +#define USB3_DP_QSERDES_TXB_LANE_MODE_1 0x1684 +#define USB3_DP_QSERDES_TXB_LANE_MODE_2 0x1688 +#define USB3_DP_QSERDES_TXB_LANE_MODE_3 0x168C +#define USB3_DP_QSERDES_TXB_ATB_SEL1 0x1690 +#define USB3_DP_QSERDES_TXB_ATB_SEL2 0x1694 +#define USB3_DP_QSERDES_TXB_RCV_DETECT_LVL 0x1698 +#define USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x169C +#define USB3_DP_QSERDES_TXB_PRBS_SEED1 0x16A0 +#define USB3_DP_QSERDES_TXB_PRBS_SEED2 0x16A4 +#define USB3_DP_QSERDES_TXB_PRBS_SEED3 0x16A8 +#define USB3_DP_QSERDES_TXB_PRBS_SEED4 0x16AC +#define USB3_DP_QSERDES_TXB_RESET_GEN 0x16B0 +#define USB3_DP_QSERDES_TXB_RESET_GEN_MUXES 0x16B4 +#define USB3_DP_QSERDES_TXB_TRAN_DRVR_EMP_EN 0x16B8 +#define USB3_DP_QSERDES_TXB_TX_INTERFACE_MODE 0x16BC +#define USB3_DP_QSERDES_TXB_PWM_CTRL 0x16C0 +#define USB3_DP_QSERDES_TXB_PWM_ENCODED_OR_DATA 0x16C4 +#define USB3_DP_QSERDES_TXB_PWM_GEAR_1_DIVIDER_BAND2 0x16C8 +#define USB3_DP_QSERDES_TXB_PWM_GEAR_2_DIVIDER_BAND2 0x16CC +#define USB3_DP_QSERDES_TXB_PWM_GEAR_3_DIVIDER_BAND2 0x16D0 +#define USB3_DP_QSERDES_TXB_PWM_GEAR_4_DIVIDER_BAND2 0x16D4 +#define USB3_DP_QSERDES_TXB_PWM_GEAR_1_DIVIDER_BAND0_1 0x16D8 +#define USB3_DP_QSERDES_TXB_PWM_GEAR_2_DIVIDER_BAND0_1 0x16DC +#define USB3_DP_QSERDES_TXB_PWM_GEAR_3_DIVIDER_BAND0_1 0x16E0 +#define USB3_DP_QSERDES_TXB_PWM_GEAR_4_DIVIDER_BAND0_1 0x16E4 +#define USB3_DP_QSERDES_TXB_VMODE_CTRL1 0x16E8 +#define USB3_DP_QSERDES_TXB_ALOG_OBSV_BUS_CTRL_1 0x16EC +#define USB3_DP_QSERDES_TXB_BIST_STATUS 0x16F0 +#define USB3_DP_QSERDES_TXB_BIST_ERROR_COUNT1 0x16F4 +#define USB3_DP_QSERDES_TXB_BIST_ERROR_COUNT2 0x16F8 +#define USB3_DP_QSERDES_TXB_ALOG_OBSV_BUS_STATUS_1 0x16FC +#define USB3_DP_QSERDES_TXB_LANE_DIG_CONFIG 0x1700 +#define USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x1704 +#define USB3_DP_QSERDES_TXB_PRE_EMPH 0x1708 +#define USB3_DP_QSERDES_TXB_SW_RESET 0x170C +#define USB3_DP_QSERDES_TXB_DIG_BKUP_CTRL 0x1710 +#define USB3_DP_QSERDES_TXB_DEBUG_BUS0 0x1714 +#define USB3_DP_QSERDES_TXB_DEBUG_BUS1 0x1718 +#define USB3_DP_QSERDES_TXB_DEBUG_BUS2 0x171C +#define USB3_DP_QSERDES_TXB_DEBUG_BUS3 0x1720 +#define USB3_DP_QSERDES_TXB_READ_EQCODE 0x1724 +#define USB3_DP_QSERDES_TXB_READ_OFFSETCODE 0x1728 +#define USB3_DP_QSERDES_TXB_IA_ERROR_COUNTER_LOW 0x172C +#define USB3_DP_QSERDES_TXB_IA_ERROR_COUNTER_HIGH 0x1730 +#define USB3_DP_QSERDES_TXB_VGA_READ_CODE 0x1734 +#define USB3_DP_QSERDES_TXB_VTH_READ_CODE 0x1738 +#define USB3_DP_QSERDES_TXB_DFE_TAP1_READ_CODE 0x173C +#define USB3_DP_QSERDES_TXB_DFE_TAP2_READ_CODE 0x1740 +#define USB3_DP_QSERDES_TXB_IDAC_STATUS_I 0x1744 +#define USB3_DP_QSERDES_TXB_IDAC_STATUS_IBAR 0x1748 +#define USB3_DP_QSERDES_TXB_IDAC_STATUS_Q 0x174C +#define USB3_DP_QSERDES_TXB_IDAC_STATUS_QBAR 0x1750 +#define USB3_DP_QSERDES_TXB_IDAC_STATUS_A 0x1754 +#define USB3_DP_QSERDES_TXB_IDAC_STATUS_ABAR 0x1758 +#define USB3_DP_QSERDES_TXB_IDAC_STATUS_SM_ON 0x175C +#define USB3_DP_QSERDES_TXB_IDAC_STATUS_CAL_DONE 0x1760 +#define USB3_DP_QSERDES_TXB_IDAC_STATUS_SIGNERROR 0x1764 +#define USB3_DP_QSERDES_TXB_DCC_CAL_STATUS 0x1768 +#define USB3_DP_QSERDES_RXB_UCDR_FO_GAIN_HALF 0x1800 +#define USB3_DP_QSERDES_RXB_UCDR_FO_GAIN_QUARTER 0x1804 +#define USB3_DP_QSERDES_RXB_UCDR_FO_GAIN 0x1808 +#define USB3_DP_QSERDES_RXB_UCDR_SO_GAIN_HALF 0x180C +#define USB3_DP_QSERDES_RXB_UCDR_SO_GAIN_QUARTER 0x1810 +#define USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x1814 +#define USB3_DP_QSERDES_RXB_UCDR_SVS_FO_GAIN_HALF 0x1818 +#define USB3_DP_QSERDES_RXB_UCDR_SVS_FO_GAIN_QUARTER 0x181C +#define USB3_DP_QSERDES_RXB_UCDR_SVS_FO_GAIN 0x1820 +#define USB3_DP_QSERDES_RXB_UCDR_SVS_SO_GAIN_HALF 0x1824 +#define USB3_DP_QSERDES_RXB_UCDR_SVS_SO_GAIN_QUARTER 0x1828 +#define USB3_DP_QSERDES_RXB_UCDR_SVS_SO_GAIN 0x182C +#define USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x1830 +#define USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x1834 +#define USB3_DP_QSERDES_RXB_UCDR_FO_TO_SO_DELAY 0x1838 +#define USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0x183C +#define USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x1840 +#define USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x1844 +#define USB3_DP_QSERDES_RXB_UCDR_PI_CTRL2 0x1848 +#define USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x184C +#define USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x1850 +#define USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x1854 +#define USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x1858 +#define USB3_DP_QSERDES_RXB_AUX_CONTROL 0x185C +#define USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0x1860 +#define USB3_DP_QSERDES_RXB_RCLK_AUXDATA_SEL 0x1864 +#define USB3_DP_QSERDES_RXB_AC_JTAG_ENABLE 0x1868 +#define USB3_DP_QSERDES_RXB_AC_JTAG_INITP 0x186C +#define USB3_DP_QSERDES_RXB_AC_JTAG_INITN 0x1870 +#define USB3_DP_QSERDES_RXB_AC_JTAG_LVL 0x1874 +#define USB3_DP_QSERDES_RXB_AC_JTAG_MODE 0x1878 +#define USB3_DP_QSERDES_RXB_AC_JTAG_RESET 0x187C +#define USB3_DP_QSERDES_RXB_RX_TERM_BW 0x1880 +#define USB3_DP_QSERDES_RXB_RX_RCVR_IQ_EN 0x1884 +#define USB3_DP_QSERDES_RXB_RX_IDAC_I_DC_OFFSETS 0x1888 +#define USB3_DP_QSERDES_RXB_RX_IDAC_IBAR_DC_OFFSETS 0x188C +#define USB3_DP_QSERDES_RXB_RX_IDAC_Q_DC_OFFSETS 0x1890 +#define USB3_DP_QSERDES_RXB_RX_IDAC_QBAR_DC_OFFSETS 0x1894 +#define USB3_DP_QSERDES_RXB_RX_IDAC_A_DC_OFFSETS 0x1898 +#define USB3_DP_QSERDES_RXB_RX_IDAC_ABAR_DC_OFFSETS 0x189C +#define USB3_DP_QSERDES_RXB_RX_IDAC_EN 0x18A0 +#define USB3_DP_QSERDES_RXB_RX_IDAC_ENABLES 0x18A4 +#define USB3_DP_QSERDES_RXB_RX_IDAC_SIGN 0x18A8 +#define USB3_DP_QSERDES_RXB_RX_HIGHZ_HIGHRATE 0x18AC +#define USB3_DP_QSERDES_RXB_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x18B0 +#define USB3_DP_QSERDES_RXB_DFE_1 0x18B4 +#define USB3_DP_QSERDES_RXB_DFE_2 0x18B8 +#define USB3_DP_QSERDES_RXB_DFE_3 0x18BC +#define USB3_DP_QSERDES_RXB_DFE_4 0x18C0 +#define USB3_DP_QSERDES_RXB_TX_ADAPT_PRE_THRESH1 0x18C4 +#define USB3_DP_QSERDES_RXB_TX_ADAPT_PRE_THRESH2 0x18C8 +#define USB3_DP_QSERDES_RXB_TX_ADAPT_POST_THRESH 0x18CC +#define USB3_DP_QSERDES_RXB_TX_ADAPT_MAIN_THRESH 0x18D0 +#define USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x18D4 +#define USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x18D8 +#define USB3_DP_QSERDES_RXB_GM_CAL 0x18DC +#define USB3_DP_QSERDES_RXB_RX_VGA_GAIN2_LSB 0x18E0 +#define USB3_DP_QSERDES_RXB_RX_VGA_GAIN2_MSB 0x18E4 +#define USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL1 0x18E8 +#define USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x18EC +#define USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x18F0 +#define USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x18F4 +#define USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0x18F8 +#define USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x18FC +#define USB3_DP_QSERDES_RXB_RX_IDAC_MEASURE_TIME 0x1900 +#define USB3_DP_QSERDES_RXB_RX_IDAC_ACCUMULATOR 0x1904 +#define USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_LSB 0x1908 +#define USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_MSB 0x190C +#define USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1910 +#define USB3_DP_QSERDES_RXB_RX_OFFSET_ADAPTOR_CNTRL2 0x1914 +#define USB3_DP_QSERDES_RXB_SIGDET_ENABLES 0x1918 +#define USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x191C +#define USB3_DP_QSERDES_RXB_SIGDET_LVL 0x1920 +#define USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x1924 +#define USB3_DP_QSERDES_RXB_RX_BAND 0x1928 +#define USB3_DP_QSERDES_RXB_CDR_FREEZE_UP_DN 0x192C +#define USB3_DP_QSERDES_RXB_CDR_RESET_OVERRIDE 0x1930 +#define USB3_DP_QSERDES_RXB_RX_INTERFACE_MODE 0x1934 +#define USB3_DP_QSERDES_RXB_JITTER_GEN_MODE 0x1938 +#define USB3_DP_QSERDES_RXB_SJ_AMP1 0x193C +#define USB3_DP_QSERDES_RXB_SJ_AMP2 0x1940 +#define USB3_DP_QSERDES_RXB_SJ_PER1 0x1944 +#define USB3_DP_QSERDES_RXB_SJ_PER2 0x1948 +#define USB3_DP_QSERDES_RXB_PPM_OFFSET1 0x194C +#define USB3_DP_QSERDES_RXB_PPM_OFFSET2 0x1950 +#define USB3_DP_QSERDES_RXB_SIGN_PPM_PERIOD1 0x1954 +#define USB3_DP_QSERDES_RXB_SIGN_PPM_PERIOD2 0x1958 +#define USB3_DP_QSERDES_RXB_RX_PWM_ENABLE_AND_DATA 0x195C +#define USB3_DP_QSERDES_RXB_RX_PWM_GEAR1_TIMEOUT_COUNT 0x1960 +#define USB3_DP_QSERDES_RXB_RX_PWM_GEAR2_TIMEOUT_COUNT 0x1964 +#define USB3_DP_QSERDES_RXB_RX_PWM_GEAR3_TIMEOUT_COUNT 0x1968 +#define USB3_DP_QSERDES_RXB_RX_PWM_GEAR4_TIMEOUT_COUNT 0x196C +#define USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0x1970 +#define USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0x1974 +#define USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0x1978 +#define USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x197C +#define USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0x1980 +#define USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0x1984 +#define USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0x1988 +#define USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0x198C +#define USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x1990 +#define USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0x1994 +#define USB3_DP_QSERDES_RXB_RX_MODE_10_LOW 0x1998 +#define USB3_DP_QSERDES_RXB_RX_MODE_10_HIGH 0x199C +#define USB3_DP_QSERDES_RXB_RX_MODE_10_HIGH2 0x19A0 +#define USB3_DP_QSERDES_RXB_RX_MODE_10_HIGH3 0x19A4 +#define USB3_DP_QSERDES_RXB_RX_MODE_10_HIGH4 0x19A8 +#define USB3_DP_QSERDES_RXB_PHPRE_CTRL 0x19AC +#define USB3_DP_QSERDES_RXB_PHPRE_INITVAL 0x19B0 +#define USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x19B4 +#define USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x19B8 +#define USB3_DP_QSERDES_RXB_DCC_CTRL1 0x19BC +#define USB3_DP_QSERDES_RXB_DCC_CTRL2 0x19C0 +#define USB3_DP_QSERDES_RXB_VTH_CODE 0x19C4 +#define USB3_DP_QSERDES_RXB_VTH_MIN_THRESH 0x19C8 +#define USB3_DP_QSERDES_RXB_VTH_MAX_THRESH 0x19CC +#define USB3_DP_QSERDES_RXB_ALOG_OBSV_BUS_CTRL_1 0x19D0 +#define USB3_DP_QSERDES_RXB_PI_CTRL1 0x19D4 +#define USB3_DP_QSERDES_RXB_PI_CTRL2 0x19D8 +#define USB3_DP_QSERDES_RXB_PI_QUAD 0x19DC +#define USB3_DP_QSERDES_RXB_IDATA1 0x19E0 +#define USB3_DP_QSERDES_RXB_IDATA2 0x19E4 +#define USB3_DP_QSERDES_RXB_AUX_DATA1 0x19E8 +#define USB3_DP_QSERDES_RXB_AUX_DATA2 0x19EC +#define USB3_DP_QSERDES_RXB_AC_JTAG_OUTP 0x19F0 +#define USB3_DP_QSERDES_RXB_AC_JTAG_OUTN 0x19F4 +#define USB3_DP_QSERDES_RXB_RX_SIGDET 0x19F8 +#define USB3_DP_QSERDES_RXB_ALOG_OBSV_BUS_STATUS_1 0x19FC +#define USB3_DP_PCS_MISC_TYPEC_CTRL 0x1A00 +#define USB3_DP_PCS_MISC_TYPEC_PWRDN_CTRL 0x1A04 +#define USB3_DP_PCS_MISC_PCS_MISC_CONFIG1 0x1A08 +#define USB3_DP_PCS_MISC_CLAMP_ENABLE 0x1A0C +#define USB3_DP_PCS_MISC_TYPEC_STATUS 0x1A10 +#define USB3_DP_PCS_MISC_PLACEHOLDER_STATUS 0x1A14 +#define USB3_DP_PCS_LN_PCS_STATUS1 0x1B00 +#define USB3_DP_PCS_LN_PCS_STATUS2 0x1B04 +#define USB3_DP_PCS_LN_PCS_STATUS2_CLEAR 0x1B08 +#define USB3_DP_PCS_LN_PCS_STATUS3 0x1B0C +#define USB3_DP_PCS_LN_BIST_CHK_ERR_CNT_L_STATUS 0x1B10 +#define USB3_DP_PCS_LN_BIST_CHK_ERR_CNT_H_STATUS 0x1B14 +#define USB3_DP_PCS_LN_BIST_CHK_STATUS 0x1B18 +#define USB3_DP_PCS_LN_INSIG_SW_CTRL1 0x1B1C +#define USB3_DP_PCS_LN_INSIG_MX_CTRL1 0x1B20 +#define USB3_DP_PCS_LN_OUTSIG_SW_CTRL1 0x1B24 +#define USB3_DP_PCS_LN_OUTSIG_MX_CTRL1 0x1B28 +#define USB3_DP_PCS_LN_TEST_CONTROL 0x1B2C +#define USB3_DP_PCS_LN_BIST_CTRL 0x1B30 +#define USB3_DP_PCS_LN_PRBS_SEED0 0x1B34 +#define USB3_DP_PCS_LN_PRBS_SEED1 0x1B38 +#define USB3_DP_PCS_LN_FIXED_PAT_CTRL 0x1B3C +#define USB3_DP_PCS_SW_RESET 0x1C00 +#define USB3_DP_PCS_REVISION_ID0 0x1C04 +#define USB3_DP_PCS_REVISION_ID1 0x1C08 +#define USB3_DP_PCS_REVISION_ID2 0x1C0C +#define USB3_DP_PCS_REVISION_ID3 0x1C10 +#define USB3_DP_PCS_PCS_STATUS1 0x1C14 +#define USB3_DP_PCS_PCS_STATUS2 0x1C18 +#define USB3_DP_PCS_PCS_STATUS3 0x1C1C +#define USB3_DP_PCS_PCS_STATUS4 0x1C20 +#define USB3_DP_PCS_PCS_STATUS5 0x1C24 +#define USB3_DP_PCS_PCS_STATUS6 0x1C28 +#define USB3_DP_PCS_PCS_STATUS7 0x1C2C +#define USB3_DP_PCS_DEBUG_BUS_0_STATUS 0x1C30 +#define USB3_DP_PCS_DEBUG_BUS_1_STATUS 0x1C34 +#define USB3_DP_PCS_DEBUG_BUS_2_STATUS 0x1C38 +#define USB3_DP_PCS_DEBUG_BUS_3_STATUS 0x1C3C +#define USB3_DP_PCS_POWER_DOWN_CONTROL 0x1C40 +#define USB3_DP_PCS_START_CONTROL 0x1C44 +#define USB3_DP_PCS_INSIG_SW_CTRL1 0x1C48 +#define USB3_DP_PCS_INSIG_SW_CTRL2 0x1C4C +#define USB3_DP_PCS_INSIG_SW_CTRL3 0x1C50 +#define USB3_DP_PCS_INSIG_SW_CTRL4 0x1C54 +#define USB3_DP_PCS_INSIG_SW_CTRL5 0x1C58 +#define USB3_DP_PCS_INSIG_SW_CTRL6 0x1C5C +#define USB3_DP_PCS_INSIG_SW_CTRL7 0x1C60 +#define USB3_DP_PCS_INSIG_SW_CTRL8 0x1C64 +#define USB3_DP_PCS_INSIG_MX_CTRL1 0x1C68 +#define USB3_DP_PCS_INSIG_MX_CTRL2 0x1C6C +#define USB3_DP_PCS_INSIG_MX_CTRL3 0x1C70 +#define USB3_DP_PCS_INSIG_MX_CTRL4 0x1C74 +#define USB3_DP_PCS_INSIG_MX_CTRL5 0x1C78 +#define USB3_DP_PCS_INSIG_MX_CTRL7 0x1C7C +#define USB3_DP_PCS_INSIG_MX_CTRL8 0x1C80 +#define USB3_DP_PCS_OUTSIG_SW_CTRL1 0x1C84 +#define USB3_DP_PCS_OUTSIG_MX_CTRL1 0x1C88 +#define USB3_DP_PCS_CLAMP_ENABLE 0x1C8C +#define USB3_DP_PCS_POWER_STATE_CONFIG1 0x1C90 +#define USB3_DP_PCS_POWER_STATE_CONFIG2 0x1C94 +#define USB3_DP_PCS_FLL_CNTRL1 0x1C98 +#define USB3_DP_PCS_FLL_CNTRL2 0x1C9C +#define USB3_DP_PCS_FLL_CNT_VAL_L 0x1CA0 +#define USB3_DP_PCS_FLL_CNT_VAL_H_TOL 0x1CA4 +#define USB3_DP_PCS_FLL_MAN_CODE 0x1CA8 +#define USB3_DP_PCS_TEST_CONTROL1 0x1CAC +#define USB3_DP_PCS_TEST_CONTROL2 0x1CB0 +#define USB3_DP_PCS_TEST_CONTROL3 0x1CB4 +#define USB3_DP_PCS_TEST_CONTROL4 0x1CB8 +#define USB3_DP_PCS_TEST_CONTROL5 0x1CBC +#define USB3_DP_PCS_TEST_CONTROL6 0x1CC0 +#define USB3_DP_PCS_LOCK_DETECT_CONFIG1 0x1CC4 +#define USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x1CC8 +#define USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x1CCC +#define USB3_DP_PCS_LOCK_DETECT_CONFIG4 0x1CD0 +#define USB3_DP_PCS_LOCK_DETECT_CONFIG5 0x1CD4 +#define USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x1CD8 +#define USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x1CDC +#define USB3_DP_PCS_REFGEN_REQ_CONFIG2 0x1CE0 +#define USB3_DP_PCS_REFGEN_REQ_CONFIG3 0x1CE4 +#define USB3_DP_PCS_BIST_CTRL 0x1CE8 +#define USB3_DP_PCS_PRBS_POLY0 0x1CEC +#define USB3_DP_PCS_PRBS_POLY1 0x1CF0 +#define USB3_DP_PCS_FIXED_PAT0 0x1CF4 +#define USB3_DP_PCS_FIXED_PAT1 0x1CF8 +#define USB3_DP_PCS_FIXED_PAT2 0x1CFC +#define USB3_DP_PCS_FIXED_PAT3 0x1D00 +#define USB3_DP_PCS_FIXED_PAT4 0x1D04 +#define USB3_DP_PCS_FIXED_PAT5 0x1D08 +#define USB3_DP_PCS_FIXED_PAT6 0x1D0C +#define USB3_DP_PCS_FIXED_PAT7 0x1D10 +#define USB3_DP_PCS_FIXED_PAT8 0x1D14 +#define USB3_DP_PCS_FIXED_PAT9 0x1D18 +#define USB3_DP_PCS_FIXED_PAT10 0x1D1C +#define USB3_DP_PCS_FIXED_PAT11 0x1D20 +#define USB3_DP_PCS_FIXED_PAT12 0x1D24 +#define USB3_DP_PCS_FIXED_PAT13 0x1D28 +#define USB3_DP_PCS_FIXED_PAT14 0x1D2C +#define USB3_DP_PCS_FIXED_PAT15 0x1D30 +#define USB3_DP_PCS_TXMGN_CONFIG 0x1D34 +#define USB3_DP_PCS_G12S1_TXMGN_V0 0x1D38 +#define USB3_DP_PCS_G12S1_TXMGN_V1 0x1D3C +#define USB3_DP_PCS_G12S1_TXMGN_V2 0x1D40 +#define USB3_DP_PCS_G12S1_TXMGN_V3 0x1D44 +#define USB3_DP_PCS_G12S1_TXMGN_V4 0x1D48 +#define USB3_DP_PCS_G12S1_TXMGN_V0_RS 0x1D4C +#define USB3_DP_PCS_G12S1_TXMGN_V1_RS 0x1D50 +#define USB3_DP_PCS_G12S1_TXMGN_V2_RS 0x1D54 +#define USB3_DP_PCS_G12S1_TXMGN_V3_RS 0x1D58 +#define USB3_DP_PCS_G12S1_TXMGN_V4_RS 0x1D5C +#define USB3_DP_PCS_G3S2_TXMGN_MAIN 0x1D60 +#define USB3_DP_PCS_G3S2_TXMGN_MAIN_RS 0x1D64 +#define USB3_DP_PCS_G12S1_TXDEEMPH_M6DB 0x1D68 +#define USB3_DP_PCS_G12S1_TXDEEMPH_M3P5DB 0x1D6C +#define USB3_DP_PCS_G3S2_PRE_GAIN 0x1D70 +#define USB3_DP_PCS_G3S2_POST_GAIN 0x1D74 +#define USB3_DP_PCS_G3S2_PRE_POST_OFFSET 0x1D78 +#define USB3_DP_PCS_G3S2_PRE_GAIN_RS 0x1D7C +#define USB3_DP_PCS_G3S2_POST_GAIN_RS 0x1D80 +#define USB3_DP_PCS_G3S2_PRE_POST_OFFSET_RS 0x1D84 +#define USB3_DP_PCS_RX_SIGDET_LVL 0x1D88 +#define USB3_DP_PCS_RX_SIGDET_DTCT_CNTRL 0x1D8C +#define USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_L 0x1D90 +#define USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_H 0x1D94 +#define USB3_DP_PCS_RATE_SLEW_CNTRL1 0x1D98 +#define USB3_DP_PCS_RATE_SLEW_CNTRL2 0x1D9C +#define USB3_DP_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1DA0 +#define USB3_DP_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1DA4 +#define USB3_DP_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1DA8 +#define USB3_DP_PCS_TSYNC_RSYNC_TIME 0x1DAC +#define USB3_DP_PCS_CDR_RESET_TIME 0x1DB0 +#define USB3_DP_PCS_TSYNC_DLY_TIME 0x1DB4 +#define USB3_DP_PCS_ELECIDLE_DLY_SEL 0x1DB8 +#define USB3_DP_PCS_CMN_ACK_OUT_SEL 0x1DBC +#define USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x1DC0 +#define USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x1DC4 +#define USB3_DP_PCS_ALIGN_DETECT_CONFIG3 0x1DC8 +#define USB3_DP_PCS_ALIGN_DETECT_CONFIG4 0x1DCC +#define USB3_DP_PCS_PCS_TX_RX_CONFIG 0x1DD0 +#define USB3_DP_PCS_RX_IDLE_DTCT_CNTRL 0x1DD4 +#define USB3_DP_PCS_RX_DCC_CAL_CONFIG 0x1DD8 +#define USB3_DP_PCS_EQ_CONFIG1 0x1DDC +#define USB3_DP_PCS_EQ_CONFIG2 0x1DE0 +#define USB3_DP_PCS_EQ_CONFIG3 0x1DE4 +#define USB3_DP_PCS_EQ_CONFIG4 0x1DE8 +#define USB3_DP_PCS_EQ_CONFIG5 0x1DEC +#define USB3_DP_PCS_USB3_POWER_STATE_CONFIG1 0x1F00 +#define USB3_DP_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x1F04 +#define USB3_DP_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x1F08 +#define USB3_DP_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x1F0C +#define USB3_DP_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x1F10 +#define USB3_DP_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x1F14 +#define USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x1F18 +#define USB3_DP_PCS_USB3_LFPS_TX_ECSTART 0x1F1C +#define USB3_DP_PCS_USB3_LFPS_PER_TIMER_VAL 0x1F20 +#define USB3_DP_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x1F24 +#define USB3_DP_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x1F28 +#define USB3_DP_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x1F2C +#define USB3_DP_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x1F30 +#define USB3_DP_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x1F34 +#define USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x1F38 +#define USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x1F3C +#define USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x1F40 +#define USB3_DP_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x1F44 +#define USB3_DP_PCS_USB3_ARCVR_DTCT_CM_DLY 0x1F48 +#define USB3_DP_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x1F4C +#define USB3_DP_PCS_USB3_ALFPS_DEGLITCH_VAL 0x1F50 +#define USB3_DP_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x1F54 +#define USB3_DP_PCS_USB3_TEST_CONTROL 0x1F58 +#define USB3_DP_QSERDES_RXA_AUX_DATA_TCOURSE_TFINE 0x1F5C +#define USB3_DP_QSERDES_RXB_AUX_DATA_TCOURSE_TFINE 0x1F60 + +/* USB3 Uni PHY register offsets */ +#define USB3_UNI_QSERDES_COM_ATB_SEL1 0x0000 +#define USB3_UNI_QSERDES_COM_ATB_SEL2 0x0004 +#define USB3_UNI_QSERDES_COM_FREQ_UPDATE 0x0008 +#define USB3_UNI_QSERDES_COM_BG_TIMER 0x000C +#define USB3_UNI_QSERDES_COM_SSC_EN_CENTER 0x0010 +#define USB3_UNI_QSERDES_COM_SSC_ADJ_PER1 0x0014 +#define USB3_UNI_QSERDES_COM_SSC_ADJ_PER2 0x0018 +#define USB3_UNI_QSERDES_COM_SSC_PER1 0x001C +#define USB3_UNI_QSERDES_COM_SSC_PER2 0x0020 +#define USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0x0024 +#define USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x0028 +#define USB3_UNI_QSERDES_COM_SSC_STEP_SIZE3_MODE0 0x002C +#define USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0x0030 +#define USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x0034 +#define USB3_UNI_QSERDES_COM_SSC_STEP_SIZE3_MODE1 0x0038 +#define USB3_UNI_QSERDES_COM_POST_DIV 0x003C +#define USB3_UNI_QSERDES_COM_POST_DIV_MUX 0x0040 +#define USB3_UNI_QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x0044 +#define USB3_UNI_QSERDES_COM_CLK_ENABLE1 0x0048 +#define USB3_UNI_QSERDES_COM_SYS_CLK_CTRL 0x004C +#define USB3_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0050 +#define USB3_UNI_QSERDES_COM_PLL_EN 0x0054 +#define USB3_UNI_QSERDES_COM_PLL_IVCO 0x0058 +#define USB3_UNI_QSERDES_COM_CMN_IETRIM 0x005C +#define USB3_UNI_QSERDES_COM_CMN_IPTRIM 0x0060 +#define USB3_UNI_QSERDES_COM_EP_CLOCK_DETECT_CTRL 0x0064 +#define USB3_UNI_QSERDES_COM_SYSCLK_DET_COMP_STATUS 0x0068 +#define USB3_UNI_QSERDES_COM_CLK_EP_DIV_MODE0 0x006C +#define USB3_UNI_QSERDES_COM_CLK_EP_DIV_MODE1 0x0070 +#define USB3_UNI_QSERDES_COM_CP_CTRL_MODE0 0x0074 +#define USB3_UNI_QSERDES_COM_CP_CTRL_MODE1 0x0078 +#define USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE0 0x007C +#define USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE1 0x0080 +#define USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE0 0x0084 +#define USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1 0x0088 +#define USB3_UNI_QSERDES_COM_PLL_CNTRL 0x008C +#define USB3_UNI_QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x0090 +#define USB3_UNI_QSERDES_COM_SYSCLK_EN_SEL 0x0094 +#define USB3_UNI_QSERDES_COM_CML_SYSCLK_SEL 0x0098 +#define USB3_UNI_QSERDES_COM_RESETSM_CNTRL 0x009C +#define USB3_UNI_QSERDES_COM_RESETSM_CNTRL2 0x00A0 +#define USB3_UNI_QSERDES_COM_LOCK_CMP_EN 0x00A4 +#define USB3_UNI_QSERDES_COM_LOCK_CMP_CFG 0x00A8 +#define USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE0 0x00AC +#define USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE0 0x00B0 +#define USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE1 0x00B4 +#define USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE1 0x00B8 +#define USB3_UNI_QSERDES_COM_DEC_START_MODE0 0x00BC +#define USB3_UNI_QSERDES_COM_DEC_START_MSB_MODE0 0x00C0 +#define USB3_UNI_QSERDES_COM_DEC_START_MODE1 0x00C4 +#define USB3_UNI_QSERDES_COM_DEC_START_MSB_MODE1 0x00C8 +#define USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0 0x00CC +#define USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0 0x00D0 +#define USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0 0x00D4 +#define USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1 0x00D8 +#define USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1 0x00DC +#define USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1 0x00E0 +#define USB3_UNI_QSERDES_COM_INTEGLOOP_INITVAL 0x00E4 +#define USB3_UNI_QSERDES_COM_INTEGLOOP_EN 0x00E8 +#define USB3_UNI_QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x00EC +#define USB3_UNI_QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x00F0 +#define USB3_UNI_QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x00F4 +#define USB3_UNI_QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x00F8 +#define USB3_UNI_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0 0x00FC +#define USB3_UNI_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1 0x0100 +#define USB3_UNI_QSERDES_COM_VCOCAL_DEADMAN_CTRL 0x0104 +#define USB3_UNI_QSERDES_COM_VCO_TUNE_CTRL 0x0108 +#define USB3_UNI_QSERDES_COM_VCO_TUNE_MAP 0x010C +#define USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE0 0x0110 +#define USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE0 0x0114 +#define USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE1 0x0118 +#define USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE1 0x011C +#define USB3_UNI_QSERDES_COM_VCO_TUNE_INITVAL1 0x0120 +#define USB3_UNI_QSERDES_COM_VCO_TUNE_INITVAL2 0x0124 +#define USB3_UNI_QSERDES_COM_VCO_TUNE_MINVAL1 0x0128 +#define USB3_UNI_QSERDES_COM_VCO_TUNE_MINVAL2 0x012C +#define USB3_UNI_QSERDES_COM_VCO_TUNE_MAXVAL1 0x0130 +#define USB3_UNI_QSERDES_COM_VCO_TUNE_MAXVAL2 0x0134 +#define USB3_UNI_QSERDES_COM_VCO_TUNE_TIMER1 0x0138 +#define USB3_UNI_QSERDES_COM_VCO_TUNE_TIMER2 0x013C +#define USB3_UNI_QSERDES_COM_CMN_STATUS 0x0140 +#define USB3_UNI_QSERDES_COM_RESET_SM_STATUS 0x0144 +#define USB3_UNI_QSERDES_COM_RESTRIM_CODE_STATUS 0x0148 +#define USB3_UNI_QSERDES_COM_PLLCAL_CODE1_STATUS 0x014C +#define USB3_UNI_QSERDES_COM_PLLCAL_CODE2_STATUS 0x0150 +#define USB3_UNI_QSERDES_COM_CLK_SELECT 0x0154 +#define USB3_UNI_QSERDES_COM_HSCLK_SEL 0x0158 +#define USB3_UNI_QSERDES_COM_HSCLK_HS_SWITCH_SEL 0x015C +#define USB3_UNI_QSERDES_COM_INTEGLOOP_BINCODE_STATUS 0x0160 +#define USB3_UNI_QSERDES_COM_PLL_ANALOG 0x0164 +#define USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE0 0x0168 +#define USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE1 0x016C +#define USB3_UNI_QSERDES_COM_SW_RESET 0x0170 +#define USB3_UNI_QSERDES_COM_CORE_CLK_EN 0x0174 +#define USB3_UNI_QSERDES_COM_C_READY_STATUS 0x0178 +#define USB3_UNI_QSERDES_COM_CMN_CONFIG 0x017C +#define USB3_UNI_QSERDES_COM_CMN_RATE_OVERRIDE 0x0180 +#define USB3_UNI_QSERDES_COM_SVS_MODE_CLK_SEL 0x0184 +#define USB3_UNI_QSERDES_COM_DEBUG_BUS0 0x0188 +#define USB3_UNI_QSERDES_COM_DEBUG_BUS1 0x018C +#define USB3_UNI_QSERDES_COM_DEBUG_BUS2 0x0190 +#define USB3_UNI_QSERDES_COM_DEBUG_BUS3 0x0194 +#define USB3_UNI_QSERDES_COM_DEBUG_BUS_SEL 0x0198 +#define USB3_UNI_QSERDES_COM_CMN_MISC1 0x019C +#define USB3_UNI_QSERDES_COM_CMN_MISC2 0x01A0 +#define USB3_UNI_QSERDES_COM_CMN_MODE 0x01A4 +#define USB3_UNI_QSERDES_COM_VCO_DC_LEVEL_CTRL 0x01A8 +#define USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x01AC +#define USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x01B0 +#define USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x01B4 +#define USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x01B8 +#define USB3_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x01BC +#define USB3_UNI_QSERDES_TX_BIST_MODE_LANENO 0x0200 +#define USB3_UNI_QSERDES_TX_BIST_INVERT 0x0204 +#define USB3_UNI_QSERDES_TX_CLKBUF_ENABLE 0x0208 +#define USB3_UNI_QSERDES_TX_TX_EMP_POST1_LVL 0x020C +#define USB3_UNI_QSERDES_TX_TX_IDLE_LVL_LARGE_AMP 0x0210 +#define USB3_UNI_QSERDES_TX_TX_DRV_LVL 0x0214 +#define USB3_UNI_QSERDES_TX_TX_DRV_LVL_OFFSET 0x0218 +#define USB3_UNI_QSERDES_TX_RESET_TSYNC_EN 0x021C +#define USB3_UNI_QSERDES_TX_PRE_STALL_LDO_BOOST_EN 0x0220 +#define USB3_UNI_QSERDES_TX_TX_BAND 0x0224 +#define USB3_UNI_QSERDES_TX_SLEW_CNTL 0x0228 +#define USB3_UNI_QSERDES_TX_INTERFACE_SELECT 0x022C +#define USB3_UNI_QSERDES_TX_LPB_EN 0x0230 +#define USB3_UNI_QSERDES_TX_RES_CODE_LANE_TX 0x0234 +#define USB3_UNI_QSERDES_TX_RES_CODE_LANE_RX 0x0238 +#define USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x023C +#define USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX 0x0240 +#define USB3_UNI_QSERDES_TX_PERL_LENGTH1 0x0244 +#define USB3_UNI_QSERDES_TX_PERL_LENGTH2 0x0248 +#define USB3_UNI_QSERDES_TX_SERDES_BYP_EN_OUT 0x024C +#define USB3_UNI_QSERDES_TX_DEBUG_BUS_SEL 0x0250 +#define USB3_UNI_QSERDES_TX_TRANSCEIVER_BIAS_EN 0x0254 +#define USB3_UNI_QSERDES_TX_HIGHZ_DRVR_EN 0x0258 +#define USB3_UNI_QSERDES_TX_TX_POL_INV 0x025C +#define USB3_UNI_QSERDES_TX_PARRATE_REC_DETECT_IDLE_EN 0x0260 +#define USB3_UNI_QSERDES_TX_BIST_PATTERN1 0x0264 +#define USB3_UNI_QSERDES_TX_BIST_PATTERN2 0x0268 +#define USB3_UNI_QSERDES_TX_BIST_PATTERN3 0x026C +#define USB3_UNI_QSERDES_TX_BIST_PATTERN4 0x0270 +#define USB3_UNI_QSERDES_TX_BIST_PATTERN5 0x0274 +#define USB3_UNI_QSERDES_TX_BIST_PATTERN6 0x0278 +#define USB3_UNI_QSERDES_TX_BIST_PATTERN7 0x027C +#define USB3_UNI_QSERDES_TX_BIST_PATTERN8 0x0280 +#define USB3_UNI_QSERDES_TX_LANE_MODE_1 0x0284 +#define USB3_UNI_QSERDES_TX_LANE_MODE_2 0x0288 +#define USB3_UNI_QSERDES_TX_LANE_MODE_3 0x028C +#define USB3_UNI_QSERDES_TX_ATB_SEL1 0x0290 +#define USB3_UNI_QSERDES_TX_ATB_SEL2 0x0294 +#define USB3_UNI_QSERDES_TX_RCV_DETECT_LVL 0x0298 +#define USB3_UNI_QSERDES_TX_RCV_DETECT_LVL_2 0x029C +#define USB3_UNI_QSERDES_TX_PRBS_SEED1 0x02A0 +#define USB3_UNI_QSERDES_TX_PRBS_SEED2 0x02A4 +#define USB3_UNI_QSERDES_TX_PRBS_SEED3 0x02A8 +#define USB3_UNI_QSERDES_TX_PRBS_SEED4 0x02AC +#define USB3_UNI_QSERDES_TX_RESET_GEN 0x02B0 +#define USB3_UNI_QSERDES_TX_RESET_GEN_MUXES 0x02B4 +#define USB3_UNI_QSERDES_TX_TRAN_DRVR_EMP_EN 0x02B8 +#define USB3_UNI_QSERDES_TX_TX_INTERFACE_MODE 0x02BC +#define USB3_UNI_QSERDES_TX_PWM_CTRL 0x02C0 +#define USB3_UNI_QSERDES_TX_PWM_ENCODED_OR_DATA 0x02C4 +#define USB3_UNI_QSERDES_TX_PWM_GEAR_1_DIVIDER_BAND2 0x02C8 +#define USB3_UNI_QSERDES_TX_PWM_GEAR_2_DIVIDER_BAND2 0x02CC +#define USB3_UNI_QSERDES_TX_PWM_GEAR_3_DIVIDER_BAND2 0x02D0 +#define USB3_UNI_QSERDES_TX_PWM_GEAR_4_DIVIDER_BAND2 0x02D4 +#define USB3_UNI_QSERDES_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x02D8 +#define USB3_UNI_QSERDES_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x02DC +#define USB3_UNI_QSERDES_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x02E0 +#define USB3_UNI_QSERDES_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x02E4 +#define USB3_UNI_QSERDES_TX_VMODE_CTRL1 0x02E8 +#define USB3_UNI_QSERDES_TX_ALOG_OBSV_BUS_CTRL_1 0x02EC +#define USB3_UNI_QSERDES_TX_BIST_STATUS 0x02F0 +#define USB3_UNI_QSERDES_TX_BIST_ERROR_COUNT1 0x02F4 +#define USB3_UNI_QSERDES_TX_BIST_ERROR_COUNT2 0x02F8 +#define USB3_UNI_QSERDES_TX_ALOG_OBSV_BUS_STATUS_1 0x02FC +#define USB3_UNI_QSERDES_TX_LANE_DIG_CONFIG 0x0300 +#define USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x0304 +#define USB3_UNI_QSERDES_TX_PRE_EMPH 0x0308 +#define USB3_UNI_QSERDES_TX_SW_RESET 0x030C +#define USB3_UNI_QSERDES_TX_DIG_BKUP_CTRL 0x0310 +#define USB3_UNI_QSERDES_TX_DEBUG_BUS0 0x0314 +#define USB3_UNI_QSERDES_TX_DEBUG_BUS1 0x0318 +#define USB3_UNI_QSERDES_TX_DEBUG_BUS2 0x031C +#define USB3_UNI_QSERDES_TX_DEBUG_BUS3 0x0320 +#define USB3_UNI_QSERDES_TX_READ_EQCODE 0x0324 +#define USB3_UNI_QSERDES_TX_READ_OFFSETCODE 0x0328 +#define USB3_UNI_QSERDES_TX_IA_ERROR_COUNTER_LOW 0x032C +#define USB3_UNI_QSERDES_TX_IA_ERROR_COUNTER_HIGH 0x0330 +#define USB3_UNI_QSERDES_TX_VGA_READ_CODE 0x0334 +#define USB3_UNI_QSERDES_TX_VTH_READ_CODE 0x0338 +#define USB3_UNI_QSERDES_TX_DFE_TAP1_READ_CODE 0x033C +#define USB3_UNI_QSERDES_TX_DFE_TAP2_READ_CODE 0x0340 +#define USB3_UNI_QSERDES_TX_IDAC_STATUS_I 0x0344 +#define USB3_UNI_QSERDES_TX_IDAC_STATUS_IBAR 0x0348 +#define USB3_UNI_QSERDES_TX_IDAC_STATUS_Q 0x034C +#define USB3_UNI_QSERDES_TX_IDAC_STATUS_QBAR 0x0350 +#define USB3_UNI_QSERDES_TX_IDAC_STATUS_A 0x0354 +#define USB3_UNI_QSERDES_TX_IDAC_STATUS_ABAR 0x0358 +#define USB3_UNI_QSERDES_TX_IDAC_STATUS_SM_ON 0x035C +#define USB3_UNI_QSERDES_TX_IDAC_STATUS_CAL_DONE 0x0360 +#define USB3_UNI_QSERDES_TX_IDAC_STATUS_SIGNERROR 0x0364 +#define USB3_UNI_QSERDES_TX_DCC_CAL_STATUS 0x0368 +#define USB3_UNI_QSERDES_RX_UCDR_FO_GAIN_HALF 0x0400 +#define USB3_UNI_QSERDES_RX_UCDR_FO_GAIN_QUARTER 0x0404 +#define USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x0408 +#define USB3_UNI_QSERDES_RX_UCDR_SO_GAIN_HALF 0x040C +#define USB3_UNI_QSERDES_RX_UCDR_SO_GAIN_QUARTER 0x0410 +#define USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x0414 +#define USB3_UNI_QSERDES_RX_UCDR_SVS_FO_GAIN_HALF 0x0418 +#define USB3_UNI_QSERDES_RX_UCDR_SVS_FO_GAIN_QUARTER 0x041C +#define USB3_UNI_QSERDES_RX_UCDR_SVS_FO_GAIN 0x0420 +#define USB3_UNI_QSERDES_RX_UCDR_SVS_SO_GAIN_HALF 0x0424 +#define USB3_UNI_QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER 0x0428 +#define USB3_UNI_QSERDES_RX_UCDR_SVS_SO_GAIN 0x042C +#define USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x0430 +#define USB3_UNI_QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x0434 +#define USB3_UNI_QSERDES_RX_UCDR_FO_TO_SO_DELAY 0x0438 +#define USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0x043C +#define USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0440 +#define USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS 0x0444 +#define USB3_UNI_QSERDES_RX_UCDR_PI_CTRL2 0x0448 +#define USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1 0x044C +#define USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2 0x0450 +#define USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1 0x0454 +#define USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2 0x0458 +#define USB3_UNI_QSERDES_RX_AUX_CONTROL 0x045C +#define USB3_UNI_QSERDES_RX_AUX_DATA_TCOARSE_TFINE 0x0460 +#define USB3_UNI_QSERDES_RX_RCLK_AUXDATA_SEL 0x0464 +#define USB3_UNI_QSERDES_RX_AC_JTAG_ENABLE 0x0468 +#define USB3_UNI_QSERDES_RX_AC_JTAG_INITP 0x046C +#define USB3_UNI_QSERDES_RX_AC_JTAG_INITN 0x0470 +#define USB3_UNI_QSERDES_RX_AC_JTAG_LVL 0x0474 +#define USB3_UNI_QSERDES_RX_AC_JTAG_MODE 0x0478 +#define USB3_UNI_QSERDES_RX_AC_JTAG_RESET 0x047C +#define USB3_UNI_QSERDES_RX_RX_TERM_BW 0x0480 +#define USB3_UNI_QSERDES_RX_RX_RCVR_IQ_EN 0x0484 +#define USB3_UNI_QSERDES_RX_RX_IDAC_I_DC_OFFSETS 0x0488 +#define USB3_UNI_QSERDES_RX_RX_IDAC_IBAR_DC_OFFSETS 0x048C +#define USB3_UNI_QSERDES_RX_RX_IDAC_Q_DC_OFFSETS 0x0490 +#define USB3_UNI_QSERDES_RX_RX_IDAC_QBAR_DC_OFFSETS 0x0494 +#define USB3_UNI_QSERDES_RX_RX_IDAC_A_DC_OFFSETS 0x0498 +#define USB3_UNI_QSERDES_RX_RX_IDAC_ABAR_DC_OFFSETS 0x049C +#define USB3_UNI_QSERDES_RX_RX_IDAC_EN 0x04A0 +#define USB3_UNI_QSERDES_RX_RX_IDAC_ENABLES 0x04A4 +#define USB3_UNI_QSERDES_RX_RX_IDAC_SIGN 0x04A8 +#define USB3_UNI_QSERDES_RX_RX_HIGHZ_HIGHRATE 0x04AC +#define USB3_UNI_QSERDES_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x04B0 +#define USB3_UNI_QSERDES_RX_DFE_1 0x04B4 +#define USB3_UNI_QSERDES_RX_DFE_2 0x04B8 +#define USB3_UNI_QSERDES_RX_DFE_3 0x04BC +#define USB3_UNI_QSERDES_RX_DFE_4 0x04C0 +#define USB3_UNI_QSERDES_RX_TX_ADAPT_PRE_THRESH1 0x04C4 +#define USB3_UNI_QSERDES_RX_TX_ADAPT_PRE_THRESH2 0x04C8 +#define USB3_UNI_QSERDES_RX_TX_ADAPT_POST_THRESH 0x04CC +#define USB3_UNI_QSERDES_RX_TX_ADAPT_MAIN_THRESH 0x04D0 +#define USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x04D4 +#define USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x04D8 +#define USB3_UNI_QSERDES_RX_GM_CAL 0x04DC +#define USB3_UNI_QSERDES_RX_RX_VGA_GAIN2_LSB 0x04E0 +#define USB3_UNI_QSERDES_RX_RX_VGA_GAIN2_MSB 0x04E4 +#define USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL1 0x04E8 +#define USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x04EC +#define USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x04F0 +#define USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x04F4 +#define USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_LOW 0x04F8 +#define USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_HIGH 0x04FC +#define USB3_UNI_QSERDES_RX_RX_IDAC_MEASURE_TIME 0x0500 +#define USB3_UNI_QSERDES_RX_RX_IDAC_ACCUMULATOR 0x0504 +#define USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_LSB 0x0508 +#define USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_MSB 0x050C +#define USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x0510 +#define USB3_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x0514 +#define USB3_UNI_QSERDES_RX_SIGDET_ENABLES 0x0518 +#define USB3_UNI_QSERDES_RX_SIGDET_CNTRL 0x051C +#define USB3_UNI_QSERDES_RX_SIGDET_LVL 0x0520 +#define USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x0524 +#define USB3_UNI_QSERDES_RX_RX_BAND 0x0528 +#define USB3_UNI_QSERDES_RX_CDR_FREEZE_UP_DN 0x052C +#define USB3_UNI_QSERDES_RX_CDR_RESET_OVERRIDE 0x0530 +#define USB3_UNI_QSERDES_RX_RX_INTERFACE_MODE 0x0534 +#define USB3_UNI_QSERDES_RX_JITTER_GEN_MODE 0x0538 +#define USB3_UNI_QSERDES_RX_SJ_AMP1 0x053C +#define USB3_UNI_QSERDES_RX_SJ_AMP2 0x0540 +#define USB3_UNI_QSERDES_RX_SJ_PER1 0x0544 +#define USB3_UNI_QSERDES_RX_SJ_PER2 0x0548 +#define USB3_UNI_QSERDES_RX_PPM_OFFSET1 0x054C +#define USB3_UNI_QSERDES_RX_PPM_OFFSET2 0x0550 +#define USB3_UNI_QSERDES_RX_SIGN_PPM_PERIOD1 0x0554 +#define USB3_UNI_QSERDES_RX_SIGN_PPM_PERIOD2 0x0558 +#define USB3_UNI_QSERDES_RX_RX_PWM_ENABLE_AND_DATA 0x055C +#define USB3_UNI_QSERDES_RX_RX_PWM_GEAR1_TIMEOUT_COUNT 0x0560 +#define USB3_UNI_QSERDES_RX_RX_PWM_GEAR2_TIMEOUT_COUNT 0x0564 +#define USB3_UNI_QSERDES_RX_RX_PWM_GEAR3_TIMEOUT_COUNT 0x0568 +#define USB3_UNI_QSERDES_RX_RX_PWM_GEAR4_TIMEOUT_COUNT 0x056C +#define USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0x0570 +#define USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x0574 +#define USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0x0578 +#define USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0x057C +#define USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0x0580 +#define USB3_UNI_QSERDES_RX_RX_MODE_01_LOW 0x0584 +#define USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0x0588 +#define USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0x058C +#define USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x0590 +#define USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0x0594 +#define USB3_UNI_QSERDES_RX_RX_MODE_10_LOW 0x0598 +#define USB3_UNI_QSERDES_RX_RX_MODE_10_HIGH 0x059C +#define USB3_UNI_QSERDES_RX_RX_MODE_10_HIGH2 0x05A0 +#define USB3_UNI_QSERDES_RX_RX_MODE_10_HIGH3 0x05A4 +#define USB3_UNI_QSERDES_RX_RX_MODE_10_HIGH4 0x05A8 +#define USB3_UNI_QSERDES_RX_PHPRE_CTRL 0x05AC +#define USB3_UNI_QSERDES_RX_PHPRE_INITVAL 0x05B0 +#define USB3_UNI_QSERDES_RX_DFE_EN_TIMER 0x05B4 +#define USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x05B8 +#define USB3_UNI_QSERDES_RX_DCC_CTRL1 0x05BC +#define USB3_UNI_QSERDES_RX_DCC_CTRL2 0x05C0 +#define USB3_UNI_QSERDES_RX_VTH_CODE 0x05C4 +#define USB3_UNI_QSERDES_RX_VTH_MIN_THRESH 0x05C8 +#define USB3_UNI_QSERDES_RX_VTH_MAX_THRESH 0x05CC +#define USB3_UNI_QSERDES_RX_ALOG_OBSV_BUS_CTRL_1 0x05D0 +#define USB3_UNI_QSERDES_RX_PI_CTRL1 0x05D4 +#define USB3_UNI_QSERDES_RX_PI_CTRL2 0x05D8 +#define USB3_UNI_QSERDES_RX_PI_QUAD 0x05DC +#define USB3_UNI_QSERDES_RX_IDATA1 0x05E0 +#define USB3_UNI_QSERDES_RX_IDATA2 0x05E4 +#define USB3_UNI_QSERDES_RX_AUX_DATA1 0x05E8 +#define USB3_UNI_QSERDES_RX_AUX_DATA2 0x05EC +#define USB3_UNI_QSERDES_RX_AC_JTAG_OUTP 0x05F0 +#define USB3_UNI_QSERDES_RX_AC_JTAG_OUTN 0x05F4 +#define USB3_UNI_QSERDES_RX_RX_SIGDET 0x05F8 +#define USB3_UNI_QSERDES_RX_ALOG_OBSV_BUS_STATUS_1 0x05FC +#define USB3_UNI_PCS_LN_PCS_STATUS1 0x0600 +#define USB3_UNI_PCS_LN_PCS_STATUS2 0x0604 +#define USB3_UNI_PCS_LN_PCS_STATUS2_CLEAR 0x0608 +#define USB3_UNI_PCS_LN_PCS_STATUS3 0x060C +#define USB3_UNI_PCS_LN_BIST_CHK_ERR_CNT_L_STATUS 0x0610 +#define USB3_UNI_PCS_LN_BIST_CHK_ERR_CNT_H_STATUS 0x0614 +#define USB3_UNI_PCS_LN_BIST_CHK_STATUS 0x0618 +#define USB3_UNI_PCS_LN_INSIG_SW_CTRL1 0x061C +#define USB3_UNI_PCS_LN_INSIG_MX_CTRL1 0x0620 +#define USB3_UNI_PCS_LN_OUTSIG_SW_CTRL1 0x0624 +#define USB3_UNI_PCS_LN_OUTSIG_MX_CTRL1 0x0628 +#define USB3_UNI_PCS_LN_TEST_CONTROL 0x062C +#define USB3_UNI_PCS_LN_BIST_CTRL 0x0630 +#define USB3_UNI_PCS_LN_PRBS_SEED0 0x0634 +#define USB3_UNI_PCS_LN_PRBS_SEED1 0x0638 +#define USB3_UNI_PCS_LN_FIXED_PAT_CTRL 0x063C +#define USB3_UNI_PCS_PCIE_LN_PRESET_OVERRIDE_PRE_POST 0x0700 +#define USB3_UNI_PCS_PCIE_LN_PRESET_OVERRIDE_PRE_POST_RS 0x0704 +#define USB3_UNI_PCS_PCIE_LN_PRESET_OVERRIDE_EN 0x0708 +#define USB3_UNI_PCS_PCIE_LN_PRESET_DSBL_L 0x070C +#define USB3_UNI_PCS_PCIE_LN_PRESET_DSBL_H 0x0710 +#define USB3_UNI_PCS_PCIE_LN_LANE_OFF_CONFIG 0x0714 +#define USB3_UNI_PCS_PCIE_LN_RXEQ_DONE_CONFIG1 0x0718 +#define USB3_UNI_PCS_PCIE_LN_RXEQ_DONE_CONFIG2 0x071C +#define USB3_UNI_PCS_PCIE_LN_PCIE_PCS_STATUS 0x0720 +#define USB3_UNI_PCS_SW_RESET 0x0800 +#define USB3_UNI_PCS_REVISION_ID0 0x0804 +#define USB3_UNI_PCS_REVISION_ID1 0x0808 +#define USB3_UNI_PCS_REVISION_ID2 0x080C +#define USB3_UNI_PCS_REVISION_ID3 0x0810 +#define USB3_UNI_PCS_PCS_STATUS1 0x0814 +#define USB3_UNI_PCS_PCS_STATUS2 0x0818 +#define USB3_UNI_PCS_PCS_STATUS3 0x081C +#define USB3_UNI_PCS_PCS_STATUS4 0x0820 +#define USB3_UNI_PCS_PCS_STATUS5 0x0824 +#define USB3_UNI_PCS_PCS_STATUS6 0x0828 +#define USB3_UNI_PCS_PCS_STATUS7 0x082C +#define USB3_UNI_PCS_DEBUG_BUS_0_STATUS 0x0830 +#define USB3_UNI_PCS_DEBUG_BUS_1_STATUS 0x0834 +#define USB3_UNI_PCS_DEBUG_BUS_2_STATUS 0x0838 +#define USB3_UNI_PCS_DEBUG_BUS_3_STATUS 0x083C +#define USB3_UNI_PCS_POWER_DOWN_CONTROL 0x0840 +#define USB3_UNI_PCS_START_CONTROL 0x0844 +#define USB3_UNI_PCS_INSIG_SW_CTRL1 0x0848 +#define USB3_UNI_PCS_INSIG_SW_CTRL2 0x084C +#define USB3_UNI_PCS_INSIG_SW_CTRL3 0x0850 +#define USB3_UNI_PCS_INSIG_SW_CTRL4 0x0854 +#define USB3_UNI_PCS_INSIG_SW_CTRL5 0x0858 +#define USB3_UNI_PCS_INSIG_SW_CTRL6 0x085C +#define USB3_UNI_PCS_INSIG_SW_CTRL7 0x0860 +#define USB3_UNI_PCS_INSIG_SW_CTRL8 0x0864 +#define USB3_UNI_PCS_INSIG_MX_CTRL1 0x0868 +#define USB3_UNI_PCS_INSIG_MX_CTRL2 0x086C +#define USB3_UNI_PCS_INSIG_MX_CTRL3 0x0870 +#define USB3_UNI_PCS_INSIG_MX_CTRL4 0x0874 +#define USB3_UNI_PCS_INSIG_MX_CTRL5 0x0878 +#define USB3_UNI_PCS_INSIG_MX_CTRL7 0x087C +#define USB3_UNI_PCS_INSIG_MX_CTRL8 0x0880 +#define USB3_UNI_PCS_OUTSIG_SW_CTRL1 0x0884 +#define USB3_UNI_PCS_OUTSIG_MX_CTRL1 0x0888 +#define USB3_UNI_PCS_CLAMP_ENABLE 0x088C +#define USB3_UNI_PCS_POWER_STATE_CONFIG1 0x0890 +#define USB3_UNI_PCS_POWER_STATE_CONFIG2 0x0894 +#define USB3_UNI_PCS_FLL_CNTRL1 0x0898 +#define USB3_UNI_PCS_FLL_CNTRL2 0x089C +#define USB3_UNI_PCS_FLL_CNT_VAL_L 0x08A0 +#define USB3_UNI_PCS_FLL_CNT_VAL_H_TOL 0x08A4 +#define USB3_UNI_PCS_FLL_MAN_CODE 0x08A8 +#define USB3_UNI_PCS_TEST_CONTROL1 0x08AC +#define USB3_UNI_PCS_TEST_CONTROL2 0x08B0 +#define USB3_UNI_PCS_TEST_CONTROL3 0x08B4 +#define USB3_UNI_PCS_TEST_CONTROL4 0x08B8 +#define USB3_UNI_PCS_TEST_CONTROL5 0x08BC +#define USB3_UNI_PCS_TEST_CONTROL6 0x08C0 +#define USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0x08C4 +#define USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x08C8 +#define USB3_UNI_PCS_LOCK_DETECT_CONFIG3 0x08CC +#define USB3_UNI_PCS_LOCK_DETECT_CONFIG4 0x08D0 +#define USB3_UNI_PCS_LOCK_DETECT_CONFIG5 0x08D4 +#define USB3_UNI_PCS_LOCK_DETECT_CONFIG6 0x08D8 +#define USB3_UNI_PCS_REFGEN_REQ_CONFIG1 0x08DC +#define USB3_UNI_PCS_REFGEN_REQ_CONFIG2 0x08E0 +#define USB3_UNI_PCS_REFGEN_REQ_CONFIG3 0x08E4 +#define USB3_UNI_PCS_BIST_CTRL 0x08E8 +#define USB3_UNI_PCS_PRBS_POLY0 0x08EC +#define USB3_UNI_PCS_PRBS_POLY1 0x08F0 +#define USB3_UNI_PCS_FIXED_PAT0 0x08F4 +#define USB3_UNI_PCS_FIXED_PAT1 0x08F8 +#define USB3_UNI_PCS_FIXED_PAT2 0x08FC +#define USB3_UNI_PCS_FIXED_PAT3 0x0900 +#define USB3_UNI_PCS_FIXED_PAT4 0x0904 +#define USB3_UNI_PCS_FIXED_PAT5 0x0908 +#define USB3_UNI_PCS_FIXED_PAT6 0x090C +#define USB3_UNI_PCS_FIXED_PAT7 0x0910 +#define USB3_UNI_PCS_FIXED_PAT8 0x0914 +#define USB3_UNI_PCS_FIXED_PAT9 0x0918 +#define USB3_UNI_PCS_FIXED_PAT10 0x091C +#define USB3_UNI_PCS_FIXED_PAT11 0x0920 +#define USB3_UNI_PCS_FIXED_PAT12 0x0924 +#define USB3_UNI_PCS_FIXED_PAT13 0x0928 +#define USB3_UNI_PCS_FIXED_PAT14 0x092C +#define USB3_UNI_PCS_FIXED_PAT15 0x0930 +#define USB3_UNI_PCS_TXMGN_CONFIG 0x0934 +#define USB3_UNI_PCS_G12S1_TXMGN_V0 0x0938 +#define USB3_UNI_PCS_G12S1_TXMGN_V1 0x093C +#define USB3_UNI_PCS_G12S1_TXMGN_V2 0x0940 +#define USB3_UNI_PCS_G12S1_TXMGN_V3 0x0944 +#define USB3_UNI_PCS_G12S1_TXMGN_V4 0x0948 +#define USB3_UNI_PCS_G12S1_TXMGN_V0_RS 0x094C +#define USB3_UNI_PCS_G12S1_TXMGN_V1_RS 0x0950 +#define USB3_UNI_PCS_G12S1_TXMGN_V2_RS 0x0954 +#define USB3_UNI_PCS_G12S1_TXMGN_V3_RS 0x0958 +#define USB3_UNI_PCS_G12S1_TXMGN_V4_RS 0x095C +#define USB3_UNI_PCS_G3S2_TXMGN_MAIN 0x0960 +#define USB3_UNI_PCS_G3S2_TXMGN_MAIN_RS 0x0964 +#define USB3_UNI_PCS_G12S1_TXDEEMPH_M6DB 0x0968 +#define USB3_UNI_PCS_G12S1_TXDEEMPH_M3P5DB 0x096C +#define USB3_UNI_PCS_G3S2_PRE_GAIN 0x0970 +#define USB3_UNI_PCS_G3S2_POST_GAIN 0x0974 +#define USB3_UNI_PCS_G3S2_PRE_POST_OFFSET 0x0978 +#define USB3_UNI_PCS_G3S2_PRE_GAIN_RS 0x097C +#define USB3_UNI_PCS_G3S2_POST_GAIN_RS 0x0980 +#define USB3_UNI_PCS_G3S2_PRE_POST_OFFSET_RS 0x0984 +#define USB3_UNI_PCS_RX_SIGDET_LVL 0x0988 +#define USB3_UNI_PCS_RX_SIGDET_DTCT_CNTRL 0x098C +#define USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0x0990 +#define USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x0994 +#define USB3_UNI_PCS_RATE_SLEW_CNTRL1 0x0998 +#define USB3_UNI_PCS_RATE_SLEW_CNTRL2 0x099C +#define USB3_UNI_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x09A0 +#define USB3_UNI_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x09A4 +#define USB3_UNI_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x09A8 +#define USB3_UNI_PCS_TSYNC_RSYNC_TIME 0x09AC +#define USB3_UNI_PCS_CDR_RESET_TIME 0x09B0 +#define USB3_UNI_PCS_TSYNC_DLY_TIME 0x09B4 +#define USB3_UNI_PCS_ELECIDLE_DLY_SEL 0x09B8 +#define USB3_UNI_PCS_CMN_ACK_OUT_SEL 0x09BC +#define USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 0x09C0 +#define USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 0x09C4 +#define USB3_UNI_PCS_ALIGN_DETECT_CONFIG3 0x09C8 +#define USB3_UNI_PCS_ALIGN_DETECT_CONFIG4 0x09CC +#define USB3_UNI_PCS_PCS_TX_RX_CONFIG 0x09D0 +#define USB3_UNI_PCS_RX_IDLE_DTCT_CNTRL 0x09D4 +#define USB3_UNI_PCS_RX_DCC_CAL_CONFIG 0x09D8 +#define USB3_UNI_PCS_EQ_CONFIG1 0x09DC +#define USB3_UNI_PCS_EQ_CONFIG2 0x09E0 +#define USB3_UNI_PCS_EQ_CONFIG3 0x09E4 +#define USB3_UNI_PCS_EQ_CONFIG4 0x09E8 +#define USB3_UNI_PCS_EQ_CONFIG5 0x09EC +#define USB3_UNI_PCS_PCIE_INT_AUX_CLK_STATUS 0x0C00 +#define USB3_UNI_PCS_PCIE_OSC_DTCT_STATUS 0x0C04 +#define USB3_UNI_PCS_PCIE_POWER_STATE_CONFIG1 0x0C08 +#define USB3_UNI_PCS_PCIE_POWER_STATE_CONFIG2 0x0C0C +#define USB3_UNI_PCS_PCIE_POWER_STATE_CONFIG3 0x0C10 +#define USB3_UNI_PCS_PCIE_POWER_STATE_CONFIG4 0x0C14 +#define USB3_UNI_PCS_PCIE_PCS_TX_RX_CONFIG 0x0C18 +#define USB3_UNI_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x0C1C +#define USB3_UNI_PCS_PCIE_ENDPOINT_REFCLK_CNTRL 0x0C20 +#define USB3_UNI_PCS_PCIE_EPCLK_PRE_PLL_LOCK_DLY_AUXCLK 0x0C24 +#define USB3_UNI_PCS_PCIE_EPCLK_DLY_COUNT_VAL_L 0x0C28 +#define USB3_UNI_PCS_PCIE_EPCLK_DLY_COUNT_VAL_H 0x0C2C +#define USB3_UNI_PCS_PCIE_RX_IDLE_DTCT_CNTRL1 0x0C30 +#define USB3_UNI_PCS_PCIE_RX_IDLE_DTCT_CNTRL2 0x0C34 +#define USB3_UNI_PCS_PCIE_SIGDET_CNTRL 0x0C38 +#define USB3_UNI_PCS_PCIE_SIGDET_LOW_2_IDLE_TIME 0x0C3C +#define USB3_UNI_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x0C40 +#define USB3_UNI_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x0C44 +#define USB3_UNI_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x0C48 +#define USB3_UNI_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x0C4C +#define USB3_UNI_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x0C50 +#define USB3_UNI_PCS_PCIE_INT_AUX_CLK_CONFIG2 0x0C54 +#define USB3_UNI_PCS_PCIE_OSC_DTCT_CONFIG1 0x0C58 +#define USB3_UNI_PCS_PCIE_OSC_DTCT_CONFIG2 0x0C5C +#define USB3_UNI_PCS_PCIE_OSC_DTCT_CONFIG3 0x0C60 +#define USB3_UNI_PCS_PCIE_OSC_DTCT_CONFIG4 0x0C64 +#define USB3_UNI_PCS_PCIE_OSC_DTCT_CONFIG5 0x0C68 +#define USB3_UNI_PCS_PCIE_OSC_DTCT_CONFIG6 0x0C6C +#define USB3_UNI_PCS_PCIE_OSC_DTCT_CONFIG7 0x0C70 +#define USB3_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG1 0x0C74 +#define USB3_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x0C78 +#define USB3_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG3 0x0C7C +#define USB3_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x0C80 +#define USB3_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x0C84 +#define USB3_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6 0x0C88 +#define USB3_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG7 0x0C8C +#define USB3_UNI_PCS_PCIE_OSC_DTCT_ACTIONS 0x0C90 +#define USB3_UNI_PCS_PCIE_LOCAL_FS 0x0C94 +#define USB3_UNI_PCS_PCIE_LOCAL_LF 0x0C98 +#define USB3_UNI_PCS_PCIE_LOCAL_FS_RS 0x0C9C +#define USB3_UNI_PCS_PCIE_EQ_CONFIG1 0x0CA0 +#define USB3_UNI_PCS_PCIE_EQ_CONFIG2 0x0CA4 +#define USB3_UNI_PCS_PCIE_PRESET_P0_P1_PRE 0x0CA8 +#define USB3_UNI_PCS_PCIE_PRESET_P2_P3_PRE 0x0CAC +#define USB3_UNI_PCS_PCIE_PRESET_P4_P5_PRE 0x0CB0 +#define USB3_UNI_PCS_PCIE_PRESET_P6_P7_PRE 0x0CB4 +#define USB3_UNI_PCS_PCIE_PRESET_P8_P9_PRE 0x0CB8 +#define USB3_UNI_PCS_PCIE_PRESET_P10_PRE 0x0CBC +#define USB3_UNI_PCS_PCIE_PRESET_P1_P3_PRE_RS 0x0CC0 +#define USB3_UNI_PCS_PCIE_PRESET_P4_P5_PRE_RS 0x0CC4 +#define USB3_UNI_PCS_PCIE_PRESET_P6_P9_PRE_RS 0x0CC8 +#define USB3_UNI_PCS_PCIE_PRESET_P0_P1_POST 0x0CCC +#define USB3_UNI_PCS_PCIE_PRESET_P2_P3_POST 0x0CD0 +#define USB3_UNI_PCS_PCIE_PRESET_P4_P5_POST 0x0CD4 +#define USB3_UNI_PCS_PCIE_PRESET_P6_P7_POST 0x0CD8 +#define USB3_UNI_PCS_PCIE_PRESET_P8_P9_POST 0x0CDC +#define USB3_UNI_PCS_PCIE_PRESET_P10_POST 0x0CE0 +#define USB3_UNI_PCS_PCIE_PRESET_P1_P3_POST_RS 0x0CE4 +#define USB3_UNI_PCS_PCIE_PRESET_P4_P5_POST_RS 0x0CE8 +#define USB3_UNI_PCS_PCIE_PRESET_P6_P9_POST_RS 0x0CEC +#define USB3_UNI_PCS_PCIE_RXEQEVAL_TIME 0x0CF0 +#define USB3_UNI_PCS_PCIE_INSIG_SW_CTRL1 0x0CF4 +#define USB3_UNI_PCS_PCIE_INSIG_MX_CTRL1 0x0CF8 +#define USB3_UNI_PCS_USB3_POWER_STATE_CONFIG1 0x0E00 +#define USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x0E04 +#define USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x0E08 +#define USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x0E0C +#define USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x0E10 +#define USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x0E14 +#define USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x0E18 +#define USB3_UNI_PCS_USB3_LFPS_TX_ECSTART 0x0E1C +#define USB3_UNI_PCS_USB3_LFPS_PER_TIMER_VAL 0x0E20 +#define USB3_UNI_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x0E24 +#define USB3_UNI_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x0E28 +#define USB3_UNI_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x0E2C +#define USB3_UNI_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x0E30 +#define USB3_UNI_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x0E34 +#define USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x0E38 +#define USB3_UNI_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x0E3C +#define USB3_UNI_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x0E40 +#define USB3_UNI_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x0E44 +#define USB3_UNI_PCS_USB3_ARCVR_DTCT_CM_DLY 0x0E48 +#define USB3_UNI_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x0E4C +#define USB3_UNI_PCS_USB3_ALFPS_DEGLITCH_VAL 0x0E50 +#define USB3_UNI_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x0E54 +#define USB3_UNI_PCS_USB3_TEST_CONTROL 0x0E58 +#define USB3_UNI_PCS_USB3_RXTERMINATION_DLY_SEL 0x0E5C + +#endif /* _DT_BINDINGS_PHY_QCOM_SM8150_QMP_USB_H */ From d948568a1f7bfbbb482c9ee39dae2c7580e24852 Mon Sep 17 00:00:00 2001 From: Hemant Kumar Date: Thu, 29 Nov 2018 18:50:54 -0800 Subject: [PATCH 2/4] usb: phy: snps: Ensure VDDA regulator is put in HPM To properly ensure that the vdd regulator is put in the correct operating mode, it needs to have a call to regulator_set_load() prior to being enabled. This is crucial for platforms where the HS PHY is the only consumer of the regulator as it could be inadvertently left in LPM mode and cause the PHY to not function properly. Change-Id: I87815c60f044d854ecc75ac6039fd80c2d3197aa Signed-off-by: Hemant Kumar --- drivers/usb/phy/phy-msm-snps-hs.c | 47 ++++++++++++++----------------- 1 file changed, 21 insertions(+), 26 deletions(-) diff --git a/drivers/usb/phy/phy-msm-snps-hs.c b/drivers/usb/phy/phy-msm-snps-hs.c index 35a46f7360aa..342fbb2ff90c 100644 --- a/drivers/usb/phy/phy-msm-snps-hs.c +++ b/drivers/usb/phy/phy-msm-snps-hs.c @@ -81,6 +81,8 @@ #define USB_HSPHY_1P8_VOL_MAX 1800000 /* uV */ #define USB_HSPHY_1P8_HPM_LOAD 19000 /* uA */ +#define USB_HSPHY_VDD_HPM_LOAD 30000 /* uA */ + struct msm_hsphy { struct usb_phy phy; void __iomem *base; @@ -146,23 +148,6 @@ static void msm_hsphy_enable_clocks(struct msm_hsphy *phy, bool on) } } -static int msm_hsphy_config_vdd(struct msm_hsphy *phy, int high) -{ - int min, ret; - - min = high ? 1 : 0; /* low or none? */ - ret = regulator_set_voltage(phy->vdd, phy->vdd_levels[min], - phy->vdd_levels[2]); - if (ret) { - dev_err(phy->phy.dev, "unable to set voltage for hsusb vdd\n"); - return ret; - } - - dev_dbg(phy->phy.dev, "%s: min_vol:%d max_vol:%d\n", __func__, - phy->vdd_levels[min], phy->vdd_levels[2]); - - return ret; -} static int msm_hsphy_enable_power(struct msm_hsphy *phy, bool on) { @@ -179,13 +164,19 @@ static int msm_hsphy_enable_power(struct msm_hsphy *phy, bool on) if (!on) goto disable_vdda33; - ret = msm_hsphy_config_vdd(phy, true); - if (ret) { - dev_err(phy->phy.dev, "Unable to config VDD:%d\n", - ret); + ret = regulator_set_load(phy->vdd, USB_HSPHY_VDD_HPM_LOAD); + if (ret < 0) { + dev_err(phy->phy.dev, "Unable to set HPM of vdd:%d\n", ret); goto err_vdd; } + ret = regulator_set_voltage(phy->vdd, phy->vdd_levels[1], + phy->vdd_levels[2]); + if (ret) { + dev_err(phy->phy.dev, "unable to set voltage for hsusb vdd\n"); + goto put_vdd_lpm; + } + ret = regulator_enable(phy->vdd); if (ret) { dev_err(phy->phy.dev, "Unable to enable VDD\n"); @@ -272,14 +263,18 @@ put_vdda18_lpm: disable_vdd: ret = regulator_disable(phy->vdd); if (ret) - dev_err(phy->phy.dev, "Unable to disable vdd:%d\n", - ret); + dev_err(phy->phy.dev, "Unable to disable vdd:%d\n", ret); unconfig_vdd: - ret = msm_hsphy_config_vdd(phy, false); + ret = regulator_set_voltage(phy->vdd, phy->vdd_levels[0], + phy->vdd_levels[2]); if (ret) - dev_err(phy->phy.dev, "Unable unconfig VDD:%d\n", - ret); + dev_err(phy->phy.dev, "unable to set voltage for hsusb vdd\n"); + +put_vdd_lpm: + ret = regulator_set_load(phy->vdd, 0); + if (ret < 0) + dev_err(phy->phy.dev, "Unable to set LPM of vdd\n"); err_vdd: phy->power_enabled = false; dev_dbg(phy->phy.dev, "HSUSB PHY's regulators are turned OFF.\n"); From 026280fcfa2b2e78d85b36cb04b2e6d0bc300f0a Mon Sep 17 00:00:00 2001 From: Pratham Pratap Date: Tue, 19 May 2020 00:33:19 +0530 Subject: [PATCH 3/4] usb: phy: snps: Return error if driver fails to enable power Currently driver is not returning any error from the error handling path if driver fails to enable power for PHY. This patch adds a check and returns error if the driver actually fails to set_voltage or fails to enable a particular regulator. Change-Id: I5427690602b6152151adee71c6388ce836ab90c6 Signed-off-by: Pratham Pratap --- drivers/usb/phy/phy-msm-snps-hs.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/usb/phy/phy-msm-snps-hs.c b/drivers/usb/phy/phy-msm-snps-hs.c index 342fbb2ff90c..f1fef3c48c96 100644 --- a/drivers/usb/phy/phy-msm-snps-hs.c +++ b/drivers/usb/phy/phy-msm-snps-hs.c @@ -275,6 +275,12 @@ put_vdd_lpm: ret = regulator_set_load(phy->vdd, 0); if (ret < 0) dev_err(phy->phy.dev, "Unable to set LPM of vdd\n"); + /* Return from here based on power_enabled. If it is not set + * then return -EINVAL since either set_voltage or + * regulator_enable failed + */ + if (!phy->power_enabled) + return -EINVAL; err_vdd: phy->power_enabled = false; dev_dbg(phy->phy.dev, "HSUSB PHY's regulators are turned OFF.\n"); From 3737f15cc71ebbac0f2fb6c7a66ff333ec81512e Mon Sep 17 00:00:00 2001 From: Ajay Agarwal Date: Mon, 18 May 2020 15:19:15 +0530 Subject: [PATCH 4/4] usb: dwc3-msm: Avoid access of gsi_reg for non-GSI targets Some targets do not have GSI feature. For such targets, gsi_reg array does not get allocated. DWC3_CONTROLLER_NOTIFY_CLEAR_DB event from gadget driver will access this unallocated memory. Fix this by putting a check for gsi_reg. Change-Id: I9903c0c6533abf3d6e689a40ea84ecbc066e10d8 Signed-off-by: Ajay Agarwal --- drivers/usb/dwc3/dwc3-msm.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-msm.c b/drivers/usb/dwc3/dwc3-msm.c index 6944bfad19b9..a2c536cb0cd4 100644 --- a/drivers/usb/dwc3/dwc3-msm.c +++ b/drivers/usb/dwc3/dwc3-msm.c @@ -2482,12 +2482,14 @@ static void dwc3_msm_notify_event(struct dwc3 *dwc, break; case DWC3_CONTROLLER_NOTIFY_CLEAR_DB: dev_dbg(mdwc->dev, "DWC3_CONTROLLER_NOTIFY_CLEAR_DB\n"); - dwc3_msm_write_reg_field(mdwc->base, - GSI_GENERAL_CFG_REG(mdwc->gsi_reg), - BLOCK_GSI_WR_GO_MASK, true); - dwc3_msm_write_reg_field(mdwc->base, - GSI_GENERAL_CFG_REG(mdwc->gsi_reg), - GSI_EN_MASK, 0); + if (mdwc->gsi_reg) { + dwc3_msm_write_reg_field(mdwc->base, + GSI_GENERAL_CFG_REG(mdwc->gsi_reg), + BLOCK_GSI_WR_GO_MASK, true); + dwc3_msm_write_reg_field(mdwc->base, + GSI_GENERAL_CFG_REG(mdwc->gsi_reg), + GSI_EN_MASK, 0); + } break; default: dev_dbg(mdwc->dev, "unknown dwc3 event\n");