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wigig_sensing: make sys-assert DRI priority higher

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In case sys-assert DRI is pending, there is no need to process other
pending DRIs.

Change-Id: I3f1422d75ae5d966c855213031b3524c46d7f5d5
Signed-off-by: Gidon Studinski <[email protected]>
Signed-off-by: Alexei Avshalom Lazar <[email protected]>
This commit is contained in:
Gidon Studinski 2019-11-25 15:00:45 +02:00 • committed by Alexei Avshalom Lazar
commit 12db099039
1 changed files with 22 additions and 19 deletions
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41
drivers/misc/wigig_sensing.c
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@ -1276,8 +1276,26 @@ static irqreturn_t wigig_sensing_dri_isr_thread(int irq, void *cookie)
goto bail_out;
}
if (spi_status.b.int_sysassert) {
pr_info_ratelimited("SYSASSERT INTERRUPT\n");
ctx->stm.fw_is_ready = false;
rc = wigig_sensing_change_state(ctx, &ctx->stm,
WIGIG_SENSING_STATE_SYS_ASSERT);
if (rc != 0 ||
ctx->stm.state != WIGIG_SENSING_STATE_SYS_ASSERT)
pr_err("State change to WIGIG_SENSING_SYS_ASSERT failed\n");
/* Send asynchronous RESET event to application */
wigig_sensing_send_event(ctx, WIGIG_SENSING_EVENT_RESET);
ctx->stm.spi_malfunction = true;
memset(&ctx->inb_cmd, 0, sizeof(ctx->inb_cmd));
spi_status.v &= ~INT_SYSASSERT;
goto deassert_and_bail_out;
}
if (spi_status.b.int_fw_ready) {
pr_debug("FW READY INTERRUPT\n");
pr_info_ratelimited("FW READY INTERRUPT\n");
ctx->stm.fw_is_ready = true;
ctx->stm.channel_request = 0;
ctx->stm.burst_size = 0;
@ -1302,27 +1320,11 @@ static irqreturn_t wigig_sensing_dri_isr_thread(int irq, void *cookie)
pr_debug("Change mode in progress, aborting data processing\n");
spi_status.v &= ~INT_DATA_READY;
}
if (spi_status.b.int_sysassert) {
pr_debug("SYSASSERT INTERRUPT\n");
ctx->stm.fw_is_ready = false;
rc = wigig_sensing_change_state(ctx, &ctx->stm,
WIGIG_SENSING_STATE_SYS_ASSERT);
if (rc != 0 ||
ctx->stm.state != WIGIG_SENSING_STATE_SYS_ASSERT)
pr_err("State change to WIGIG_SENSING_SYS_ASSERT failed\n");
/* Send asynchronous RESET event to application */
wigig_sensing_send_event(ctx, WIGIG_SENSING_EVENT_RESET);
ctx->stm.spi_malfunction = true;
spi_status.v &= ~INT_SYSASSERT;
}
if (spi_status.b.int_deep_sleep_exit ||
(ctx->stm.waiting_for_deep_sleep_exit &&
ctx->stm.waiting_for_deep_sleep_exit_first_pass)) {
if (spi_status.b.int_deep_sleep_exit)
pr_debug("DEEP SLEEP EXIT INTERRUPT\n");
pr_info_ratelimited("DEEP SLEEP EXIT INTERRUPT\n");
if (ctx->stm.waiting_for_deep_sleep_exit) {
additional_inb_command = ctx->inb_cmd;
@ -1335,7 +1337,7 @@ static irqreturn_t wigig_sensing_dri_isr_thread(int irq, void *cookie)
spi_status.v &= ~INT_DEEP_SLEEP_EXIT;
}
if (spi_status.b.int_fifo_ready) {
pr_debug("FIFO READY INTERRUPT\n");
pr_info_ratelimited("FIFO READY INTERRUPT\n");
wigig_sensing_handle_fifo_ready_dri(ctx);
spi_status.v &= ~INT_FIFO_READY;
@ -1349,6 +1351,7 @@ static irqreturn_t wigig_sensing_dri_isr_thread(int irq, void *cookie)
pr_err("Unexpected interrupt received, spi_status=0x%X\n",
spi_status.v & CLEAR_LOW_23_BITS);
deassert_and_bail_out:
/* Notify FW we are done with interrupt handling */
rc = wigig_sensing_deassert_dri(ctx, additional_inb_command);
if (rc)