From 12dee74ffc5cdd52dca24a2f0d162e54b82e1699 Mon Sep 17 00:00:00 2001
From: Vivek Kumar <vivekuma@qti.qualcomm.com>
Date: Thu, 19 Nov 2020 14:02:56 +0530
Subject: [PATCH] ARM: dts: msm: Add the SMMU devices for SM8150

Add the set of devices that describe the APPS
and graphics SMMU register spaces and various
properties for SM8150.

Change-Id: I149b53bbb2c36410df69a954dc246ccbc9350534
---
 qcom/msm-arm-smmu-sm8150-v2.dtsi | 318 +++++++++++++++++++++++++++++
 qcom/msm-arm-smmu-sm8150.dtsi    | 332 +++++++++++++++++++++++++++++++
 qcom/sm8150-v2.dtsi              |   6 +
 qcom/sm8150.dtsi                 |   1 +
 4 files changed, 657 insertions(+)
 create mode 100644 qcom/msm-arm-smmu-sm8150-v2.dtsi
 create mode 100644 qcom/msm-arm-smmu-sm8150.dtsi

diff --git a/qcom/msm-arm-smmu-sm8150-v2.dtsi b/qcom/msm-arm-smmu-sm8150-v2.dtsi
new file mode 100644
index 000000000000..b694e0b014e8
--- /dev/null
+++ b/qcom/msm-arm-smmu-sm8150-v2.dtsi
@@ -0,0 +1,318 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+&soc {
+	kgsl_smmu: kgsl-smmu@0x02ca0000 {
+		compatible = "qcom,qsmmu-v500";
+		reg = <0x02ca0000 0x10000>,
+			<0x2cc2000 0x20>;
+		reg-names = "base", "tcu-base";
+		#iommu-cells = <2>;
+		qcom,dynamic;
+		qcom,skip-init;
+		qcom,use-3-lvl-tables;
+		qcom,disable-atos;
+		#global-interrupts = <1>;
+		qcom,regulator-names = "vdd";
+		vdd-supply = <&gpu_cx_gdsc>;
+
+		clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+			 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+			 <&gpucc GPU_CC_AHB_CLK>;
+		clock-names = "gcc_gpu_memnoc_gfx_clk",
+			      "gcc_gpu_snoc_dvm_gfx_clk",
+			      "gpu_cc_ahb_clk";
+		#size-cells = <1>;
+		#address-cells = <1>;
+		ranges;
+		interrupts =	<GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>;
+
+		gfx_0_tbu: gfx_0_tbu@0x2cc5000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x2cc5000 0x1000>,
+				<0x2cc2200 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x0 0x400>;
+		};
+
+		gfx_1_tbu: gfx_1_tbu@0x2cc9000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x2cc9000 0x1000>,
+				<0x2cc2208 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x400 0x400>;
+		};
+	};
+
+	apps_smmu: apps-smmu@0x15000000 {
+		compatible = "qcom,qsmmu-v500";
+		reg = <0x15000000 0x100000>,
+			<0x15182000 0x20>;
+		reg-names = "base", "tcu-base";
+		#iommu-cells = <2>;
+		qcom,skip-init;
+		qcom,use-3-lvl-tables;
+		qcom,disable-atos;
+		#global-interrupts = <1>;
+		#size-cells = <1>;
+		#address-cells = <1>;
+		ranges;
+		interrupts =	<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
+
+		interconnects = <&system_noc MASTER_GEM_NOC_SNOC
+				&config_noc SLAVE_IMEM_CFG>;
+		qcom,active-only;
+
+		anoc_1_tbu: anoc_1_tbu@0x15185000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x15185000 0x1000>,
+				<0x15182200 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x0 0x400>;
+			qcom,regulator-names = "vdd";
+			vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu1_gdsc>;
+			qcom,active-only;
+			interconnects = <&system_noc MASTER_GEM_NOC_SNOC
+					&config_noc SLAVE_IMEM_CFG>;
+		};
+
+		anoc_2_tbu: anoc_2_tbu@0x15189000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x15189000 0x1000>,
+				<0x15182208 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x400 0x400>;
+			qcom,regulator-names = "vdd";
+			vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu2_gdsc>;
+			qcom,active-only;
+			interconnects = <&system_noc MASTER_GEM_NOC_SNOC
+					&config_noc SLAVE_IMEM_CFG>;
+		};
+
+		mnoc_hf_0_tbu: mnoc_hf_0_tbu@0x1518d000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x1518d000 0x1000>,
+				<0x15182210 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x800 0x400>;
+			qcom,regulator-names = "vdd";
+			vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>;
+			qcom,active-only;
+			interconnects = <&mmss_noc MASTER_MDP0
+					 &mmss_noc SLAVE_MNOC_HF_MEM_NOC>;
+		};
+
+		mnoc_hf_1_tbu: mnoc_hf_1_tbu@0x15191000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x15191000 0x1000>,
+				<0x15182218 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0xc00 0x400>;
+			qcom,regulator-names = "vdd";
+			vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc>;
+			qcom,active-only;
+			interconnects = <&mmss_noc MASTER_MDP0
+					 &mmss_noc SLAVE_MNOC_HF_MEM_NOC>;
+		};
+
+		compute_dsp_1_tbu: compute_dsp_1_tbu@0x15195000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x15195000 0x1000>,
+				<0x15182220 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x1000 0x400>;
+			/* No GDSC */
+			qcom,active-only;
+			interconnects = <&compute_noc MASTER_NPU
+					 &compute_noc SLAVE_CDSP_MEM_NOC>;
+		};
+
+		compute_dsp_0_tbu: compute_dsp_0_tbu@0x15199000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x15199000 0x1000>,
+				<0x15182228 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x1400 0x400>;
+			/* No GDSC */
+			qcom,active-only;
+			interconnects = <&compute_noc MASTER_NPU
+					 &compute_noc SLAVE_CDSP_MEM_NOC>;
+		};
+
+		adsp_tbu: adsp_tbu@0x1519d000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x1519d000 0x1000>,
+				<0x15182230 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x1800 0x400>;
+			qcom,regulator-names = "vdd";
+			vdd-supply = <&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc>;
+			qcom,active-only;
+			interconnects = <&system_noc MASTER_GEM_NOC_SNOC
+					&config_noc SLAVE_IMEM_CFG>;
+		};
+
+		anoc_1_pcie_tbu: anoc_1_pcie_tbu@0x151a1000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151a1000 0x1000>,
+				<0x15182238 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x1c00 0x400>;
+			qcom,opt-out-tbu-halting;
+			qcom,regulator-names = "vdd";
+			vdd-supply = <&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc>;
+			clock-names = "gcc_aggre_noc_pcie_tbu_clk";
+			clocks = <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
+			qcom,active-only;
+			interconnects = <&system_noc MASTER_GEM_NOC_SNOC
+					&config_noc SLAVE_IMEM_CFG>;
+		};
+
+		mnoc_sf_0_tbu: mnoc_sf_0_tbu@0x151a5000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151a5000 0x1000>,
+				<0x15182240 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x2000 0x400>;
+			qcom,regulator-names = "vdd";
+			vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc>;
+			qcom,active-only;
+			interconnects = <&mmss_noc MASTER_CAMNOC_SF
+					 &mmss_noc SLAVE_MNOC_SF_MEM_NOC>;
+		};
+	};
+
+	kgsl_iommu_test_device {
+		compatible = "iommu-debug-test";
+		iommus = <&kgsl_smmu 0x7 0>;
+		qcom,iommu-dma = "disabled";
+	};
+
+	kgsl_iommu_coherent_test_device {
+		compatible = "iommu-debug-test";
+		iommus = <&kgsl_smmu 0x9 0>;
+		qcom,iommu-dma = "disabled";
+		dma-coherent;
+	};
+
+	apps_iommu_test_device {
+		compatible = "iommu-debug-test";
+		iommus = <&apps_smmu 0x21 0>;
+		qcom,iommu-dma = "disabled";
+	};
+
+	apps_iommu_coherent_test_device {
+		compatible = "iommu-debug-test";
+		iommus = <&apps_smmu 0x23 0>;
+		qcom,iommu-dma = "disabled";
+		dma-coherent;
+	};
+};
+
+&kgsl_smmu {
+	qcom,actlr =
+		/* All CBs of GFX: +15 deep PF */
+		<0x0 0x407 0x303>;
+};
+
+&apps_smmu {
+	qcom,actlr =
+		/* HF0 and HF1 TBUs: +3 deep PF */
+		<0x800 0x7ff 0x103>,
+
+		/* SF TBU: +3 deep PF */
+		<0x2000 0x3ff 0x103>,
+
+		/* NPU SIDs: +15 deep PF */
+		<0x1480 0x3 0x303>,
+		<0x1484 0x1 0x303>,
+		<0x1080 0x3 0x303>,
+		<0x1084 0x1 0x303>;
+};
diff --git a/qcom/msm-arm-smmu-sm8150.dtsi b/qcom/msm-arm-smmu-sm8150.dtsi
new file mode 100644
index 000000000000..f279e5a55d46
--- /dev/null
+++ b/qcom/msm-arm-smmu-sm8150.dtsi
@@ -0,0 +1,332 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+&soc {
+	kgsl_smmu: kgsl-smmu@0x02CA0000 {
+		compatible = "qcom,qsmmu-v500";
+		reg = <0x02CA0000 0x10000>,
+			<0x2CC2000 0x20>;
+		reg-names = "base", "tcu-base";
+		#iommu-cells = <2>;
+		qcom,dynamic;
+		qcom,skip-init;
+		qcom,use-3-lvl-tables;
+		qcom,disable-atos;
+		qcom,min-iova-align;
+		#global-interrupts = <1>;
+		qcom,regulator-names = "vdd";
+		vdd-supply = <&gpu_cx_gdsc>;
+
+		clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+			 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+			 <&gpucc GPU_CC_AHB_CLK>;
+		clock-names = "gcc_gpu_memnoc_gfx_clk",
+			      "gcc_gpu_snoc_dvm_gfx_clk",
+			      "gpu_cc_ahb_clk";
+		#size-cells = <1>;
+		#address-cells = <1>;
+		ranges;
+		interrupts =	<GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>;
+
+		gfx_0_tbu: gfx_0_tbu@0x2CC5000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x2CC5000 0x1000>,
+				<0x2CC2200 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x0 0x400>;
+		};
+
+		gfx_1_tbu: gfx_1_tbu@0x2CC9000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x2CC9000 0x1000>,
+				<0x2CC2208 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x400 0x400>;
+		};
+	};
+
+	apps_smmu: apps-smmu@0x15000000 {
+		compatible = "qcom,qsmmu-v500";
+		reg = <0x15000000 0x100000>,
+			<0x15182000 0x20>;
+		reg-names = "base", "tcu-base";
+		#iommu-cells = <2>;
+		qcom,skip-init;
+		qcom,use-3-lvl-tables;
+		qcom,disable-atos;
+		qcom,min-iova-align;
+		#global-interrupts = <1>;
+		#size-cells = <1>;
+		#address-cells = <1>;
+		ranges;
+		interrupts =	<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
+
+		interconnects = <&system_noc MASTER_GEM_NOC_SNOC
+				&config_noc SLAVE_IMEM_CFG>;
+		qcom,active-only;
+
+		anoc_1_tbu: anoc_1_tbu@0x15185000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x15185000 0x1000>,
+				<0x15182200 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x0 0x400>;
+			qcom,regulator-names = "vdd";
+			vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu1_gdsc>;
+			qcom,active-only;
+			interconnects = <&system_noc MASTER_GEM_NOC_SNOC
+					&config_noc SLAVE_IMEM_CFG>;
+		};
+
+		anoc_2_tbu: anoc_2_tbu@0x15189000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x15189000 0x1000>,
+				<0x15182208 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x400 0x400>;
+			qcom,regulator-names = "vdd";
+			vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu2_gdsc>;
+			qcom,active-only;
+			interconnects = <&system_noc MASTER_GEM_NOC_SNOC
+					&config_noc SLAVE_IMEM_CFG>;
+
+		};
+
+		mnoc_hf_0_tbu: mnoc_hf_0_tbu@0x1518D000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x1518D000 0x1000>,
+				<0x15182210 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x800 0x400>;
+			qcom,regulator-names = "vdd";
+			vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>;
+			qcom,active-only;
+			interconnects = <&mmss_noc MASTER_MDP0
+					 &mmss_noc SLAVE_MNOC_HF_MEM_NOC>;
+		};
+
+		mnoc_hf_1_tbu: mnoc_hf_1_tbu@0x15191000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x15191000 0x1000>,
+				<0x15182218 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0xc00 0x400>;
+			qcom,regulator-names = "vdd";
+			vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc>;
+			qcom,active-only;
+			interconnects = <&mmss_noc MASTER_MDP0
+					 &mmss_noc SLAVE_MNOC_HF_MEM_NOC>;
+		};
+
+		mnoc_sf_0_tbu: mnoc_sf_0_tbu@0x15195000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x15195000 0x1000>,
+				<0x15182220 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x1000 0x400>;
+			qcom,regulator-names = "vdd";
+			vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc>;
+			qcom,active-only;
+			interconnects = <&mmss_noc MASTER_CAMNOC_SF
+					 &mmss_noc SLAVE_MNOC_SF_MEM_NOC>;
+		};
+
+		compute_dsp_0_tbu: compute_dsp_0_tbu@0x15199000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x15199000 0x1000>,
+				<0x15182228 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x1400 0x400>;
+			/* No GDSC */
+			interconnects = <&compute_noc MASTER_NPU
+					 &compute_noc SLAVE_CDSP_MEM_NOC>;
+		};
+
+		adsp_tbu: adsp_tbu@0x1519D000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x1519D000 0x1000>,
+				<0x15182230 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x1800 0x400>;
+			qcom,regulator-names = "vdd";
+			vdd-supply = <&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc>;
+			qcom,active-only;
+			interconnects = <&system_noc MASTER_GEM_NOC_SNOC
+					&config_noc SLAVE_IMEM_CFG>;
+		};
+
+		anoc_1_pcie_tbu: anoc_1_pcie_tbu@0x151A1000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151A1000 0x1000>,
+				<0x15182238 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x1c00 0x400>;
+			qcom,opt-out-tbu-halting;
+			qcom,regulator-names = "vdd";
+			vdd-supply = <&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc>;
+			clock-names = "gcc_aggre_noc_pcie_tbu_clk";
+			clocks = <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
+			qcom,active-only;
+			interconnects = <&system_noc MASTER_GEM_NOC_SNOC
+					&config_noc SLAVE_IMEM_CFG>;
+		};
+
+		compute_dsp_1_tbu: compute_dsp_1_tbu@0x151A5000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151A5000 0x1000>,
+				<0x15182240 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x2000 0x400>;
+			/* No GDSC */
+			qcom,active-only;
+			interconnects = <&compute_noc MASTER_NPU
+					 &compute_noc SLAVE_CDSP_MEM_NOC>;
+		};
+	};
+
+	kgsl_iommu_test_device {
+		compatible = "iommu-debug-test";
+		iommus = <&kgsl_smmu 0x7 0>;
+		qcom,iommu-dma = "disabled";
+	};
+
+	kgsl_iommu_coherent_test_device {
+		compatible = "iommu-debug-test";
+		iommus = <&kgsl_smmu 0x9 0>;
+		qcom,iommu-dma = "disabled";
+		dma-coherent;
+	};
+
+	apps_iommu_test_device {
+		compatible = "iommu-debug-test";
+		iommus = <&apps_smmu 0x21 0>;
+		qcom,iommu-dma = "disabled";
+	};
+
+	apps_iommu_coherent_test_device {
+		compatible = "iommu-debug-test";
+		iommus = <&apps_smmu 0x23 0>;
+		qcom,iommu-dma = "disabled";
+		dma-coherent;
+	};
+};
+
+&kgsl_smmu {
+	qcom,actlr =
+		/* All CBs of GFX: +15 deep PF */
+		<0x0 0x407 0x303>;
+};
+
+&apps_smmu {
+	qcom,actlr =
+		/* SIDs 0x1460 - 0x1463 of NPU: +3 deep PF */
+		<0x1460 0x3 0x103>,
+
+		/* SIDs 0x1464 - 0x1465 of NPU: +3 deep PF */
+		<0x1464 0x1 0x103>,
+
+		/* SIDs 0x2060 - 0x2063 of NPU: +3 deep PF */
+		<0x2060 0x3 0x103>,
+
+		/* SIDs 0x2064 - 0x2065 of NPU: +3 deep PF */
+		<0x2064 0x1 0x103>,
+
+		/* Display SIDs: +3 deep PF */
+		<0x0800 0x0420 0x103>,
+		<0x0801 0x0420 0x103>,
+		<0x1040 0x0001 0x103>,
+
+		/* Video SIDs: +3 deep PF */
+		<0x1300 0x0060 0x103>,
+		<0x1301 0x0004 0x103>,
+		<0x1303 0x0020 0x103>,
+		<0x1304 0x0060 0x103>,
+		<0x1342 0x0000 0x103>;
+};
diff --git a/qcom/sm8150-v2.dtsi b/qcom/sm8150-v2.dtsi
index a7ec31ec4fa3..a6f26d35f304 100644
--- a/qcom/sm8150-v2.dtsi
+++ b/qcom/sm8150-v2.dtsi
@@ -6,6 +6,10 @@
 	qcom,msm-id = <339 0x20000>;
 };
 
+/* Remove smmu nodes specific to SM8150 */
+/delete-node/ &apps_smmu;
+/delete-node/ &kgsl_smmu;
+
 &gcc {
 	compatible = "qcom,sm8150-gcc-v2", "syscon";
 };
@@ -29,3 +33,5 @@
 &scc {
 	compatible = "qcom,sm8150-scc-v2", "syscon";
 };
+
+#include "msm-arm-smmu-sm8150-v2.dtsi"
diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi
index 28a139213f08..961e4e0fb6e2 100644
--- a/qcom/sm8150.dtsi
+++ b/qcom/sm8150.dtsi
@@ -1505,6 +1505,7 @@
 #include "sm8150-slpi-pinctrl.dtsi"
 #include "sm8150-smp2p.dtsi"
 #include "sm8150-gdsc.dtsi"
+#include "msm-arm-smmu-sm8150.dtsi"
 
 &emac_gdsc {
 	status = "ok";