Merge "ARM: dts: qcom: Update limit-rate and add limit-phy-submode on Lahaina"

This commit is contained in:
qctecmdr 2020-02-05 05:46:23 -08:00 • committed by Gerrit - the friendly Code Review server
commit 1351fca9db
3 changed files with 6 additions and 2 deletions

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@ -35,7 +35,10 @@ Optional properties:
- vddp-ref-clk-max-microamp : specifies max. load that can be drawn from this supply
- resets : specifies the PHY reset in the UFS controller
- limit-rate : specifies if the rate has to be limited to A or B.
1 = rate B, 0 = rate A.
1 = rate A, 2 = rate B.
- limit-phy-submode : specifies the PHY submode which is used for PHY calibration,
0 = non-G4, 1 = G4.
Example:
ufsphy1: ufsphy@fc597000 {

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@ -27,7 +27,7 @@
&ufshc_mem {
limit-tx-hs-gear = <1>;
limit-rx-hs-gear = <1>;
limit-rate = <1>;
limit-rate = <2>; /* HS Rate-B */
vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
vdd-hba-fixed-regulator;

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@ -1422,6 +1422,7 @@
phys = <&ufsphy_mem>;
phy-names = "ufsphy";
lanes-per-direction = <2>;
limit-rate = <1>; /* HS Rate-A */
dev-ref-clk-freq = <0>; /* 19.2 MHz */
clock-names =