mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-09 13:49:24 -04:00
drm for v4.18-rc1
-----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJbFzauAAoJEAx081l5xIa+jzwP/AwfTreH3XBmlLeMO8kwkAMW AiH1u3KHrlitN1U85x90dC8hVuuV2Kv9pEXQo1me/TAL/QCb9VZYCSf2dHHkkMwD 1UdwxAQW7soBbTRo9k0zuVJpRGSYIiYfqDh3L6KmTC3UF0tUJm53VOWCLG/DNrtn XhEnGnlCUNbABZMMpavEvlwxPtvaYFlp6M+MmwRPIx32SrPJ3vSaBzxwWxOaFmjU xiRdK+GpAbCV8yGeCCSkDgEe/TdWGUhZxoC9dLb0H9ex7ip8uZ0W4D+VTHPFrhQX 6nCpqUbp7BQTsbVSd1pAVsAv45scmSgWbKcqfC0NKSVcsHcJZBR0tQOF9OvnGZcf o1Hv/beTqJ++IcG2rEIwyJTGxAGfZ0YSb0evTC9VcszaYo+b3+G283bdztIjzDeS 0QCTeLHYbZRHPITWVULNpMWy3TkJv32IdFhQfYSnD8/OGQIxLNhh4FFOtHnOmxSF N8dnzOLKXhXMo/NgOL+UMNnbgLqIyOtEXCPDLuOQJNv/SOp8662m/A0yRjQNR6M2 gsPmR7dxQIwwJMyqrkLDOF411ABZohulquYgwLgG938MRPmTpPWOR72PtpGF4hAW HLg+3HHBd1N/A1mlJUMAbUn2eMUACZBUIycE9u+U/geRgve/OQnzJH/FKGP2EJ4R pf6CruEva+6GRR5GVzuM =twst -----END PGP SIGNATURE----- Merge tag 'drm-next-2018-06-06-1' of git://anongit.freedesktop.org/drm/drm Pull drm updates from Dave Airlie: "This starts to support NVIDIA volta hardware with nouveau, and adds amdgpu support for the GPU in the Kabylake-G (the intel + radeon single package chip), along with some initial Intel icelake enabling. Summary: New Drivers: - v3d - driver for broadcom V3D V3.x+ hardware - xen-front - XEN PV display frontend core: - handle zpos normalization in the core - stop looking at legacy pointers in atomic paths - improved scheduler documentation - improved aspect ratio validation - aspect ratio support for 64:27 and 256:135 - drop unused control node code. i915: - Icelake (ICL) enabling - GuC/HuC refactoring - PSR/PSR2 enabling and fixes - DPLL management refactoring - DP MST fixes - NV12 enabling - HDCP improvements - GEM/Execlist/reset improvements - GVT improvements - stolen memory first 4k fix amdgpu: - Vega 20 support - VEGAM support (Kabylake-G) - preOS scanout buffer reservation - power management gfxoff support for raven - SR-IOV fixes - Vega10 power profiles and clock voltage control - scatter/gather display support on CZ/ST amdkfd: - GFX9 dGPU support - userptr memory mapping nouveau: - major refactoring for Volta GV100 support tda998x: - HDMI i2c CEC support etnaviv: - removed unused logging code - license text cleanups - MMU handling improvements - timeout fence fix for 50 days uptime tegra: - IOMMU support in gr2d/gr3d drivers - zpos support vc4: - syncobj support - CTM, plane alpha and async cursor support analogix_dp: - HPD and aux chan fixes sun4i: - MIPI DSI support tilcdc: - clock divider fixes for OMAP-l138 LCDK board rcar-du: - R8A77965 support - dma-buf fences fixes - hardware indexed crtc/du group handling - generic zplane property support atmel-hclcdc: - generic zplane property support mediatek: - use generic video mode function exynos: - S5PV210 FIMD variant support - IPP v2 framework - more HW overlays support" * tag 'drm-next-2018-06-06-1' of git://anongit.freedesktop.org/drm/drm: (1286 commits) drm/amdgpu: fix 32-bit build warning drm/exynos: fimc: signedness bug in fimc_setup_clocks() drm/exynos: scaler: fix static checker warning drm/amdgpu: Use dev_info() to report amdkfd is not supported for this ASIC drm/amd/display: Remove use of division operator for long longs drm/amdgpu: Update GFX info structure to match what vega20 used drm/amdgpu/pp: remove duplicate assignment drm/sched: add rcu_barrier after entity fini drm/amdgpu: move VM BOs on LRU again drm/amdgpu: consistenly use VM moved flag drm/amdgpu: kmap PDs/PTs in amdgpu_vm_update_directories drm/amdgpu: further optimize amdgpu_vm_handle_moved drm/amdgpu: cleanup amdgpu_vm_validate_pt_bos v2 drm/amdgpu: rework VM state machine lock handling v2 drm/amdgpu: Add runtime VCN PG support drm/amdgpu: Enable VCN static PG by default on RV drm/amdgpu: Add VCN static PG support on RV drm/amdgpu: Enable VCN CG by default on RV drm/amdgpu: Add static CG control for VCN on RV drm/exynos: Fix default value for zpos plane property ...
This commit is contained in:
Linus Torvalds
commit
135c5504a6
1110 changed files with 72647 additions and 26344 deletions
|
|
@ -78,6 +78,12 @@ extern "C" {
|
|||
#define AMDGPU_GEM_DOMAIN_GDS 0x8
|
||||
#define AMDGPU_GEM_DOMAIN_GWS 0x10
|
||||
#define AMDGPU_GEM_DOMAIN_OA 0x20
|
||||
#define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \
|
||||
AMDGPU_GEM_DOMAIN_GTT | \
|
||||
AMDGPU_GEM_DOMAIN_VRAM | \
|
||||
AMDGPU_GEM_DOMAIN_GDS | \
|
||||
AMDGPU_GEM_DOMAIN_GWS | \
|
||||
AMDGPU_GEM_DOMAIN_OA)
|
||||
|
||||
/* Flag that CPU access will be required for the case of VRAM domain */
|
||||
#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
|
||||
|
|
@ -95,6 +101,10 @@ extern "C" {
|
|||
#define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)
|
||||
/* Flag that BO sharing will be explicitly synchronized */
|
||||
#define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7)
|
||||
/* Flag that indicates allocating MQD gart on GFX9, where the mtype
|
||||
* for the second page onward should be set to NC.
|
||||
*/
|
||||
#define AMDGPU_GEM_CREATE_MQD_GFX9 (1 << 8)
|
||||
|
||||
struct drm_amdgpu_gem_create_in {
|
||||
/** the requested memory size */
|
||||
|
|
@ -520,6 +530,10 @@ union drm_amdgpu_cs {
|
|||
/* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */
|
||||
#define AMDGPU_IB_FLAG_PREEMPT (1<<2)
|
||||
|
||||
/* The IB fence should do the L2 writeback but not invalidate any shader
|
||||
* caches (L2/vL1/sL1/I$). */
|
||||
#define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)
|
||||
|
||||
struct drm_amdgpu_cs_chunk_ib {
|
||||
__u32 _pad;
|
||||
/** AMDGPU_IB_FLAG_* */
|
||||
|
|
@ -620,6 +634,12 @@ struct drm_amdgpu_cs_chunk_data {
|
|||
#define AMDGPU_INFO_FW_ASD 0x0d
|
||||
/* Subquery id: Query VCN firmware version */
|
||||
#define AMDGPU_INFO_FW_VCN 0x0e
|
||||
/* Subquery id: Query GFX RLC SRLC firmware version */
|
||||
#define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f
|
||||
/* Subquery id: Query GFX RLC SRLG firmware version */
|
||||
#define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10
|
||||
/* Subquery id: Query GFX RLC SRLS firmware version */
|
||||
#define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11
|
||||
/* number of bytes moved for TTM migration */
|
||||
#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
|
||||
/* the used VRAM size */
|
||||
|
|
|
|||
|
|
@ -680,6 +680,13 @@ struct drm_get_cap {
|
|||
*/
|
||||
#define DRM_CLIENT_CAP_ATOMIC 3
|
||||
|
||||
/**
|
||||
* DRM_CLIENT_CAP_ASPECT_RATIO
|
||||
*
|
||||
* If set to 1, the DRM core will provide aspect ratio information in modes.
|
||||
*/
|
||||
#define DRM_CLIENT_CAP_ASPECT_RATIO 4
|
||||
|
||||
/** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */
|
||||
struct drm_set_client_cap {
|
||||
__u64 capability;
|
||||
|
|
|
|||
|
|
@ -93,6 +93,8 @@ extern "C" {
|
|||
#define DRM_MODE_PICTURE_ASPECT_NONE 0
|
||||
#define DRM_MODE_PICTURE_ASPECT_4_3 1
|
||||
#define DRM_MODE_PICTURE_ASPECT_16_9 2
|
||||
#define DRM_MODE_PICTURE_ASPECT_64_27 3
|
||||
#define DRM_MODE_PICTURE_ASPECT_256_135 4
|
||||
|
||||
/* Aspect ratio flag bitmask (4 bits 22:19) */
|
||||
#define DRM_MODE_FLAG_PIC_AR_MASK (0x0F<<19)
|
||||
|
|
@ -102,6 +104,10 @@ extern "C" {
|
|||
(DRM_MODE_PICTURE_ASPECT_4_3<<19)
|
||||
#define DRM_MODE_FLAG_PIC_AR_16_9 \
|
||||
(DRM_MODE_PICTURE_ASPECT_16_9<<19)
|
||||
#define DRM_MODE_FLAG_PIC_AR_64_27 \
|
||||
(DRM_MODE_PICTURE_ASPECT_64_27<<19)
|
||||
#define DRM_MODE_FLAG_PIC_AR_256_135 \
|
||||
(DRM_MODE_PICTURE_ASPECT_256_135<<19)
|
||||
|
||||
#define DRM_MODE_FLAG_ALL (DRM_MODE_FLAG_PHSYNC | \
|
||||
DRM_MODE_FLAG_NHSYNC | \
|
||||
|
|
|
|||
|
|
@ -135,6 +135,219 @@ struct drm_exynos_g2d_exec {
|
|||
__u64 async;
|
||||
};
|
||||
|
||||
/* Exynos DRM IPP v2 API */
|
||||
|
||||
/**
|
||||
* Enumerate available IPP hardware modules.
|
||||
*
|
||||
* @count_ipps: size of ipp_id array / number of ipp modules (set by driver)
|
||||
* @reserved: padding
|
||||
* @ipp_id_ptr: pointer to ipp_id array or NULL
|
||||
*/
|
||||
struct drm_exynos_ioctl_ipp_get_res {
|
||||
__u32 count_ipps;
|
||||
__u32 reserved;
|
||||
__u64 ipp_id_ptr;
|
||||
};
|
||||
|
||||
enum drm_exynos_ipp_format_type {
|
||||
DRM_EXYNOS_IPP_FORMAT_SOURCE = 0x01,
|
||||
DRM_EXYNOS_IPP_FORMAT_DESTINATION = 0x02,
|
||||
};
|
||||
|
||||
struct drm_exynos_ipp_format {
|
||||
__u32 fourcc;
|
||||
__u32 type;
|
||||
__u64 modifier;
|
||||
};
|
||||
|
||||
enum drm_exynos_ipp_capability {
|
||||
DRM_EXYNOS_IPP_CAP_CROP = 0x01,
|
||||
DRM_EXYNOS_IPP_CAP_ROTATE = 0x02,
|
||||
DRM_EXYNOS_IPP_CAP_SCALE = 0x04,
|
||||
DRM_EXYNOS_IPP_CAP_CONVERT = 0x08,
|
||||
};
|
||||
|
||||
/**
|
||||
* Get IPP hardware capabilities and supported image formats.
|
||||
*
|
||||
* @ipp_id: id of IPP module to query
|
||||
* @capabilities: bitmask of drm_exynos_ipp_capability (set by driver)
|
||||
* @reserved: padding
|
||||
* @formats_count: size of formats array (in entries) / number of filled
|
||||
* formats (set by driver)
|
||||
* @formats_ptr: pointer to formats array or NULL
|
||||
*/
|
||||
struct drm_exynos_ioctl_ipp_get_caps {
|
||||
__u32 ipp_id;
|
||||
__u32 capabilities;
|
||||
__u32 reserved;
|
||||
__u32 formats_count;
|
||||
__u64 formats_ptr;
|
||||
};
|
||||
|
||||
enum drm_exynos_ipp_limit_type {
|
||||
/* size (horizontal/vertial) limits, in pixels (min, max, alignment) */
|
||||
DRM_EXYNOS_IPP_LIMIT_TYPE_SIZE = 0x0001,
|
||||
/* scale ratio (horizonta/vertial), 16.16 fixed point (min, max) */
|
||||
DRM_EXYNOS_IPP_LIMIT_TYPE_SCALE = 0x0002,
|
||||
|
||||
/* image buffer area */
|
||||
DRM_EXYNOS_IPP_LIMIT_SIZE_BUFFER = 0x0001 << 16,
|
||||
/* src/dst rectangle area */
|
||||
DRM_EXYNOS_IPP_LIMIT_SIZE_AREA = 0x0002 << 16,
|
||||
/* src/dst rectangle area when rotation enabled */
|
||||
DRM_EXYNOS_IPP_LIMIT_SIZE_ROTATED = 0x0003 << 16,
|
||||
|
||||
DRM_EXYNOS_IPP_LIMIT_TYPE_MASK = 0x000f,
|
||||
DRM_EXYNOS_IPP_LIMIT_SIZE_MASK = 0x000f << 16,
|
||||
};
|
||||
|
||||
struct drm_exynos_ipp_limit_val {
|
||||
__u32 min;
|
||||
__u32 max;
|
||||
__u32 align;
|
||||
__u32 reserved;
|
||||
};
|
||||
|
||||
/**
|
||||
* IPP module limitation.
|
||||
*
|
||||
* @type: limit type (see drm_exynos_ipp_limit_type enum)
|
||||
* @reserved: padding
|
||||
* @h: horizontal limits
|
||||
* @v: vertical limits
|
||||
*/
|
||||
struct drm_exynos_ipp_limit {
|
||||
__u32 type;
|
||||
__u32 reserved;
|
||||
struct drm_exynos_ipp_limit_val h;
|
||||
struct drm_exynos_ipp_limit_val v;
|
||||
};
|
||||
|
||||
/**
|
||||
* Get IPP limits for given image format.
|
||||
*
|
||||
* @ipp_id: id of IPP module to query
|
||||
* @fourcc: image format code (see DRM_FORMAT_* in drm_fourcc.h)
|
||||
* @modifier: image format modifier (see DRM_FORMAT_MOD_* in drm_fourcc.h)
|
||||
* @type: source/destination identifier (drm_exynos_ipp_format_flag enum)
|
||||
* @limits_count: size of limits array (in entries) / number of filled entries
|
||||
* (set by driver)
|
||||
* @limits_ptr: pointer to limits array or NULL
|
||||
*/
|
||||
struct drm_exynos_ioctl_ipp_get_limits {
|
||||
__u32 ipp_id;
|
||||
__u32 fourcc;
|
||||
__u64 modifier;
|
||||
__u32 type;
|
||||
__u32 limits_count;
|
||||
__u64 limits_ptr;
|
||||
};
|
||||
|
||||
enum drm_exynos_ipp_task_id {
|
||||
/* buffer described by struct drm_exynos_ipp_task_buffer */
|
||||
DRM_EXYNOS_IPP_TASK_BUFFER = 0x0001,
|
||||
/* rectangle described by struct drm_exynos_ipp_task_rect */
|
||||
DRM_EXYNOS_IPP_TASK_RECTANGLE = 0x0002,
|
||||
/* transformation described by struct drm_exynos_ipp_task_transform */
|
||||
DRM_EXYNOS_IPP_TASK_TRANSFORM = 0x0003,
|
||||
/* alpha configuration described by struct drm_exynos_ipp_task_alpha */
|
||||
DRM_EXYNOS_IPP_TASK_ALPHA = 0x0004,
|
||||
|
||||
/* source image data (for buffer and rectangle chunks) */
|
||||
DRM_EXYNOS_IPP_TASK_TYPE_SOURCE = 0x0001 << 16,
|
||||
/* destination image data (for buffer and rectangle chunks) */
|
||||
DRM_EXYNOS_IPP_TASK_TYPE_DESTINATION = 0x0002 << 16,
|
||||
};
|
||||
|
||||
/**
|
||||
* Memory buffer with image data.
|
||||
*
|
||||
* @id: must be DRM_EXYNOS_IPP_TASK_BUFFER
|
||||
* other parameters are same as for AddFB2 generic DRM ioctl
|
||||
*/
|
||||
struct drm_exynos_ipp_task_buffer {
|
||||
__u32 id;
|
||||
__u32 fourcc;
|
||||
__u32 width, height;
|
||||
__u32 gem_id[4];
|
||||
__u32 offset[4];
|
||||
__u32 pitch[4];
|
||||
__u64 modifier;
|
||||
};
|
||||
|
||||
/**
|
||||
* Rectangle for processing.
|
||||
*
|
||||
* @id: must be DRM_EXYNOS_IPP_TASK_RECTANGLE
|
||||
* @reserved: padding
|
||||
* @x,@y: left corner in pixels
|
||||
* @w,@h: width/height in pixels
|
||||
*/
|
||||
struct drm_exynos_ipp_task_rect {
|
||||
__u32 id;
|
||||
__u32 reserved;
|
||||
__u32 x;
|
||||
__u32 y;
|
||||
__u32 w;
|
||||
__u32 h;
|
||||
};
|
||||
|
||||
/**
|
||||
* Image tranformation description.
|
||||
*
|
||||
* @id: must be DRM_EXYNOS_IPP_TASK_TRANSFORM
|
||||
* @rotation: DRM_MODE_ROTATE_* and DRM_MODE_REFLECT_* values
|
||||
*/
|
||||
struct drm_exynos_ipp_task_transform {
|
||||
__u32 id;
|
||||
__u32 rotation;
|
||||
};
|
||||
|
||||
/**
|
||||
* Image global alpha configuration for formats without alpha values.
|
||||
*
|
||||
* @id: must be DRM_EXYNOS_IPP_TASK_ALPHA
|
||||
* @value: global alpha value (0-255)
|
||||
*/
|
||||
struct drm_exynos_ipp_task_alpha {
|
||||
__u32 id;
|
||||
__u32 value;
|
||||
};
|
||||
|
||||
enum drm_exynos_ipp_flag {
|
||||
/* generate DRM event after processing */
|
||||
DRM_EXYNOS_IPP_FLAG_EVENT = 0x01,
|
||||
/* dry run, only check task parameters */
|
||||
DRM_EXYNOS_IPP_FLAG_TEST_ONLY = 0x02,
|
||||
/* non-blocking processing */
|
||||
DRM_EXYNOS_IPP_FLAG_NONBLOCK = 0x04,
|
||||
};
|
||||
|
||||
#define DRM_EXYNOS_IPP_FLAGS (DRM_EXYNOS_IPP_FLAG_EVENT |\
|
||||
DRM_EXYNOS_IPP_FLAG_TEST_ONLY | DRM_EXYNOS_IPP_FLAG_NONBLOCK)
|
||||
|
||||
/**
|
||||
* Perform image processing described by array of drm_exynos_ipp_task_*
|
||||
* structures (parameters array).
|
||||
*
|
||||
* @ipp_id: id of IPP module to run the task
|
||||
* @flags: bitmask of drm_exynos_ipp_flag values
|
||||
* @reserved: padding
|
||||
* @params_size: size of parameters array (in bytes)
|
||||
* @params_ptr: pointer to parameters array or NULL
|
||||
* @user_data: (optional) data for drm event
|
||||
*/
|
||||
struct drm_exynos_ioctl_ipp_commit {
|
||||
__u32 ipp_id;
|
||||
__u32 flags;
|
||||
__u32 reserved;
|
||||
__u32 params_size;
|
||||
__u64 params_ptr;
|
||||
__u64 user_data;
|
||||
};
|
||||
|
||||
#define DRM_EXYNOS_GEM_CREATE 0x00
|
||||
#define DRM_EXYNOS_GEM_MAP 0x01
|
||||
/* Reserved 0x03 ~ 0x05 for exynos specific gem ioctl */
|
||||
|
|
@ -147,6 +360,11 @@ struct drm_exynos_g2d_exec {
|
|||
#define DRM_EXYNOS_G2D_EXEC 0x22
|
||||
|
||||
/* Reserved 0x30 ~ 0x33 for obsolete Exynos IPP ioctls */
|
||||
/* IPP - Image Post Processing */
|
||||
#define DRM_EXYNOS_IPP_GET_RESOURCES 0x40
|
||||
#define DRM_EXYNOS_IPP_GET_CAPS 0x41
|
||||
#define DRM_EXYNOS_IPP_GET_LIMITS 0x42
|
||||
#define DRM_EXYNOS_IPP_COMMIT 0x43
|
||||
|
||||
#define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \
|
||||
DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create)
|
||||
|
|
@ -165,8 +383,20 @@ struct drm_exynos_g2d_exec {
|
|||
#define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + \
|
||||
DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec)
|
||||
|
||||
#define DRM_IOCTL_EXYNOS_IPP_GET_RESOURCES DRM_IOWR(DRM_COMMAND_BASE + \
|
||||
DRM_EXYNOS_IPP_GET_RESOURCES, \
|
||||
struct drm_exynos_ioctl_ipp_get_res)
|
||||
#define DRM_IOCTL_EXYNOS_IPP_GET_CAPS DRM_IOWR(DRM_COMMAND_BASE + \
|
||||
DRM_EXYNOS_IPP_GET_CAPS, struct drm_exynos_ioctl_ipp_get_caps)
|
||||
#define DRM_IOCTL_EXYNOS_IPP_GET_LIMITS DRM_IOWR(DRM_COMMAND_BASE + \
|
||||
DRM_EXYNOS_IPP_GET_LIMITS, \
|
||||
struct drm_exynos_ioctl_ipp_get_limits)
|
||||
#define DRM_IOCTL_EXYNOS_IPP_COMMIT DRM_IOWR(DRM_COMMAND_BASE + \
|
||||
DRM_EXYNOS_IPP_COMMIT, struct drm_exynos_ioctl_ipp_commit)
|
||||
|
||||
/* EXYNOS specific events */
|
||||
#define DRM_EXYNOS_G2D_EVENT 0x80000000
|
||||
#define DRM_EXYNOS_IPP_EVENT 0x80000002
|
||||
|
||||
struct drm_exynos_g2d_event {
|
||||
struct drm_event base;
|
||||
|
|
@ -177,6 +407,16 @@ struct drm_exynos_g2d_event {
|
|||
__u32 reserved;
|
||||
};
|
||||
|
||||
struct drm_exynos_ipp_event {
|
||||
struct drm_event base;
|
||||
__u64 user_data;
|
||||
__u32 tv_sec;
|
||||
__u32 tv_usec;
|
||||
__u32 ipp_id;
|
||||
__u32 sequence;
|
||||
__u64 reserved;
|
||||
};
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -32,143 +32,615 @@ extern "C" {
|
|||
#define DRM_TEGRA_GEM_CREATE_TILED (1 << 0)
|
||||
#define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1)
|
||||
|
||||
/**
|
||||
* struct drm_tegra_gem_create - parameters for the GEM object creation IOCTL
|
||||
*/
|
||||
struct drm_tegra_gem_create {
|
||||
/**
|
||||
* @size:
|
||||
*
|
||||
* The size, in bytes, of the buffer object to be created.
|
||||
*/
|
||||
__u64 size;
|
||||
|
||||
/**
|
||||
* @flags:
|
||||
*
|
||||
* A bitmask of flags that influence the creation of GEM objects:
|
||||
*
|
||||
* DRM_TEGRA_GEM_CREATE_TILED
|
||||
* Use the 16x16 tiling format for this buffer.
|
||||
*
|
||||
* DRM_TEGRA_GEM_CREATE_BOTTOM_UP
|
||||
* The buffer has a bottom-up layout.
|
||||
*/
|
||||
__u32 flags;
|
||||
|
||||
/**
|
||||
* @handle:
|
||||
*
|
||||
* The handle of the created GEM object. Set by the kernel upon
|
||||
* successful completion of the IOCTL.
|
||||
*/
|
||||
__u32 handle;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_gem_mmap - parameters for the GEM mmap IOCTL
|
||||
*/
|
||||
struct drm_tegra_gem_mmap {
|
||||
/**
|
||||
* @handle:
|
||||
*
|
||||
* Handle of the GEM object to obtain an mmap offset for.
|
||||
*/
|
||||
__u32 handle;
|
||||
|
||||
/**
|
||||
* @pad:
|
||||
*
|
||||
* Structure padding that may be used in the future. Must be 0.
|
||||
*/
|
||||
__u32 pad;
|
||||
|
||||
/**
|
||||
* @offset:
|
||||
*
|
||||
* The mmap offset for the given GEM object. Set by the kernel upon
|
||||
* successful completion of the IOCTL.
|
||||
*/
|
||||
__u64 offset;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_syncpt_read - parameters for the read syncpoint IOCTL
|
||||
*/
|
||||
struct drm_tegra_syncpt_read {
|
||||
/**
|
||||
* @id:
|
||||
*
|
||||
* ID of the syncpoint to read the current value from.
|
||||
*/
|
||||
__u32 id;
|
||||
|
||||
/**
|
||||
* @value:
|
||||
*
|
||||
* The current syncpoint value. Set by the kernel upon successful
|
||||
* completion of the IOCTL.
|
||||
*/
|
||||
__u32 value;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_syncpt_incr - parameters for the increment syncpoint IOCTL
|
||||
*/
|
||||
struct drm_tegra_syncpt_incr {
|
||||
/**
|
||||
* @id:
|
||||
*
|
||||
* ID of the syncpoint to increment.
|
||||
*/
|
||||
__u32 id;
|
||||
|
||||
/**
|
||||
* @pad:
|
||||
*
|
||||
* Structure padding that may be used in the future. Must be 0.
|
||||
*/
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_syncpt_wait - parameters for the wait syncpoint IOCTL
|
||||
*/
|
||||
struct drm_tegra_syncpt_wait {
|
||||
/**
|
||||
* @id:
|
||||
*
|
||||
* ID of the syncpoint to wait on.
|
||||
*/
|
||||
__u32 id;
|
||||
|
||||
/**
|
||||
* @thresh:
|
||||
*
|
||||
* Threshold value for which to wait.
|
||||
*/
|
||||
__u32 thresh;
|
||||
|
||||
/**
|
||||
* @timeout:
|
||||
*
|
||||
* Timeout, in milliseconds, to wait.
|
||||
*/
|
||||
__u32 timeout;
|
||||
|
||||
/**
|
||||
* @value:
|
||||
*
|
||||
* The new syncpoint value after the wait. Set by the kernel upon
|
||||
* successful completion of the IOCTL.
|
||||
*/
|
||||
__u32 value;
|
||||
};
|
||||
|
||||
#define DRM_TEGRA_NO_TIMEOUT (0xffffffff)
|
||||
|
||||
/**
|
||||
* struct drm_tegra_open_channel - parameters for the open channel IOCTL
|
||||
*/
|
||||
struct drm_tegra_open_channel {
|
||||
/**
|
||||
* @client:
|
||||
*
|
||||
* The client ID for this channel.
|
||||
*/
|
||||
__u32 client;
|
||||
|
||||
/**
|
||||
* @pad:
|
||||
*
|
||||
* Structure padding that may be used in the future. Must be 0.
|
||||
*/
|
||||
__u32 pad;
|
||||
|
||||
/**
|
||||
* @context:
|
||||
*
|
||||
* The application context of this channel. Set by the kernel upon
|
||||
* successful completion of the IOCTL. This context needs to be passed
|
||||
* to the DRM_TEGRA_CHANNEL_CLOSE or the DRM_TEGRA_SUBMIT IOCTLs.
|
||||
*/
|
||||
__u64 context;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_close_channel - parameters for the close channel IOCTL
|
||||
*/
|
||||
struct drm_tegra_close_channel {
|
||||
/**
|
||||
* @context:
|
||||
*
|
||||
* The application context of this channel. This is obtained from the
|
||||
* DRM_TEGRA_OPEN_CHANNEL IOCTL.
|
||||
*/
|
||||
__u64 context;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_get_syncpt - parameters for the get syncpoint IOCTL
|
||||
*/
|
||||
struct drm_tegra_get_syncpt {
|
||||
/**
|
||||
* @context:
|
||||
*
|
||||
* The application context identifying the channel for which to obtain
|
||||
* the syncpoint ID.
|
||||
*/
|
||||
__u64 context;
|
||||
|
||||
/**
|
||||
* @index:
|
||||
*
|
||||
* Index of the client syncpoint for which to obtain the ID.
|
||||
*/
|
||||
__u32 index;
|
||||
|
||||
/**
|
||||
* @id:
|
||||
*
|
||||
* The ID of the given syncpoint. Set by the kernel upon successful
|
||||
* completion of the IOCTL.
|
||||
*/
|
||||
__u32 id;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_get_syncpt_base - parameters for the get wait base IOCTL
|
||||
*/
|
||||
struct drm_tegra_get_syncpt_base {
|
||||
/**
|
||||
* @context:
|
||||
*
|
||||
* The application context identifying for which channel to obtain the
|
||||
* wait base.
|
||||
*/
|
||||
__u64 context;
|
||||
|
||||
/**
|
||||
* @syncpt:
|
||||
*
|
||||
* ID of the syncpoint for which to obtain the wait base.
|
||||
*/
|
||||
__u32 syncpt;
|
||||
|
||||
/**
|
||||
* @id:
|
||||
*
|
||||
* The ID of the wait base corresponding to the client syncpoint. Set
|
||||
* by the kernel upon successful completion of the IOCTL.
|
||||
*/
|
||||
__u32 id;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_syncpt - syncpoint increment operation
|
||||
*/
|
||||
struct drm_tegra_syncpt {
|
||||
/**
|
||||
* @id:
|
||||
*
|
||||
* ID of the syncpoint to operate on.
|
||||
*/
|
||||
__u32 id;
|
||||
|
||||
/**
|
||||
* @incrs:
|
||||
*
|
||||
* Number of increments to perform for the syncpoint.
|
||||
*/
|
||||
__u32 incrs;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_cmdbuf - structure describing a command buffer
|
||||
*/
|
||||
struct drm_tegra_cmdbuf {
|
||||
/**
|
||||
* @handle:
|
||||
*
|
||||
* Handle to a GEM object containing the command buffer.
|
||||
*/
|
||||
__u32 handle;
|
||||
|
||||
/**
|
||||
* @offset:
|
||||
*
|
||||
* Offset, in bytes, into the GEM object identified by @handle at
|
||||
* which the command buffer starts.
|
||||
*/
|
||||
__u32 offset;
|
||||
|
||||
/**
|
||||
* @words:
|
||||
*
|
||||
* Number of 32-bit words in this command buffer.
|
||||
*/
|
||||
__u32 words;
|
||||
|
||||
/**
|
||||
* @pad:
|
||||
*
|
||||
* Structure padding that may be used in the future. Must be 0.
|
||||
*/
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_reloc - GEM object relocation structure
|
||||
*/
|
||||
struct drm_tegra_reloc {
|
||||
struct {
|
||||
/**
|
||||
* @cmdbuf.handle:
|
||||
*
|
||||
* Handle to the GEM object containing the command buffer for
|
||||
* which to perform this GEM object relocation.
|
||||
*/
|
||||
__u32 handle;
|
||||
|
||||
/**
|
||||
* @cmdbuf.offset:
|
||||
*
|
||||
* Offset, in bytes, into the command buffer at which to
|
||||
* insert the relocated address.
|
||||
*/
|
||||
__u32 offset;
|
||||
} cmdbuf;
|
||||
struct {
|
||||
/**
|
||||
* @target.handle:
|
||||
*
|
||||
* Handle to the GEM object to be relocated.
|
||||
*/
|
||||
__u32 handle;
|
||||
|
||||
/**
|
||||
* @target.offset:
|
||||
*
|
||||
* Offset, in bytes, into the target GEM object at which the
|
||||
* relocated data starts.
|
||||
*/
|
||||
__u32 offset;
|
||||
} target;
|
||||
|
||||
/**
|
||||
* @shift:
|
||||
*
|
||||
* The number of bits by which to shift relocated addresses.
|
||||
*/
|
||||
__u32 shift;
|
||||
|
||||
/**
|
||||
* @pad:
|
||||
*
|
||||
* Structure padding that may be used in the future. Must be 0.
|
||||
*/
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_waitchk - wait check structure
|
||||
*/
|
||||
struct drm_tegra_waitchk {
|
||||
/**
|
||||
* @handle:
|
||||
*
|
||||
* Handle to the GEM object containing a command stream on which to
|
||||
* perform the wait check.
|
||||
*/
|
||||
__u32 handle;
|
||||
|
||||
/**
|
||||
* @offset:
|
||||
*
|
||||
* Offset, in bytes, of the location in the command stream to perform
|
||||
* the wait check on.
|
||||
*/
|
||||
__u32 offset;
|
||||
|
||||
/**
|
||||
* @syncpt:
|
||||
*
|
||||
* ID of the syncpoint to wait check.
|
||||
*/
|
||||
__u32 syncpt;
|
||||
|
||||
/**
|
||||
* @thresh:
|
||||
*
|
||||
* Threshold value for which to check.
|
||||
*/
|
||||
__u32 thresh;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_submit - job submission structure
|
||||
*/
|
||||
struct drm_tegra_submit {
|
||||
/**
|
||||
* @context:
|
||||
*
|
||||
* The application context identifying the channel to use for the
|
||||
* execution of this job.
|
||||
*/
|
||||
__u64 context;
|
||||
__u32 num_syncpts;
|
||||
__u32 num_cmdbufs;
|
||||
__u32 num_relocs;
|
||||
__u32 num_waitchks;
|
||||
__u32 waitchk_mask;
|
||||
__u32 timeout;
|
||||
__u64 syncpts;
|
||||
__u64 cmdbufs;
|
||||
__u64 relocs;
|
||||
__u64 waitchks;
|
||||
__u32 fence; /* Return value */
|
||||
|
||||
__u32 reserved[5]; /* future expansion */
|
||||
/**
|
||||
* @num_syncpts:
|
||||
*
|
||||
* The number of syncpoints operated on by this job. This defines the
|
||||
* length of the array pointed to by @syncpts.
|
||||
*/
|
||||
__u32 num_syncpts;
|
||||
|
||||
/**
|
||||
* @num_cmdbufs:
|
||||
*
|
||||
* The number of command buffers to execute as part of this job. This
|
||||
* defines the length of the array pointed to by @cmdbufs.
|
||||
*/
|
||||
__u32 num_cmdbufs;
|
||||
|
||||
/**
|
||||
* @num_relocs:
|
||||
*
|
||||
* The number of relocations to perform before executing this job.
|
||||
* This defines the length of the array pointed to by @relocs.
|
||||
*/
|
||||
__u32 num_relocs;
|
||||
|
||||
/**
|
||||
* @num_waitchks:
|
||||
*
|
||||
* The number of wait checks to perform as part of this job. This
|
||||
* defines the length of the array pointed to by @waitchks.
|
||||
*/
|
||||
__u32 num_waitchks;
|
||||
|
||||
/**
|
||||
* @waitchk_mask:
|
||||
*
|
||||
* Bitmask of valid wait checks.
|
||||
*/
|
||||
__u32 waitchk_mask;
|
||||
|
||||
/**
|
||||
* @timeout:
|
||||
*
|
||||
* Timeout, in milliseconds, before this job is cancelled.
|
||||
*/
|
||||
__u32 timeout;
|
||||
|
||||
/**
|
||||
* @syncpts:
|
||||
*
|
||||
* A pointer to an array of &struct drm_tegra_syncpt structures that
|
||||
* specify the syncpoint operations performed as part of this job.
|
||||
* The number of elements in the array must be equal to the value
|
||||
* given by @num_syncpts.
|
||||
*/
|
||||
__u64 syncpts;
|
||||
|
||||
/**
|
||||
* @cmdbufs:
|
||||
*
|
||||
* A pointer to an array of &struct drm_tegra_cmdbuf structures that
|
||||
* define the command buffers to execute as part of this job. The
|
||||
* number of elements in the array must be equal to the value given
|
||||
* by @num_syncpts.
|
||||
*/
|
||||
__u64 cmdbufs;
|
||||
|
||||
/**
|
||||
* @relocs:
|
||||
*
|
||||
* A pointer to an array of &struct drm_tegra_reloc structures that
|
||||
* specify the relocations that need to be performed before executing
|
||||
* this job. The number of elements in the array must be equal to the
|
||||
* value given by @num_relocs.
|
||||
*/
|
||||
__u64 relocs;
|
||||
|
||||
/**
|
||||
* @waitchks:
|
||||
*
|
||||
* A pointer to an array of &struct drm_tegra_waitchk structures that
|
||||
* specify the wait checks to be performed while executing this job.
|
||||
* The number of elements in the array must be equal to the value
|
||||
* given by @num_waitchks.
|
||||
*/
|
||||
__u64 waitchks;
|
||||
|
||||
/**
|
||||
* @fence:
|
||||
*
|
||||
* The threshold of the syncpoint associated with this job after it
|
||||
* has been completed. Set by the kernel upon successful completion of
|
||||
* the IOCTL. This can be used with the DRM_TEGRA_SYNCPT_WAIT IOCTL to
|
||||
* wait for this job to be finished.
|
||||
*/
|
||||
__u32 fence;
|
||||
|
||||
/**
|
||||
* @reserved:
|
||||
*
|
||||
* This field is reserved for future use. Must be 0.
|
||||
*/
|
||||
__u32 reserved[5];
|
||||
};
|
||||
|
||||
#define DRM_TEGRA_GEM_TILING_MODE_PITCH 0
|
||||
#define DRM_TEGRA_GEM_TILING_MODE_TILED 1
|
||||
#define DRM_TEGRA_GEM_TILING_MODE_BLOCK 2
|
||||
|
||||
/**
|
||||
* struct drm_tegra_gem_set_tiling - parameters for the set tiling IOCTL
|
||||
*/
|
||||
struct drm_tegra_gem_set_tiling {
|
||||
/* input */
|
||||
/**
|
||||
* @handle:
|
||||
*
|
||||
* Handle to the GEM object for which to set the tiling parameters.
|
||||
*/
|
||||
__u32 handle;
|
||||
|
||||
/**
|
||||
* @mode:
|
||||
*
|
||||
* The tiling mode to set. Must be one of:
|
||||
*
|
||||
* DRM_TEGRA_GEM_TILING_MODE_PITCH
|
||||
* pitch linear format
|
||||
*
|
||||
* DRM_TEGRA_GEM_TILING_MODE_TILED
|
||||
* 16x16 tiling format
|
||||
*
|
||||
* DRM_TEGRA_GEM_TILING_MODE_BLOCK
|
||||
* 16Bx2 tiling format
|
||||
*/
|
||||
__u32 mode;
|
||||
|
||||
/**
|
||||
* @value:
|
||||
*
|
||||
* The value to set for the tiling mode parameter.
|
||||
*/
|
||||
__u32 value;
|
||||
|
||||
/**
|
||||
* @pad:
|
||||
*
|
||||
* Structure padding that may be used in the future. Must be 0.
|
||||
*/
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_gem_get_tiling - parameters for the get tiling IOCTL
|
||||
*/
|
||||
struct drm_tegra_gem_get_tiling {
|
||||
/* input */
|
||||
/**
|
||||
* @handle:
|
||||
*
|
||||
* Handle to the GEM object for which to query the tiling parameters.
|
||||
*/
|
||||
__u32 handle;
|
||||
/* output */
|
||||
|
||||
/**
|
||||
* @mode:
|
||||
*
|
||||
* The tiling mode currently associated with the GEM object. Set by
|
||||
* the kernel upon successful completion of the IOCTL.
|
||||
*/
|
||||
__u32 mode;
|
||||
|
||||
/**
|
||||
* @value:
|
||||
*
|
||||
* The tiling mode parameter currently associated with the GEM object.
|
||||
* Set by the kernel upon successful completion of the IOCTL.
|
||||
*/
|
||||
__u32 value;
|
||||
|
||||
/**
|
||||
* @pad:
|
||||
*
|
||||
* Structure padding that may be used in the future. Must be 0.
|
||||
*/
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
#define DRM_TEGRA_GEM_BOTTOM_UP (1 << 0)
|
||||
#define DRM_TEGRA_GEM_FLAGS (DRM_TEGRA_GEM_BOTTOM_UP)
|
||||
|
||||
/**
|
||||
* struct drm_tegra_gem_set_flags - parameters for the set flags IOCTL
|
||||
*/
|
||||
struct drm_tegra_gem_set_flags {
|
||||
/* input */
|
||||
/**
|
||||
* @handle:
|
||||
*
|
||||
* Handle to the GEM object for which to set the flags.
|
||||
*/
|
||||
__u32 handle;
|
||||
/* output */
|
||||
|
||||
/**
|
||||
* @flags:
|
||||
*
|
||||
* The flags to set for the GEM object.
|
||||
*/
|
||||
__u32 flags;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_gem_get_flags - parameters for the get flags IOCTL
|
||||
*/
|
||||
struct drm_tegra_gem_get_flags {
|
||||
/* input */
|
||||
/**
|
||||
* @handle:
|
||||
*
|
||||
* Handle to the GEM object for which to query the flags.
|
||||
*/
|
||||
__u32 handle;
|
||||
/* output */
|
||||
|
||||
/**
|
||||
* @flags:
|
||||
*
|
||||
* The flags currently associated with the GEM object. Set by the
|
||||
* kernel upon successful completion of the IOCTL.
|
||||
*/
|
||||
__u32 flags;
|
||||
};
|
||||
|
||||
|
|
@ -193,7 +665,7 @@ struct drm_tegra_gem_get_flags {
|
|||
#define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr)
|
||||
#define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait)
|
||||
#define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel)
|
||||
#define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_open_channel)
|
||||
#define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_close_channel)
|
||||
#define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt)
|
||||
#define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit)
|
||||
#define DRM_IOCTL_TEGRA_GET_SYNCPT_BASE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT_BASE, struct drm_tegra_get_syncpt_base)
|
||||
|
|
|
|||
194
include/uapi/drm/v3d_drm.h
Normal file
194
include/uapi/drm/v3d_drm.h
Normal file
|
|
@ -0,0 +1,194 @@
|
|||
/*
|
||||
* Copyright © 2014-2018 Broadcom
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
|
||||
* IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _V3D_DRM_H_
|
||||
#define _V3D_DRM_H_
|
||||
|
||||
#include "drm.h"
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define DRM_V3D_SUBMIT_CL 0x00
|
||||
#define DRM_V3D_WAIT_BO 0x01
|
||||
#define DRM_V3D_CREATE_BO 0x02
|
||||
#define DRM_V3D_MMAP_BO 0x03
|
||||
#define DRM_V3D_GET_PARAM 0x04
|
||||
#define DRM_V3D_GET_BO_OFFSET 0x05
|
||||
|
||||
#define DRM_IOCTL_V3D_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl)
|
||||
#define DRM_IOCTL_V3D_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo)
|
||||
#define DRM_IOCTL_V3D_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_CREATE_BO, struct drm_v3d_create_bo)
|
||||
#define DRM_IOCTL_V3D_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_MMAP_BO, struct drm_v3d_mmap_bo)
|
||||
#define DRM_IOCTL_V3D_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_PARAM, struct drm_v3d_get_param)
|
||||
#define DRM_IOCTL_V3D_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset)
|
||||
|
||||
/**
|
||||
* struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D
|
||||
* engine.
|
||||
*
|
||||
* This asks the kernel to have the GPU execute an optional binner
|
||||
* command list, and a render command list.
|
||||
*/
|
||||
struct drm_v3d_submit_cl {
|
||||
/* Pointer to the binner command list.
|
||||
*
|
||||
* This is the first set of commands executed, which runs the
|
||||
* coordinate shader to determine where primitives land on the screen,
|
||||
* then writes out the state updates and draw calls necessary per tile
|
||||
* to the tile allocation BO.
|
||||
*/
|
||||
__u32 bcl_start;
|
||||
|
||||
/** End address of the BCL (first byte after the BCL) */
|
||||
__u32 bcl_end;
|
||||
|
||||
/* Offset of the render command list.
|
||||
*
|
||||
* This is the second set of commands executed, which will either
|
||||
* execute the tiles that have been set up by the BCL, or a fixed set
|
||||
* of tiles (in the case of RCL-only blits).
|
||||
*/
|
||||
__u32 rcl_start;
|
||||
|
||||
/** End address of the RCL (first byte after the RCL) */
|
||||
__u32 rcl_end;
|
||||
|
||||
/** An optional sync object to wait on before starting the BCL. */
|
||||
__u32 in_sync_bcl;
|
||||
/** An optional sync object to wait on before starting the RCL. */
|
||||
__u32 in_sync_rcl;
|
||||
/** An optional sync object to place the completion fence in. */
|
||||
__u32 out_sync;
|
||||
|
||||
/* Offset of the tile alloc memory
|
||||
*
|
||||
* This is optional on V3D 3.3 (where the CL can set the value) but
|
||||
* required on V3D 4.1.
|
||||
*/
|
||||
__u32 qma;
|
||||
|
||||
/** Size of the tile alloc memory. */
|
||||
__u32 qms;
|
||||
|
||||
/** Offset of the tile state data array. */
|
||||
__u32 qts;
|
||||
|
||||
/* Pointer to a u32 array of the BOs that are referenced by the job.
|
||||
*/
|
||||
__u64 bo_handles;
|
||||
|
||||
/* Number of BO handles passed in (size is that times 4). */
|
||||
__u32 bo_handle_count;
|
||||
|
||||
/* Pad, must be zero-filled. */
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_v3d_wait_bo - ioctl argument for waiting for
|
||||
* completion of the last DRM_V3D_SUBMIT_CL on a BO.
|
||||
*
|
||||
* This is useful for cases where multiple processes might be
|
||||
* rendering to a BO and you want to wait for all rendering to be
|
||||
* completed.
|
||||
*/
|
||||
struct drm_v3d_wait_bo {
|
||||
__u32 handle;
|
||||
__u32 pad;
|
||||
__u64 timeout_ns;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_v3d_create_bo - ioctl argument for creating V3D BOs.
|
||||
*
|
||||
* There are currently no values for the flags argument, but it may be
|
||||
* used in a future extension.
|
||||
*/
|
||||
struct drm_v3d_create_bo {
|
||||
__u32 size;
|
||||
__u32 flags;
|
||||
/** Returned GEM handle for the BO. */
|
||||
__u32 handle;
|
||||
/**
|
||||
* Returned offset for the BO in the V3D address space. This offset
|
||||
* is private to the DRM fd and is valid for the lifetime of the GEM
|
||||
* handle.
|
||||
*
|
||||
* This offset value will always be nonzero, since various HW
|
||||
* units treat 0 specially.
|
||||
*/
|
||||
__u32 offset;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_v3d_mmap_bo - ioctl argument for mapping V3D BOs.
|
||||
*
|
||||
* This doesn't actually perform an mmap. Instead, it returns the
|
||||
* offset you need to use in an mmap on the DRM device node. This
|
||||
* means that tools like valgrind end up knowing about the mapped
|
||||
* memory.
|
||||
*
|
||||
* There are currently no values for the flags argument, but it may be
|
||||
* used in a future extension.
|
||||
*/
|
||||
struct drm_v3d_mmap_bo {
|
||||
/** Handle for the object being mapped. */
|
||||
__u32 handle;
|
||||
__u32 flags;
|
||||
/** offset into the drm node to use for subsequent mmap call. */
|
||||
__u64 offset;
|
||||
};
|
||||
|
||||
enum drm_v3d_param {
|
||||
DRM_V3D_PARAM_V3D_UIFCFG,
|
||||
DRM_V3D_PARAM_V3D_HUB_IDENT1,
|
||||
DRM_V3D_PARAM_V3D_HUB_IDENT2,
|
||||
DRM_V3D_PARAM_V3D_HUB_IDENT3,
|
||||
DRM_V3D_PARAM_V3D_CORE0_IDENT0,
|
||||
DRM_V3D_PARAM_V3D_CORE0_IDENT1,
|
||||
DRM_V3D_PARAM_V3D_CORE0_IDENT2,
|
||||
};
|
||||
|
||||
struct drm_v3d_get_param {
|
||||
__u32 param;
|
||||
__u32 pad;
|
||||
__u64 value;
|
||||
};
|
||||
|
||||
/**
|
||||
* Returns the offset for the BO in the V3D address space for this DRM fd.
|
||||
* This is the same value returned by drm_v3d_create_bo, if that was called
|
||||
* from this DRM fd.
|
||||
*/
|
||||
struct drm_v3d_get_bo_offset {
|
||||
__u32 handle;
|
||||
__u32 offset;
|
||||
};
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _V3D_DRM_H_ */
|
||||
|
|
@ -183,10 +183,17 @@ struct drm_vc4_submit_cl {
|
|||
/* ID of the perfmon to attach to this job. 0 means no perfmon. */
|
||||
__u32 perfmonid;
|
||||
|
||||
/* Unused field to align this struct on 64 bits. Must be set to 0.
|
||||
* If one ever needs to add an u32 field to this struct, this field
|
||||
* can be used.
|
||||
/* Syncobj handle to wait on. If set, processing of this render job
|
||||
* will not start until the syncobj is signaled. 0 means ignore.
|
||||
*/
|
||||
__u32 in_sync;
|
||||
|
||||
/* Syncobj handle to export fence to. If set, the fence in the syncobj
|
||||
* will be replaced with a fence that signals upon completion of this
|
||||
* render job. 0 means ignore.
|
||||
*/
|
||||
__u32 out_sync;
|
||||
|
||||
__u32 pad2;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -260,6 +260,7 @@ struct virtio_gpu_cmd_submit {
|
|||
};
|
||||
|
||||
#define VIRTIO_GPU_CAPSET_VIRGL 1
|
||||
#define VIRTIO_GPU_CAPSET_VIRGL2 2
|
||||
|
||||
/* VIRTIO_GPU_CMD_GET_CAPSET_INFO */
|
||||
struct virtio_gpu_get_capset_info {
|
||||
|
|
|
|||
Loading…
Reference in a new issue