mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-09 21:59:12 -04:00
aw896x: awinic haptics driver
Initial DLKM code Change-Id: Ib6f27aa7deeb9807d46fbf2264181c5612c14a41 Signed-off-by: Konstantin Makariev <hcv867@motorola.com> Reviewed-on: https://gerrit.mot.com/1193016 SLTApproved: Slta Waiver SME-Granted: SME Approvals Granted Tested-by: Jira Key Reviewed-by: Konstantin Makariev <kmakariev@motorola.com> Submit-Approved: Jira Key
This commit is contained in:
Konstantin Makariev
Konstantin Makariev
parent
880641c595
commit
145fc10ebb
6 changed files with 2701 additions and 0 deletions
8
drivers/misc/awinic/Android.mk
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8
drivers/misc/awinic/Android.mk
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@ -0,0 +1,8 @@
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DLKM_DIR := motorola/kernel/modules
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LOCAL_PATH := $(call my-dir)
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include $(CLEAR_VARS)
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LOCAL_MODULE := aw869x.ko
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LOCAL_MODULE_TAGS := optional
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LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT)
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include $(DLKM_DIR)/AndroidKernelModule.mk
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5
drivers/misc/awinic/Kbuild
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5
drivers/misc/awinic/Kbuild
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# add -Wall to try to catch everything we can.
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EXTRA_CFLAGS += -Wall
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EXTRA_CFLAGS += -I$(TOP)/motorola/kernel/modules/include
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obj-m += aw869x.o
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11
drivers/misc/awinic/Makefile
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11
drivers/misc/awinic/Makefile
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@ -0,0 +1,11 @@
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KERNEL_SRC ?= /lib/modules/$(shell uname -r)/build
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all:
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$(MAKE) -C $(KERNEL_SRC) M=$(shell pwd) modules $(KBUILD_OPTIONS)
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modules_install:
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$(MAKE) INSTALL_MOD_STRIP=1 -C $(KERNEL_SRC) M=$(shell pwd) modules_install
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clean:
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$(MAKE) -C $(KERNEL_SRC) M=$(PWD) clean
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2206
drivers/misc/awinic/aw869x.c
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2206
drivers/misc/awinic/aw869x.c
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File diff suppressed because it is too large
Load diff
183
drivers/misc/awinic/aw869x.h
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183
drivers/misc/awinic/aw869x.h
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#ifndef _AW869X_H_
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#define _AW869X_H_
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/*********************************************************
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*
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* kernel 3.18
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*
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********************************************************/
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#if LINUX_VERSION_CODE <= KERNEL_VERSION(4, 4, 1)
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#define TIMED_OUTPUT
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#endif
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/*********************************************************
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*
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* aw869x.h
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*
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********************************************************/
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#include <linux/regmap.h>
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#include <linux/timer.h>
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#include <linux/workqueue.h>
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#include <linux/hrtimer.h>
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#include <linux/mutex.h>
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#include <linux/cdev.h>
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#include <linux/pm_wakeup.h>
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#ifdef TIMED_OUTPUT
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#include <../../../drivers/staging/android/timed_output.h>
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#else
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#include <linux/leds.h>
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#endif
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/*********************************************************
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*
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* marco
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*
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********************************************************/
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#define MAX_I2C_BUFFER_SIZE 65536
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#define AW869X_REG_MAX 0xff
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#define AW869X_SEQUENCER_SIZE 4
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#define AW869X_SEQUENCER_LOOP_SIZE 2
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#define AW869X_RTP_I2C_SINGLE_MAX_NUM 512
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#define HAPTIC_MAX_TIMEOUT 10000
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/*
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#define AW869X_HAPTIC_VBAT_MONITOR
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*/
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#ifdef AW869X_HAPTIC_VBAT_MONITOR
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#define SYS_BAT_DEV "/sys/class/power_supply/battery/voltage_now"
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#define AW869X_SYS_VBAT_REFERENCE 4200000
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#define AW869X_SYS_VBAT_MIN 3000000
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#define AW869X_SYS_VBAT_MAX 4500000
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#endif
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enum aw869x_flags {
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AW869X_FLAG_NONR = 0,
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AW869X_FLAG_SKIP_INTERRUPTS = 1,
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};
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enum aw869x_chipids {
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AW8691_ID = 0,
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};
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enum aw869x_haptic_read_write {
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AW869X_HAPTIC_CMD_READ_REG = 0,
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AW869X_HAPTIC_CMD_WRITE_REG = 1,
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AW869X_HAPTIC_CMD_UPDATE_FIRMWARE = 2,
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AW869X_HAPTIC_CMD_READ_FIRMWARE = 3,
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};
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enum aw869x_haptic_work_mode {
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AW869X_HAPTIC_STANDBY_MODE = 0,
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AW869X_HAPTIC_RAM_MODE = 1,
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AW869X_HAPTIC_RTP_MODE = 2,
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AW869X_HAPTIC_TRIG_MODE = 3,
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};
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enum aw869x_haptic_bst_mode {
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AW869X_HAPTIC_BYPASS_MODE = 0,
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AW869X_HAPTIC_BOOST_MODE = 1,
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};
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/*********************************************************
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*
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* struct
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*
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********************************************************/
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struct fileops {
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unsigned char cmd;
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unsigned char reg;
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unsigned char ram_addrh;
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unsigned char ram_addrl;
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};
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struct ram {
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unsigned int len;
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unsigned int check_sum;
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unsigned int base_addr;
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unsigned char version;
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unsigned char ram_shift;
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unsigned char baseaddr_shift;
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};
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struct aw869x {
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struct regmap *regmap;
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struct i2c_client *i2c;
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struct device *dev;
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struct input_dev *input;
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struct wakeup_source ws;
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struct mutex lock;
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struct hrtimer timer;
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struct work_struct vibrator_work;
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struct work_struct rtp_work;
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#ifdef TIMED_OUTPUT
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struct timed_output_dev to_dev;
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#else
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struct led_classdev cdev;
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#endif
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int reset_gpio;
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int irq_gpio;
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int state;
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int duration;
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int amplitude;
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int index;
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int vmax;
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int gain;
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int seq;
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int loop;
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unsigned char hwen_flag;
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unsigned char flags;
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unsigned char chipid;
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unsigned int rtp_cnt;
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unsigned char rtp_init;
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unsigned char ram_init;
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unsigned char play_mode;
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struct fileops fileops;
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struct ram ram;
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struct hrtimer ram_timer;
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struct work_struct ram_work;
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};
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struct aw869x_container{
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int len;
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unsigned char data[];
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};
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/*********************************************************
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*
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* ioctl
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*
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********************************************************/
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struct aw869x_seq_loop {
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unsigned char loop[AW869X_SEQUENCER_SIZE];
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};
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struct aw869x_que_seq {
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unsigned char index[AW869X_SEQUENCER_SIZE];
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};
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#define AW869X_HAPTIC_IOCTL_MAGIC 'h'
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#define AW869X_HAPTIC_SET_QUE_SEQ _IOWR(AW869X_HAPTIC_IOCTL_MAGIC, 1, struct aw869x_que_seq*)
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#define AW869X_HAPTIC_SET_SEQ_LOOP _IOWR(AW869X_HAPTIC_IOCTL_MAGIC, 2, struct aw869x_seq_loop*)
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#define AW869X_HAPTIC_PLAY_QUE_SEQ _IOWR(AW869X_HAPTIC_IOCTL_MAGIC, 3, unsigned int)
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#define AW869X_HAPTIC_SET_BST_VOL _IOWR(AW869X_HAPTIC_IOCTL_MAGIC, 4, unsigned int)
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#define AW869X_HAPTIC_SET_BST_PEAK_CUR _IOWR(AW869X_HAPTIC_IOCTL_MAGIC, 5, unsigned int)
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#define AW869X_HAPTIC_SET_GAIN _IOWR(AW869X_HAPTIC_IOCTL_MAGIC, 6, unsigned int)
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#define AW869X_HAPTIC_PLAY_REPEAT_SEQ _IOWR(AW869X_HAPTIC_IOCTL_MAGIC, 7, unsigned int)
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#endif
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288
drivers/misc/awinic/aw869x_reg.h
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288
drivers/misc/awinic/aw869x_reg.h
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#ifndef _AW869X_REG_H_
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#define _AW869X_REG_H_
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/********************************************
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* Register List
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*******************************************/
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#define AW869X_REG_ID 0x00
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#define AW869X_REG_SYSST 0x01
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#define AW869X_REG_SYSINT 0x02
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#define AW869X_REG_SYSINTM 0x03
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#define AW869X_REG_SYSCTRL 0x04
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#define AW869X_REG_PROC_CTRL 0x05
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#define AW869X_REG_RTP_DATA 0x06
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#define AW869X_REG_QUE_SEQ1 0x07
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#define AW869X_REG_QUE_SEQ2 0x08
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#define AW869X_REG_QUE_SEQ3 0x09
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#define AW869X_REG_QUE_SEQ4 0x0A
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#define AW869X_REG_SEQ_LOOP1 0x0B
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#define AW869X_REG_SEQ_LOOP2 0x0C
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#define AW869X_REG_TRG1_WAV_P 0x0D
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#define AW869X_REG_TRG2_WAV_P 0x0E
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#define AW869X_REG_TRG3_WAV_P 0x0F
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#define AW869X_REG_TRG1_WAV_N 0x10
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#define AW869X_REG_TRG2_WAV_N 0x11
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#define AW869X_REG_TRG3_WAV_N 0x12
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#define AW869X_REG_TRG_PRIO 0x13
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#define AW869X_REG_TRG_CFG 0x14
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#define AW869X_REG_DBGCTRL 0x20
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#define AW869X_REG_BASE_ADDRH 0x21
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#define AW869X_REG_BASE_ADDRL 0x22
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#define AW869X_REG_FIFO_AEH 0x23
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#define AW869X_REG_FIFO_AEL 0x24
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#define AW869X_REG_FIFO_AFH 0x25
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#define AW869X_REG_FIFO_AFL 0x26
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#define AW869X_REG_WAKE_DLY 0x27
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#define AW869X_REG_START_DLY 0x28
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#define AW869X_REG_END_DLY_H 0x29
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#define AW869X_REG_END_DLY_L 0x2A
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#define AW869X_REG_DATACTRL 0x2B
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#define AW869X_REG_PWMDEL 0x2C
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#define AW869X_REG_PWMPSC 0x2D
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#define AW869X_REG_PWMDBG 0x2E
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#define AW869X_REG_LDOCTRL 0x2F
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#define AW869X_REG_DBGSTAT 0x30
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#define AW869X_REG_BSTDBG1 0x31
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#define AW869X_REG_BSTDBG2 0x32
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#define AW869X_REG_BSTDBG3 0x33
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#define AW869X_REG_BSTCFG 0x34
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#define AW869X_REG_ANADBG 0x35
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#define AW869X_REG_ANACTRL 0x36
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#define AW869X_REG_OSCDBG 0x37
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#define AW869X_REG_GLBDBG 0x38
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#define AW869X_REG_DATDBG 0x39
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#define AW869X_REG_RAMADDRH 0x40
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#define AW869X_REG_RAMADDRL 0x41
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#define AW869X_REG_RAMDATA 0x42
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/********************************************
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* Register Access
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*******************************************/
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#define REG_NONE_ACCESS 0
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#define REG_RD_ACCESS 1 << 0
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#define REG_WR_ACCESS 1 << 1
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const unsigned char aw869x_reg_access[AW869X_REG_MAX]={
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[AW869X_REG_ID ] = REG_RD_ACCESS,
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[AW869X_REG_SYSST ] = REG_RD_ACCESS,
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[AW869X_REG_SYSINT ] = REG_RD_ACCESS,
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[AW869X_REG_SYSINTM ] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_SYSCTRL ] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_PROC_CTRL ] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_RTP_DATA ] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_QUE_SEQ1 ] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_QUE_SEQ2 ] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_QUE_SEQ3 ] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_QUE_SEQ4 ] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_SEQ_LOOP1 ] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_SEQ_LOOP2 ] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_TRG1_WAV_P] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_TRG2_WAV_P] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_TRG3_WAV_P] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_TRG1_WAV_N] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_TRG2_WAV_N] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_TRG3_WAV_N] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_TRG_PRIO ] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_TRG_CFG ] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_DBGCTRL ] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_BASE_ADDRH] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_BASE_ADDRL] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_FIFO_AEH ] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_FIFO_AEL ] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_FIFO_AFH ] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_FIFO_AFL ] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_WAKE_DLY ] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_START_DLY ] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_END_DLY_H ] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_END_DLY_L ] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_DATACTRL ] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_PWMDEL ] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_PWMPSC ] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_PWMDBG ] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_LDOCTRL ] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_DBGSTAT ] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_BSTDBG1 ] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_BSTDBG2 ] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_BSTDBG3 ] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_BSTCFG ] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_ANADBG ] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_ANACTRL ] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_OSCDBG ] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_GLBDBG ] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_DATDBG ] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_RAMADDRH ] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_RAMADDRL ] = REG_RD_ACCESS|REG_WR_ACCESS,
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[AW869X_REG_RAMDATA ] = REG_RD_ACCESS|REG_WR_ACCESS,
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};
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/******************************************************
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* Register Detail
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*****************************************************/
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// SYSST
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#define AW869X_BIT_SYSST_UVLS (1<<5)
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#define AW869X_BIT_SYSST_FF_AES (1<<4)
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#define AW869X_BIT_SYSST_FF_AFS (1<<3)
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#define AW869X_BIT_SYSST_OCDS (1<<2)
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#define AW869X_BIT_SYSST_OTS (1<<1)
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#define AW869X_BIT_SYSST_DONES (1<<0)
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// SYSINT
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#define AW869X_BIT_SYSINT_UVLI (1<<5)
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#define AW869X_BIT_SYSINT_FF_AEI (1<<4)
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#define AW869X_BIT_SYSINT_FF_AFI (1<<3)
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#define AW869X_BIT_SYSINT_OCDI (1<<2)
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#define AW869X_BIT_SYSINT_OTI (1<<1)
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#define AW869X_BIT_SYSINT_DONEI (1<<0)
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// SYSINTM
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#define AW869X_BIT_SYSINTM_UVLO_MASK (~(1<<5))
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#define AW869X_BIT_SYSINTM_UVLO_OFF (1<<5)
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#define AW869X_BIT_SYSINTM_UVLO_EN (0<<5)
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#define AW869X_BIT_SYSINTM_FF_AE_MASK (~(1<<4))
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#define AW869X_BIT_SYSINTM_FF_AE_OFF (1<<4)
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#define AW869X_BIT_SYSINTM_FF_AE_EN (0<<4)
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#define AW869X_BIT_SYSINTM_FF_AF_MASK (~(1<<3))
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#define AW869X_BIT_SYSINTM_FF_AF_OFF (1<<3)
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#define AW869X_BIT_SYSINTM_FF_AF_EN (0<<3)
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#define AW869X_BIT_SYSINTM_OCD_MASK (~(1<<2))
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#define AW869X_BIT_SYSINTM_OCD_OFF (1<<2)
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#define AW869X_BIT_SYSINTM_OCD_EN (0<<2)
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#define AW869X_BIT_SYSINTM_OT_MASK (~(1<<1))
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#define AW869X_BIT_SYSINTM_OT_OFF (1<<1)
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#define AW869X_BIT_SYSINTM_OT_EN (0<<1)
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#define AW869X_BIT_SYSINTM_DONE_MASK (~(1<<0))
|
||||
#define AW869X_BIT_SYSINTM_DONE_OFF (1<<0)
|
||||
#define AW869X_BIT_SYSINTM_DONE_EN (0<<0)
|
||||
|
||||
// SYSCTRL
|
||||
#define AW869X_BIT_SYSCTRL_RAMINIT_MASK (~(1<<5))
|
||||
#define AW869X_BIT_SYSCTRL_RAMINIT_EN (1<<5)
|
||||
#define AW869X_BIT_SYSCTRL_RAMINIT_OFF (0<<5)
|
||||
#define AW869X_BIT_SYSCTRL_PLAY_MODE_MASK (~(1<<3))
|
||||
#define AW869X_BIT_SYSCTRL_PLAY_MODE_RTP (1<<3)
|
||||
#define AW869X_BIT_SYSCTRL_PLAY_MODE_RAM (0<<3)
|
||||
#define AW869X_BIT_SYSCTRL_BST_MODE_MASK (~(1<<2))
|
||||
#define AW869X_BIT_SYSCTRL_BST_MODE_BOOST (1<<2)
|
||||
#define AW869X_BIT_SYSCTRL_BST_MODE_BYPASS (0<<2)
|
||||
#define AW869X_BIT_SYSCTRL_WORK_MODE_MASK (~(1<<0))
|
||||
#define AW869X_BIT_SYSCTRL_STANDBY (1<<0)
|
||||
#define AW869X_BIT_SYSCTRL_ACTIVE (0<<0)
|
||||
|
||||
// PROC_CTRL
|
||||
#define AW869X_BIT_PROC_CTRL_GO (1<<0)
|
||||
|
||||
// WAV_SEQ1
|
||||
#define AW869X_BIT_QUE_SEQ1_WAIT (1<<7)
|
||||
#define AW869X_BIT_QUE_SEQ1_WAV_FRM_SEQ1_MASK (~(128<<0))
|
||||
|
||||
// WAV_SEQ2
|
||||
#define AW869X_BIT_QUE_SEQ2_WAIT (1<<7)
|
||||
#define AW869X_BIT_QUE_SEQ2_WAV_FRM_SEQ2_MASK (~(128<<0))
|
||||
|
||||
// WAV_SEQ3
|
||||
#define AW869X_BIT_QUE_SEQ3_WAIT (1<<7)
|
||||
#define AW869X_BIT_QUE_SEQ3_WAV_FRM_SEQ3_MASK (~(128<<0))
|
||||
|
||||
// WAV_SEQ4
|
||||
#define AW869X_BIT_QUE_SEQ4_WAIT (1<<7)
|
||||
#define AW869X_BIT_QUE_SEQ4_WAV_FRM_SEQ4_MASK (~(128<<0))
|
||||
|
||||
|
||||
// WAV_LOOP1
|
||||
#define AW869X_BIT_SEQ_LOOP1_SEQ1_MASK (~(16<<4))
|
||||
#define AW869X_BIT_SEQ_LOOP1_SEQ2_MASK (~(16<<0))
|
||||
|
||||
// WAV_LOOP2
|
||||
#define AW869X_BIT_SEQ_LOOP2_SEQ1_MASK (~(16<<4))
|
||||
#define AW869X_BIT_SEQ_LOOP2_SEQ2_MASK (~(16<<0))
|
||||
|
||||
// TRG_PRIO
|
||||
#define AW869X_BIT_TRG_PRIO_TRIG3_MASK (~(3<<4))
|
||||
#define AW869X_BIT_TRG_PRIO_TRIG2_MASK (~(3<<2))
|
||||
#define AW869X_BIT_TRG_PRIO_TRIG1_MASK (~(3<<0))
|
||||
|
||||
// TRG_CFG
|
||||
#define AW869X_BIT_TRG_CFG_TRG3_PULSE_MASK (~(1<<5))
|
||||
#define AW869X_BIT_TRG_CFG_TRG3_PULSE_NEG (1<<5)
|
||||
#define AW869X_BIT_TRG_CFG_TRG3_PULSE_POS (0<<5)
|
||||
#define AW869X_BIT_TRG_CFG_TRG3_EDGE_MASK (~(1<<4))
|
||||
#define AW869X_BIT_TRG_CFG_TRG3_EDGE_POS (1<<4)
|
||||
#define AW869X_BIT_TRG_CFG_TRG3_EDGE_POS_NEG (0<<4)
|
||||
#define AW869X_BIT_TRG_CFG_TRG2_PULSE_MASK (~(1<<3))
|
||||
#define AW869X_BIT_TRG_CFG_TRG2_PULSE_NEG (1<<3)
|
||||
#define AW869X_BIT_TRG_CFG_TRG2_PULSE_POS (0<<3)
|
||||
#define AW869X_BIT_TRG_CFG_TRG2_EDGE_MASK (~(1<<2))
|
||||
#define AW869X_BIT_TRG_CFG_TRG2_EDGE_POS (1<<2)
|
||||
#define AW869X_BIT_TRG_CFG_TRG2_EDGE_POS_NEG (0<<2)
|
||||
#define AW869X_BIT_TRG_CFG_TRG1_PULSE_MASK (~(1<<1))
|
||||
#define AW869X_BIT_TRG_CFG_TRG1_PULSE_NEG (1<<1)
|
||||
#define AW869X_BIT_TRG_CFG_TRG1_PULSE_POS (0<<1)
|
||||
#define AW869X_BIT_TRG_CFG_TRG1_EDGE_MASK (~(1<<0))
|
||||
#define AW869X_BIT_TRG_CFG_TRG1_EDGE_POS (1<<0)
|
||||
#define AW869X_BIT_TRG_CFG_TRG1_EDGE_POS_NEG (0<<0)
|
||||
|
||||
// DBGCTRL
|
||||
#define AW869X_BIT_DBGCTRL_EN_BST (1<<7)
|
||||
#define AW869X_BIT_DBGCTRL_EN_HDRIVER (1<<6)
|
||||
#define AW869X_BIT_DBGCTRL_EN_UVLO (1<<5)
|
||||
#define AW869X_BIT_DBGCTRL_OVERRIDE_MASK (~(1<<4))
|
||||
#define AW869X_BIT_DBGCTRL_EN_OVERRIDE (1<<4)
|
||||
#define AW869X_BIT_DBGCTRL_DIS_OVERRIDE (1<<4)
|
||||
#define AW869X_BIT_DBGCTRL_INT_EDGE_MASK (~(1<<3))
|
||||
#define AW869X_BIT_DBGCTRL_INT_EDGE_POS_NEG (1<<3)
|
||||
#define AW869X_BIT_DBGCTRL_INT_EDGE_POS (0<<3)
|
||||
#define AW869X_BIT_DBGCTRL_INTMODE_MASK (~(1<<2))
|
||||
#define AW869X_BIT_DBGCTRL_INTMODE_EDGE (1<<2)
|
||||
#define AW869X_BIT_DBGCTRL_INTMODE_LEVEL (0<<2)
|
||||
#define AW869X_BIT_DBGCTRL_WAITSLOT_MASK (~(3<<0))
|
||||
#define AW869X_BIT_DBGCTRL_WAITSLOT_10MS (3<<0)
|
||||
#define AW869X_BIT_DBGCTRL_WAITSLOT_1280US (2<<0)
|
||||
#define AW869X_BIT_DBGCTRL_WAITSLOT_160US (1<<0)
|
||||
#define AW869X_BIT_DBGCTRL_WAITSLOT_20US (0<<0)
|
||||
|
||||
// DATACTRL
|
||||
#define AW869X_BIT_DATACTRL_INTP_MASK (~(1<<4))
|
||||
#define AW869X_BIT_DATACTRL_INTP_HIGH (1<<4)
|
||||
#define AW869X_BIT_DATACTRL_INTP_LOW (0<<4)
|
||||
#define AW869X_BIT_DATACTRL_WAV_DBG_MASK (~(1<<3))
|
||||
#define AW869X_BIT_DATACTRL_WAV_DBG (1<<3)
|
||||
#define AW869X_BIT_DATACTRL_WAV_NORMAL (0<<3)
|
||||
#define AW869X_BIT_DATACTRL_WAKE_MASK (~(1<<2))
|
||||
#define AW869X_BIT_DATACTRL_WAKE_AF_WAKE_DLY (1<<2)
|
||||
#define AW869X_BIT_DATACTRL_WAKE_AF_BST_OK (0<<2)
|
||||
#define AW869X_BIT_DATACTRL_END_MODE_MASK (~(1<<1))
|
||||
#define AW869X_BIT_DATACTRL_END_DELAY (1<<1)
|
||||
#define AW869X_BIT_DATACTRL_END_BACK_WAIT (0<<1)
|
||||
|
||||
// BSTCFG
|
||||
#define AW869X_BIT_BSTCFG_BSTVOL_MASK (~(31<<3))
|
||||
#define AW869X_BIT_BSTCFG_BSTVOL_10P5V (18<<3)
|
||||
#define AW869X_BIT_BSTCFG_BSTVOL_10P25V (17<<3)
|
||||
#define AW869X_BIT_BSTCFG_BSTVOL_10V (16<<3)
|
||||
#define AW869X_BIT_BSTCFG_BSTVOL_9P75V (15<<3)
|
||||
#define AW869X_BIT_BSTCFG_BSTVOL_9P5V (14<<3)
|
||||
#define AW869X_BIT_BSTCFG_BSTVOL_9P25V (13<<3)
|
||||
#define AW869X_BIT_BSTCFG_BSTVOL_9V (12<<3)
|
||||
#define AW869X_BIT_BSTCFG_BSTVOL_8P75V (11<<3)
|
||||
#define AW869X_BIT_BSTCFG_BSTVOL_8P5V (10<<3)
|
||||
#define AW869X_BIT_BSTCFG_BSTVOL_8P25V (9<<3)
|
||||
#define AW869X_BIT_BSTCFG_BSTVOL_8V (8<<3)
|
||||
#define AW869X_BIT_BSTCFG_BSTVOL_7P75V (7<<3)
|
||||
#define AW869X_BIT_BSTCFG_BSTVOL_7P5V (6<<3)
|
||||
#define AW869X_BIT_BSTCFG_BSTVOL_7P25V (5<<3)
|
||||
#define AW869X_BIT_BSTCFG_BSTVOL_7V (4<<3)
|
||||
#define AW869X_BIT_BSTCFG_BSTVOL_6P75V (3<<3)
|
||||
#define AW869X_BIT_BSTCFG_BSTVOL_6P5V (2<<3)
|
||||
#define AW869X_BIT_BSTCFG_BSTVOL_6P25V (1<<3)
|
||||
#define AW869X_BIT_BSTCFG_BSTVOL_6V (0<<3)
|
||||
#define AW869X_BIT_BSTCFG_PEAKCUR_MASK (~(7<<0))
|
||||
#define AW869X_BIT_BSTCFG_PEAKCUR_4A (7<<0)
|
||||
#define AW869X_BIT_BSTCFG_PEAKCUR_3P75A (6<<0)
|
||||
#define AW869X_BIT_BSTCFG_PEAKCUR_3P5A (5<<0)
|
||||
#define AW869X_BIT_BSTCFG_PEAKCUR_3P25A (4<<0)
|
||||
#define AW869X_BIT_BSTCFG_PEAKCUR_3A (3<<0)
|
||||
#define AW869X_BIT_BSTCFG_PEAKCUR_2P5A (2<<0)
|
||||
#define AW869X_BIT_BSTCFG_PEAKCUR_2A (1<<0)
|
||||
#define AW869X_BIT_BSTCFG_PEAKCUR_1P5A (0<<0)
|
||||
|
||||
#endif
|
||||
Loading…
Reference in a new issue