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clk: hix5hd2: add watchdog0 clocks

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hix5hd2 add watchdog0 clocks

Signed-off-by: Guoxiong Yan <[email protected]>
Signed-off-by: Zhangfei Gao <[email protected]>
Signed-off-by: Wei Xu <[email protected]>
This commit is contained in:
Guoxiong Yan 2014-06-17 17:04:17 +08:00 • committed by Wei Xu
commit 1463fba39c
2 changed files with 7 additions and 0 deletions
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5
drivers/clk/hisilicon/clk-hix5hd2.c
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@ -95,6 +95,11 @@ static struct hisi_gate_clock hix5hd2_gate_clks[] __initdata = {
{ HIX5HD2_FWD_SYS_CLK, "clk_fwd_sys", "clk_fwd_bus", 0, 0xcc, 5, 0, },
{ HIX5HD2_MAC0_PHY_CLK, "clk_fephy", "clk_fwd_sys",
CLK_SET_RATE_PARENT, 0x120, 0, 0, },
/* wdg0 */
{ HIX5HD2_WDG0_CLK, "clk_wdg0", "24m",
CLK_SET_RATE_PARENT, 0x178, 0, 0, },
{ HIX5HD2_WDG0_RST, "rst_wdg0", "clk_wdg0",
CLK_SET_RATE_PARENT, 0x178, 4, CLK_GATE_SET_TO_DISABLE, },
};
enum hix5hd2_clk_type {