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Merge "firmware: qcom_scm: Add calls to support poweroff driver"

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This commit is contained in:
qctecmdr 2019-12-19 03:51:40 -08:00 • committed by Gerrit - the friendly Code Review server
commit 14bc58fa2d
5 changed files with 140 additions and 43 deletions
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11
drivers/firmware/Kconfig
View file

@ -244,17 +244,6 @@ config QCOM_SCM
Qualcomm Technologies, Inc. "Secure Channel Manager"
interface.
config QCOM_SCM_DOWNLOAD_MODE_DEFAULT
bool "Qualcomm download mode enabled by default"
depends on QCOM_SCM
help
A device with "download mode" enabled will upon an unexpected
warm-restart enter a special debug mode that allows the user to
"download" memory content over USB for offline postmortem analysis.
The feature can be enabled/disabled on the kernel command line.
Say Y here to enable "download mode" by default.
config QTEE_SHM_BRIDGE
bool "QTI TEE shared memory bridge"
depends on QCOM_SCM

52
drivers/firmware/qcom_scm-smc.c
View file

@ -735,6 +735,24 @@ int __qcom_scm_sec_wdog_trigger(struct device *dev)
return ret ? : desc.res[0];
}
void __qcom_scm_disable_sdi(struct device *dev)
{
int ret;
struct qcom_scm_desc desc = {
.svc = QCOM_SCM_SVC_BOOT,
.cmd = QCOM_SCM_BOOT_WDOG_DEBUG_PART,
.owner = ARM_SMCCC_OWNER_SIP
};
desc.args[0] = 1;
desc.args[1] = 0;
desc.arginfo = QCOM_SCM_ARGS(2);
ret = qcom_scm_call_atomic(dev, &desc);
if (ret)
pr_err("Failed to disable secure wdog debug: %d\n", ret);
}
int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id)
{
struct qcom_scm_desc desc = {
@ -767,7 +785,7 @@ int __qcom_scm_spin_cpu(struct device *dev)
return qcom_scm_call(dev, &desc);
}
int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
int __qcom_scm_set_dload_mode(struct device *dev, enum qcom_download_mode mode)
{
struct qcom_scm_desc desc = {
.svc = QCOM_SCM_SVC_BOOT,
@ -775,8 +793,8 @@ int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
.owner = ARM_SMCCC_OWNER_SIP,
};
desc.args[0] = QCOM_SCM_BOOT_SET_DLOAD_MODE;
desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0;
desc.args[0] = mode;
desc.args[1] = 0;
desc.arginfo = QCOM_SCM_ARGS(2);
return qcom_scm_call_atomic(dev, &desc);
@ -1039,6 +1057,34 @@ int __qcom_scm_get_feat_version(struct device *dev, u64 feat_id, u64 *version)
return ret;
}
void __qcom_scm_halt_spmi_pmic_arbiter(struct device *dev)
{
struct qcom_scm_desc desc = {
.svc = QCOM_SCM_SVC_PWR,
.cmd = QCOM_SCM_PWR_IO_DISABLE_PMIC_ARBITER,
.owner = ARM_SMCCC_OWNER_SIP
};
desc.args[0] = 0;
desc.arginfo = QCOM_SCM_ARGS(1);
qcom_scm_call_atomic(dev, &desc);
}
void __qcom_scm_deassert_ps_hold(struct device *dev)
{
struct qcom_scm_desc desc = {
.svc = QCOM_SCM_SVC_PWR,
.cmd = QCOM_SCM_PWR_IO_DEASSERT_PS_HOLD,
.owner = ARM_SMCCC_OWNER_SIP
};
desc.args[0] = 0;
desc.arginfo = QCOM_SCM_ARGS(1);
qcom_scm_call_atomic(dev, &desc);
}
void __qcom_scm_mmu_sync(struct device *dev, bool sync)
{
int ret;

95
drivers/firmware/qcom_scm.c
View file

@ -21,9 +21,6 @@
#include "qcom_scm.h"
#include "qtee_shmbridge_internal.h"
static bool download_mode = IS_ENABLED(CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT);
module_param(download_mode, bool, 0);
#define SCM_HAS_CORE_CLK BIT(0)
#define SCM_HAS_IFACE_CLK BIT(1)
#define SCM_HAS_BUS_CLK BIT(2)
@ -131,6 +128,15 @@ int qcom_scm_sec_wdog_trigger(void)
}
EXPORT_SYMBOL(qcom_scm_sec_wdog_trigger);
/**
* qcom_scm_disable_sdi() - Disable SDI
*/
void qcom_scm_disable_sdi(void)
{
__qcom_scm_disable_sdi(__scm ? __scm->dev : NULL);
}
EXPORT_SYMBOL(qcom_scm_disable_sdi);
int qcom_scm_set_remote_state(u32 state, u32 id)
{
return __qcom_scm_set_remote_state(__scm->dev, state, id);
@ -143,28 +149,31 @@ int qcom_scm_spin_cpu(void)
}
EXPORT_SYMBOL(qcom_scm_spin_cpu);
static void qcom_scm_set_download_mode(bool enable)
void qcom_scm_set_download_mode(enum qcom_download_mode mode,
phys_addr_t tcsr_boot_misc)
{
bool avail;
int ret = 0;
struct device *dev = __scm ? __scm->dev : NULL;
avail = __qcom_scm_is_call_available(__scm->dev,
avail = __qcom_scm_is_call_available(dev,
QCOM_SCM_SVC_BOOT,
QCOM_SCM_BOOT_SET_DLOAD_MODE);
if (avail) {
ret = __qcom_scm_set_dload_mode(__scm->dev, enable);
} else if (__scm->dload_mode_addr) {
ret = __qcom_scm_io_writel(__scm->dev, __scm->dload_mode_addr,
enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE
: 0);
ret = __qcom_scm_set_dload_mode(dev, mode);
} else if (tcsr_boot_misc || (__scm && __scm->dload_mode_addr)) {
ret = __qcom_scm_io_writel(dev,
tcsr_boot_misc ? : __scm->dload_mode_addr,
mode);
} else {
dev_err(__scm->dev,
dev_err(dev,
"No available mechanism for setting download mode\n");
}
if (ret)
dev_err(__scm->dev, "failed to set download mode: %d\n", ret);
dev_err(dev, "failed to set download mode: %d\n", ret);
}
EXPORT_SYMBOL(qcom_scm_set_download_mode);
int qcom_scm_config_cpu_errata(void)
{
@ -383,6 +392,52 @@ int qcom_scm_get_jtag_etm_feat_id(u64 *version)
}
EXPORT_SYMBOL(qcom_scm_get_jtag_etm_feat_id);
/**
* qcom_halt_spmi_pmic_arbiter() - Halt SPMI PMIC arbiter
*
* Force the SPMI PMIC arbiter to shutdown so that no more SPMI transactions
* are sent from the MSM to the PMIC. This is required in order to avoid an
* SPMI lockup on certain PMIC chips if PS_HOLD is lowered in the middle of
* an SPMI transaction.
*/
void qcom_scm_halt_spmi_pmic_arbiter(void)
{
bool avail;
struct device *dev = __scm ? __scm->dev : NULL;
avail = __qcom_scm_is_call_available(dev,
QCOM_SCM_SVC_PWR,
QCOM_SCM_PWR_IO_DISABLE_PMIC_ARBITER);
if (!avail)
return;
pr_crit("Calling SCM to disable SPMI PMIC arbiter\n");
return __qcom_scm_halt_spmi_pmic_arbiter(dev);
}
EXPORT_SYMBOL(qcom_scm_halt_spmi_pmic_arbiter);
/**
* qcom_deassert_ps_hold() - Deassert PS_HOLD
*
* Deassert PS_HOLD to signal the PMIC that we are ready to power down or reset.
*
* This function should never return if the SCM call is available.
*/
void qcom_scm_deassert_ps_hold(void)
{
bool avail;
struct device *dev = __scm ? __scm->dev : NULL;
avail = __qcom_scm_is_call_available(dev,
QCOM_SCM_SVC_PWR,
QCOM_SCM_PWR_IO_DEASSERT_PS_HOLD);
if (avail)
__qcom_scm_deassert_ps_hold(dev);
}
EXPORT_SYMBOL(qcom_scm_deassert_ps_hold);
void qcom_scm_mmu_sync(bool sync)
{
__qcom_scm_mmu_sync(__scm ? __scm->dev : NULL, sync);
@ -1024,24 +1079,9 @@ static int qcom_scm_probe(struct platform_device *pdev)
return ret;
#endif
/*
* If requested enable "download mode", from this point on warmboot
* will cause the the boot stages to enter download mode, unless
* disabled below by a clean shutdown/reboot.
*/
if (download_mode)
qcom_scm_set_download_mode(true);
return 0;
}
static void qcom_scm_shutdown(struct platform_device *pdev)
{
/* Clean shutdown, disable download mode to allow normal restart */
if (download_mode)
qcom_scm_set_download_mode(false);
}
static const struct of_device_id qcom_scm_dt_match[] = {
{ .compatible = "qcom,scm-apq8064",
/* FIXME: This should have .data = (void *) SCM_HAS_CORE_CLK */
@ -1072,7 +1112,6 @@ static struct platform_driver qcom_scm_driver = {
.of_match_table = qcom_scm_dt_match,
},
.probe = qcom_scm_probe,
.shutdown = qcom_scm_shutdown,
};
static int __init qcom_scm_init(void)

9
drivers/firmware/qcom_scm.h
View file

@ -10,6 +10,7 @@
#define QCOM_SCM_BOOT_TERMINATE_PC 0x02
#define QCOM_SCM_BOOT_SEC_WDOG_DIS 0x07
#define QCOM_SCM_BOOT_SEC_WDOG_TRIGGER 0x08
#define QCOM_SCM_BOOT_WDOG_DEBUG_PART 0x09
#define QCOM_SCM_BOOT_SET_REMOTE_STATE 0x0a
#define QCOM_SCM_BOOT_SPIN_CPU 0x0d
#define QCOM_SCM_BOOT_SWITCH_MODE 0x0f
@ -22,9 +23,11 @@ extern int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry,
extern void __qcom_scm_cpu_power_down(struct device *dev, u32 flags);
extern int __qcom_scm_sec_wdog_deactivate(struct device *dev);
extern int __qcom_scm_sec_wdog_trigger(struct device *dev);
extern void __qcom_scm_disable_sdi(struct device *dev);
extern int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id);
extern int __qcom_scm_spin_cpu(struct device *dev);
extern int __qcom_scm_set_dload_mode(struct device *dev, bool enable);
extern int __qcom_scm_set_dload_mode(struct device *dev,
enum qcom_download_mode mode);
extern int __qcom_scm_config_cpu_errata(struct device *dev);
#define QCOM_SCM_FLUSH_FLAG_MASK 0x3
@ -72,7 +75,11 @@ extern int __qcom_scm_get_feat_version(struct device *dev, u64 feat_id,
#define QCOM_SCM_MP_CP_FEAT_ID 0x0c
#define QCOM_SCM_SVC_PWR 0x09
#define QCOM_SCM_PWR_IO_DISABLE_PMIC_ARBITER 0x01
#define QCOM_SCM_PWR_IO_DEASSERT_PS_HOLD 0x02
#define QCOM_SCM_PWR_MMU_SYNC 0x08
extern void __qcom_scm_halt_spmi_pmic_arbiter(struct device *dev);
extern void __qcom_scm_deassert_ps_hold(struct device *dev);
extern void __qcom_scm_mmu_sync(struct device *dev, bool sync);
#define QCOM_SCM_SVC_MP 0x0c

16
include/linux/qcom_scm.h
View file

@ -14,6 +14,12 @@
#define QCOM_SCM_CPU_PWR_DOWN_L2_OFF 0x1
#define QCOM_SCM_HDCP_MAX_REQ_CNT 5
enum qcom_download_mode {
QCOM_DOWNLOAD_NODUMP = 0x00,
QCOM_DOWNLOAD_EDL = 0x01,
QCOM_DOWNLOAD_FULLDUMP = 0x10,
};
struct qcom_scm_hdcp_req {
u32 addr;
u32 val;
@ -77,8 +83,11 @@ extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);
extern void qcom_scm_cpu_power_down(u32 flags);
extern int qcom_scm_sec_wdog_deactivate(void);
extern int qcom_scm_sec_wdog_trigger(void);
extern void qcom_scm_disable_sdi(void);
extern int qcom_scm_set_remote_state(u32 state, u32 id);
extern int qcom_scm_spin_cpu(void);
extern void qcom_scm_set_download_mode(enum qcom_download_mode mode,
phys_addr_t tcsr_boot_misc);
extern int qcom_scm_config_cpu_errata(void);
extern bool qcom_scm_pas_supported(u32 peripheral);
extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
@ -95,6 +104,8 @@ extern int qcom_scm_io_reset(void);
extern bool qcom_scm_is_secure_wdog_trigger_available(void);
extern bool qcom_scm_is_mode_switch_available(void);
extern int qcom_scm_get_jtag_etm_feat_id(u64 *version);
extern void qcom_scm_halt_spmi_pmic_arbiter(void);
extern void qcom_scm_deassert_ps_hold(void);
extern void qcom_scm_mmu_sync(bool sync);
extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
@ -191,9 +202,12 @@ int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
static inline void qcom_scm_cpu_power_down(u32 flags) {}
static inline int qcom_scm_sec_wdog_deactivate(void) { return -ENODEV; }
static inline int qcom_scm_sec_wdog_trigger(void) { return -ENODEV; }
static inline void qcom_scm_disable_sdi(void) {}
static inline u32 qcom_scm_set_remote_state(u32 state, u32 id)
{ return -ENODEV; }
static inline int qcom_scm_spin_cpu(void) { return -ENODEV; }
static inline void qcom_scm_set_download_mode(enum qcom_download_mode mode,
phys_addr_t tcsr_boot_misc) {}
static inline int qcom_scm_config_cpu_errata(void)
{ return -ENODEV; }
static inline bool qcom_scm_pas_supported(u32 peripheral) { return false; }
@ -220,6 +234,8 @@ static inline bool qcom_scm_is_mode_switch_available(void)
{ return -ENODEV; }
static inline int qcom_scm_get_jtag_etm_feat_id(u64 *version)
{ return -ENODEV; }
static inline void qcom_scm_halt_spmi_pmic_arbiter(void) {}
static inline void qcom_scm_deassert_ps_hold(void) {}
static inline void qcom_scm_mmu_sync(bool sync) {}
static inline int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare)
{ return -ENODEV; }