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qcacmn: WAR for RXDMA packet drop issue
When monitor RXDMA is enabled, regular RXDMA will drop a good packet whenever an error is indicated in monitor path due to a HW bug. To avoid this, a dummy buffer will be used to receive packets passing "monitor other" filter on regular DMA, which will be received on RXDMA2HOST ring. These packets should be ignored based on a special cookie value. Change-Id: I348527f662cd664652d8d99c01484bb310c6e705
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80cded8b4a
commit
15a3d48c75
2 changed files with 26 additions and 6 deletions
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@ -843,6 +843,8 @@ dp_rx_err_mpdu_pop(struct dp_soc *soc, uint32_t mac_id,
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uint32_t msdu_cnt;
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uint32_t i;
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bool mpdu_err;
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uint8_t push_reason;
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uint8_t rxdma_error_code = 0;
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msdu = 0;
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@ -851,6 +853,13 @@ dp_rx_err_mpdu_pop(struct dp_soc *soc, uint32_t mac_id,
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hal_rx_reo_ent_buf_paddr_get(rxdma_dst_ring_desc, &buf_info,
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&p_last_buf_addr_info, &msdu_cnt, &mpdu_err);
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push_reason =
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hal_rx_reo_ent_rxdma_push_reason_get(rxdma_dst_ring_desc);
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if (push_reason == HAL_RX_WBM_RXDMA_PSH_RSN_ERROR) {
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rxdma_error_code =
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hal_rx_reo_ent_rxdma_error_code_get(rxdma_dst_ring_desc);
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}
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do {
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rx_msdu_link_desc =
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dp_rx_cookie_2_link_desc_va(soc, &buf_info);
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@ -864,11 +873,11 @@ dp_rx_err_mpdu_pop(struct dp_soc *soc, uint32_t mac_id,
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msdu_cnt -= num_msdus;
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for (i = 0; i < num_msdus; i++) {
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struct dp_rx_desc *rx_desc =
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dp_rx_cookie_2_va_rxdma_buf(soc,
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msdu_list.sw_cookie[i]);
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if (msdu_list.sw_cookie[0] != HAL_RX_COOKIE_SPECIAL) {
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for (i = 0; i < num_msdus; i++) {
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struct dp_rx_desc *rx_desc =
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dp_rx_cookie_2_va_rxdma_buf(soc,
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msdu_list.sw_cookie[i]);
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qdf_assert(rx_desc);
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msdu = rx_desc->nbuf;
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@ -884,6 +893,9 @@ dp_rx_err_mpdu_pop(struct dp_soc *soc, uint32_t mac_id,
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rx_bufs_used++;
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dp_rx_add_to_free_desc_list(head,
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tail, rx_desc);
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}
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} else {
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rxdma_error_code = HAL_RXDMA_ERR_WAR;
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}
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hal_rx_mon_next_link_desc_get(rx_msdu_link_desc, &buf_info,
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@ -894,6 +906,8 @@ dp_rx_err_mpdu_pop(struct dp_soc *soc, uint32_t mac_id,
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} while (buf_info.paddr && msdu_cnt);
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DP_STATS_INC(soc, rx.err.rxdma_error[rxdma_error_code], 1);
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return rx_bufs_used;
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}
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@ -1633,6 +1633,10 @@ struct hal_buf_info {
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uint32_t sw_cookie;
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};
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/* This special cookie value will be used to indicate FW allocated buffers
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* received through RXDMA2SW ring for RXDMA WARs */
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#define HAL_RX_COOKIE_SPECIAL 0x1fffff
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/**
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* hal_rx_msdu_link_desc_get(): API to get the MSDU information
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* from the MSDU link descriptor
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@ -1795,6 +1799,7 @@ enum hal_reo_error_code {
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* @ HAL_RXDMA_ERR_DA_TIMEOUT : Destination Address search timeout
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* @ HAL_RXDMA_ERR_FLOW_TIMEOUT : Flow Search Timeout
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* @ HAL_RXDMA_ERR_FLUSH_REQUEST : RxDMA FIFO Flush request
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* @ HAL_RXDMA_ERR_WAR : RxDMA WAR dummy errors
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*/
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enum hal_rxdma_error_code {
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HAL_RXDMA_ERR_OVERFLOW = 0,
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@ -1810,7 +1815,8 @@ enum hal_rxdma_error_code {
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HAL_RXDMA_ERR_SA_TIMEOUT,
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HAL_RXDMA_ERR_DA_TIMEOUT,
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HAL_RXDMA_ERR_FLOW_TIMEOUT,
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HAL_RXDMA_ERR_FLUSH_REQUEST
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HAL_RXDMA_ERR_FLUSH_REQUEST,
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HAL_RXDMA_ERR_WAR = 31
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};
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/**
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