mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-09 05:39:54 -04:00
Merge "clk: qcom: gdsc-regulator: Place a min operational vote on GDSC parent"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
161cd099fb
2 changed files with 740 additions and 1 deletions
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@ -1,4 +1,4 @@
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# SPDX-License-Identifier: GPL-2.0
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# SPDX-License-Identifier: GPL-2.0-only
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obj-$(CONFIG_COMMON_CLK_QCOM) += clk-qcom.o
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clk-qcom-y += common.o
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@ -15,6 +15,7 @@ clk-qcom-$(CONFIG_KRAIT_CLOCKS) += clk-krait.o
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clk-qcom-y += clk-hfpll.o
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clk-qcom-y += reset.o
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clk-qcom-y += clk-dummy.o
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clk-qcom-y += gdsc-regulator.o
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clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
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# Keep alphabetically sorted by config
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738
drivers/clk/qcom/gdsc-regulator.c
Normal file
738
drivers/clk/qcom/gdsc-regulator.c
Normal file
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@ -0,0 +1,738 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/driver.h>
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#include <linux/regulator/machine.h>
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#include <linux/regulator/of_regulator.h>
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include <linux/mfd/syscon.h>
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#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
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/* GDSCR */
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#define PWR_ON_MASK BIT(31)
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#define CLK_DIS_WAIT_MASK (0xF << 12)
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#define CLK_DIS_WAIT_SHIFT (12)
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#define SW_OVERRIDE_MASK BIT(2)
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#define HW_CONTROL_MASK BIT(1)
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#define SW_COLLAPSE_MASK BIT(0)
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/* Domain Address */
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#define GMEM_CLAMP_IO_MASK BIT(0)
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#define GMEM_RESET_MASK BIT(4)
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/* SW Reset */
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#define BCR_BLK_ARES_BIT BIT(0)
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/* Register Offset */
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#define REG_OFFSET 0x0
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/* Timeout Delay */
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#define TIMEOUT_US 100
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struct gdsc {
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struct regulator_dev *rdev;
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struct regulator_desc rdesc;
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void __iomem *gdscr;
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struct regmap *regmap;
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struct regmap *domain_addr;
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struct regmap *hw_ctrl;
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struct regmap *sw_reset;
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struct clk **clocks;
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struct regulator *parent_regulator;
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struct reset_control **reset_clocks;
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bool toggle_logic;
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bool resets_asserted;
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bool root_en;
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bool force_root_en;
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bool no_status_check_on_disable;
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bool is_gdsc_enabled;
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bool reset_aon;
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int clock_count;
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int reset_count;
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int root_clk_idx;
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u32 gds_timeout;
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};
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enum gdscr_status {
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ENABLED,
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DISABLED,
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};
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static DEFINE_MUTEX(gdsc_seq_lock);
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static inline u32 gdsc_mb(struct gdsc *gds)
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{
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u32 reg;
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regmap_read(gds->regmap, REG_OFFSET, ®);
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return reg;
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}
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static int poll_gdsc_status(struct gdsc *sc, enum gdscr_status status)
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{
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struct regmap *regmap;
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int count = sc->gds_timeout;
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u32 val;
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if (sc->hw_ctrl)
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regmap = sc->hw_ctrl;
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else
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regmap = sc->regmap;
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for (; count > 0; count--) {
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regmap_read(regmap, REG_OFFSET, &val);
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val &= PWR_ON_MASK;
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switch (status) {
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case ENABLED:
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if (val)
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return 0;
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break;
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case DISABLED:
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if (!val)
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return 0;
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break;
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}
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/*
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* There is no guarantee about the delay needed for the enable
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* bit in the GDSCR to be set or reset after the GDSC state
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* changes. Hence, keep on checking for a reasonable number
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* of times until the bit is set with the least possible delay
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* between succeessive tries.
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*/
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udelay(1);
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}
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return -ETIMEDOUT;
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}
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static int gdsc_is_enabled(struct regulator_dev *rdev)
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{
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struct gdsc *sc = rdev_get_drvdata(rdev);
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uint32_t regval;
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if (!sc->toggle_logic)
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return !sc->resets_asserted;
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regmap_read(sc->regmap, REG_OFFSET, ®val);
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if (regval & PWR_ON_MASK) {
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/*
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* The GDSC might be turned on due to TZ/HYP vote on the
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* votable GDS registers. Check the SW_COLLAPSE_MASK to
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* determine if HLOS has voted for it.
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*/
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if (!(regval & SW_COLLAPSE_MASK))
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return true;
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}
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return false;
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}
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static int gdsc_enable(struct regulator_dev *rdev)
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{
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struct gdsc *sc = rdev_get_drvdata(rdev);
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uint32_t regval, hw_ctrl_regval = 0x0;
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int i, ret = 0;
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mutex_lock(&gdsc_seq_lock);
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if (sc->parent_regulator) {
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ret = regulator_set_voltage(sc->parent_regulator,
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RPMH_REGULATOR_LEVEL_LOW_SVS, INT_MAX);
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if (ret) {
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mutex_unlock(&gdsc_seq_lock);
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return ret;
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}
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}
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if (sc->root_en || sc->force_root_en)
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clk_prepare_enable(sc->clocks[sc->root_clk_idx]);
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regmap_read(sc->regmap, REG_OFFSET, ®val);
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if (regval & HW_CONTROL_MASK) {
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dev_warn(&rdev->dev, "Invalid enable while %s is under HW control\n",
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sc->rdesc.name);
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ret = -EBUSY;
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goto end;
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}
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if (sc->toggle_logic) {
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if (sc->sw_reset) {
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regmap_read(sc->sw_reset, REG_OFFSET, ®val);
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regval |= BCR_BLK_ARES_BIT;
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regmap_write(sc->sw_reset, REG_OFFSET, regval);
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/*
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* BLK_ARES should be kept asserted for 1us before
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* being de-asserted.
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*/
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gdsc_mb(sc);
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udelay(1);
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regval &= ~BCR_BLK_ARES_BIT;
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regmap_write(sc->sw_reset, REG_OFFSET, regval);
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/* Make sure de-assert goes through before continuing */
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gdsc_mb(sc);
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}
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if (sc->domain_addr) {
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if (sc->reset_aon) {
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regmap_read(sc->domain_addr, REG_OFFSET,
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®val);
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regval |= GMEM_RESET_MASK;
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regmap_write(sc->domain_addr, REG_OFFSET,
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regval);
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/*
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* Keep reset asserted for at-least 1us before
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* continuing.
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*/
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gdsc_mb(sc);
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udelay(1);
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regval &= ~GMEM_RESET_MASK;
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regmap_write(sc->domain_addr, REG_OFFSET,
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regval);
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/*
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* Make sure GMEM_RESET is de-asserted before
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* continuing.
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*/
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gdsc_mb(sc);
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}
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regmap_read(sc->domain_addr, REG_OFFSET, ®val);
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regval &= ~GMEM_CLAMP_IO_MASK;
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regmap_write(sc->domain_addr, REG_OFFSET, regval);
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/*
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* Make sure CLAMP_IO is de-asserted before continuing.
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*/
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gdsc_mb(sc);
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}
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regmap_read(sc->regmap, REG_OFFSET, ®val);
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regval &= ~SW_COLLAPSE_MASK;
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regmap_write(sc->regmap, REG_OFFSET, regval);
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/* Wait for 8 XO cycles before polling the status bit. */
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gdsc_mb(sc);
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udelay(1);
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ret = poll_gdsc_status(sc, ENABLED);
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if (ret) {
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regmap_read(sc->regmap, REG_OFFSET, ®val);
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if (sc->hw_ctrl) {
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regmap_read(sc->hw_ctrl, REG_OFFSET,
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&hw_ctrl_regval);
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dev_warn(&rdev->dev, "%s state (after %d us timeout): 0x%x, GDS_HW_CTRL: 0x%x. Re-polling.\n",
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sc->rdesc.name, sc->gds_timeout,
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regval, hw_ctrl_regval);
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ret = poll_gdsc_status(sc, ENABLED);
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if (ret) {
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regmap_read(sc->regmap, REG_OFFSET,
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®val);
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regmap_read(sc->hw_ctrl, REG_OFFSET,
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&hw_ctrl_regval);
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dev_err(&rdev->dev, "%s final state (after additional %d us timeout): 0x%x, GDS_HW_CTRL: 0x%x\n",
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sc->rdesc.name, sc->gds_timeout,
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regval, hw_ctrl_regval);
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goto end;
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}
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} else {
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dev_err(&rdev->dev, "%s enable timed out: 0x%x\n",
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sc->rdesc.name,
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regval);
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udelay(sc->gds_timeout);
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regmap_read(sc->regmap, REG_OFFSET, ®val);
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dev_err(&rdev->dev, "%s final state: 0x%x (%d us after timeout)\n",
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sc->rdesc.name, regval,
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sc->gds_timeout);
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goto end;
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}
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}
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} else {
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for (i = 0; i < sc->reset_count; i++)
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reset_control_deassert(sc->reset_clocks[i]);
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sc->resets_asserted = false;
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}
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/*
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* If clocks to this power domain were already on, they will take an
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* additional 4 clock cycles to re-enable after the rail is enabled.
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* Delay to account for this. A delay is also needed to ensure clocks
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* are not enabled within 400ns of enabling power to the memories.
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*/
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udelay(1);
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/* Delay to account for staggered memory powerup. */
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udelay(1);
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if (sc->force_root_en)
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clk_disable_unprepare(sc->clocks[sc->root_clk_idx]);
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sc->is_gdsc_enabled = true;
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end:
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if (sc->parent_regulator)
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regulator_set_voltage(sc->parent_regulator, 0, INT_MAX);
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mutex_unlock(&gdsc_seq_lock);
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return ret;
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}
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static int gdsc_disable(struct regulator_dev *rdev)
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{
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struct gdsc *sc = rdev_get_drvdata(rdev);
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uint32_t regval;
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int i, ret = 0;
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mutex_lock(&gdsc_seq_lock);
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|
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if (sc->parent_regulator) {
|
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ret = regulator_set_voltage(sc->parent_regulator,
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RPMH_REGULATOR_LEVEL_LOW_SVS, INT_MAX);
|
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if (ret) {
|
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mutex_unlock(&gdsc_seq_lock);
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return ret;
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}
|
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}
|
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|
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if (sc->force_root_en)
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clk_prepare_enable(sc->clocks[sc->root_clk_idx]);
|
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|
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/* Delay to account for staggered memory powerdown. */
|
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udelay(1);
|
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|
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if (sc->toggle_logic) {
|
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regmap_read(sc->regmap, REG_OFFSET, ®val);
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regval |= SW_COLLAPSE_MASK;
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regmap_write(sc->regmap, REG_OFFSET, regval);
|
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|
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/* Wait for 8 XO cycles before polling the status bit. */
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gdsc_mb(sc);
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udelay(1);
|
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|
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if (sc->no_status_check_on_disable) {
|
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/*
|
||||
* Add a short delay here to ensure that gdsc_enable
|
||||
* right after it was disabled does not put it in a
|
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* weird state.
|
||||
*/
|
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udelay(TIMEOUT_US);
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} else {
|
||||
ret = poll_gdsc_status(sc, DISABLED);
|
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if (ret)
|
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dev_err(&rdev->dev, "%s disable timed out: 0x%x\n",
|
||||
sc->rdesc.name, regval);
|
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}
|
||||
|
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if (sc->domain_addr) {
|
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regmap_read(sc->domain_addr, REG_OFFSET, ®val);
|
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regval |= GMEM_CLAMP_IO_MASK;
|
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regmap_write(sc->domain_addr, REG_OFFSET, regval);
|
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}
|
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|
||||
} else {
|
||||
for (i = sc->reset_count - 1; i >= 0; i--)
|
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reset_control_assert(sc->reset_clocks[i]);
|
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sc->resets_asserted = true;
|
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}
|
||||
|
||||
/*
|
||||
* Check if gdsc_enable was called for this GDSC. If not, the root
|
||||
* clock will not have been enabled prior to this.
|
||||
*/
|
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if ((sc->is_gdsc_enabled && sc->root_en) || sc->force_root_en)
|
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clk_disable_unprepare(sc->clocks[sc->root_clk_idx]);
|
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|
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if (sc->parent_regulator)
|
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regulator_set_voltage(sc->parent_regulator, 0, INT_MAX);
|
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|
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sc->is_gdsc_enabled = false;
|
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|
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mutex_unlock(&gdsc_seq_lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static unsigned int gdsc_get_mode(struct regulator_dev *rdev)
|
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{
|
||||
struct gdsc *sc = rdev_get_drvdata(rdev);
|
||||
uint32_t regval;
|
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|
||||
mutex_lock(&gdsc_seq_lock);
|
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regmap_read(sc->regmap, REG_OFFSET, ®val);
|
||||
mutex_unlock(&gdsc_seq_lock);
|
||||
|
||||
if (regval & HW_CONTROL_MASK)
|
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return REGULATOR_MODE_FAST;
|
||||
|
||||
return REGULATOR_MODE_NORMAL;
|
||||
}
|
||||
|
||||
static int gdsc_set_mode(struct regulator_dev *rdev, unsigned int mode)
|
||||
{
|
||||
struct gdsc *sc = rdev_get_drvdata(rdev);
|
||||
uint32_t regval;
|
||||
int ret = 0;
|
||||
|
||||
mutex_lock(&gdsc_seq_lock);
|
||||
|
||||
if (sc->parent_regulator) {
|
||||
ret = regulator_set_voltage(sc->parent_regulator,
|
||||
RPMH_REGULATOR_LEVEL_LOW_SVS, INT_MAX);
|
||||
if (ret) {
|
||||
mutex_unlock(&gdsc_seq_lock);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
regmap_read(sc->regmap, REG_OFFSET, ®val);
|
||||
|
||||
switch (mode) {
|
||||
case REGULATOR_MODE_FAST:
|
||||
/* Turn on HW trigger mode */
|
||||
regval |= HW_CONTROL_MASK;
|
||||
regmap_write(sc->regmap, REG_OFFSET, regval);
|
||||
/*
|
||||
* There may be a race with internal HW trigger signal,
|
||||
* that will result in GDSC going through a power down and
|
||||
* up cycle. In case HW trigger signal is controlled by
|
||||
* firmware that also poll same status bits as we do, FW
|
||||
* might read an 'on' status before the GDSC can finish
|
||||
* power cycle. We wait 1us before returning to ensure
|
||||
* FW can't immediately poll the status bit.
|
||||
*/
|
||||
gdsc_mb(sc);
|
||||
udelay(1);
|
||||
break;
|
||||
case REGULATOR_MODE_NORMAL:
|
||||
/* Turn off HW trigger mode */
|
||||
regval &= ~HW_CONTROL_MASK;
|
||||
regmap_write(sc->regmap, REG_OFFSET, regval);
|
||||
/*
|
||||
* There may be a race with internal HW trigger signal,
|
||||
* that will result in GDSC going through a power down and
|
||||
* up cycle. If we poll too early, status bit will
|
||||
* indicate 'on' before the GDSC can finish the power cycle.
|
||||
* Account for this case by waiting 1us before polling.
|
||||
*/
|
||||
gdsc_mb(sc);
|
||||
udelay(1);
|
||||
|
||||
ret = poll_gdsc_status(sc, ENABLED);
|
||||
if (ret)
|
||||
dev_err(&rdev->dev, "%s set_mode timed out: 0x%x\n",
|
||||
sc->rdesc.name, regval);
|
||||
break;
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
if (sc->parent_regulator)
|
||||
regulator_set_voltage(sc->parent_regulator, 0, INT_MAX);
|
||||
|
||||
mutex_unlock(&gdsc_seq_lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct regulator_ops gdsc_ops = {
|
||||
.is_enabled = gdsc_is_enabled,
|
||||
.enable = gdsc_enable,
|
||||
.disable = gdsc_disable,
|
||||
.set_mode = gdsc_set_mode,
|
||||
.get_mode = gdsc_get_mode,
|
||||
};
|
||||
|
||||
static const struct regmap_config gdsc_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static int gdsc_probe(struct platform_device *pdev)
|
||||
{
|
||||
static atomic_t gdsc_count = ATOMIC_INIT(-1);
|
||||
struct regulator_config reg_config = {};
|
||||
struct regulator_init_data *init_data;
|
||||
struct resource *res;
|
||||
struct gdsc *sc;
|
||||
uint32_t regval, clk_dis_wait_val = 0;
|
||||
bool support_hw_trigger;
|
||||
int i, ret;
|
||||
u32 timeout;
|
||||
|
||||
sc = devm_kzalloc(&pdev->dev, sizeof(struct gdsc), GFP_KERNEL);
|
||||
if (sc == NULL)
|
||||
return -ENOMEM;
|
||||
|
||||
init_data = of_get_regulator_init_data(&pdev->dev, pdev->dev.of_node,
|
||||
&sc->rdesc);
|
||||
if (init_data == NULL)
|
||||
return -ENOMEM;
|
||||
|
||||
if (of_get_property(pdev->dev.of_node, "parent-supply", NULL))
|
||||
init_data->supply_regulator = "parent";
|
||||
|
||||
ret = of_property_read_string(pdev->dev.of_node, "regulator-name",
|
||||
&sc->rdesc.name);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (res == NULL) {
|
||||
dev_err(&pdev->dev, "Failed to get resources\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
sc->gdscr = devm_ioremap(&pdev->dev, res->start, resource_size(res));
|
||||
if (sc->gdscr == NULL)
|
||||
return -ENOMEM;
|
||||
|
||||
sc->regmap = devm_regmap_init_mmio(&pdev->dev, sc->gdscr,
|
||||
&gdsc_regmap_config);
|
||||
if (!sc->regmap) {
|
||||
dev_err(&pdev->dev, "Couldn't get regmap\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (of_find_property(pdev->dev.of_node, "domain-addr", NULL)) {
|
||||
sc->domain_addr = syscon_regmap_lookup_by_phandle
|
||||
(pdev->dev.of_node, "domain-addr");
|
||||
if (IS_ERR(sc->domain_addr))
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
if (of_find_property(pdev->dev.of_node, "sw-reset", NULL)) {
|
||||
sc->sw_reset = syscon_regmap_lookup_by_phandle
|
||||
(pdev->dev.of_node, "sw-reset");
|
||||
if (IS_ERR(sc->sw_reset))
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
if (of_find_property(pdev->dev.of_node, "hw-ctrl-addr", NULL)) {
|
||||
sc->hw_ctrl = syscon_regmap_lookup_by_phandle(
|
||||
pdev->dev.of_node, "hw-ctrl-addr");
|
||||
if (IS_ERR(sc->hw_ctrl))
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
sc->gds_timeout = TIMEOUT_US;
|
||||
|
||||
ret = of_property_read_u32(pdev->dev.of_node, "qcom,gds-timeout",
|
||||
&timeout);
|
||||
if (!ret)
|
||||
sc->gds_timeout = timeout;
|
||||
|
||||
sc->clock_count = of_property_count_strings(pdev->dev.of_node,
|
||||
"clock-names");
|
||||
if (sc->clock_count == -EINVAL) {
|
||||
sc->clock_count = 0;
|
||||
} else if (sc->clock_count < 0) {
|
||||
dev_err(&pdev->dev, "Failed to get clock names\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
sc->clocks = devm_kzalloc(&pdev->dev,
|
||||
sizeof(struct clk *) * sc->clock_count, GFP_KERNEL);
|
||||
if (!sc->clocks)
|
||||
return -ENOMEM;
|
||||
|
||||
sc->root_clk_idx = -1;
|
||||
|
||||
sc->root_en = of_property_read_bool(pdev->dev.of_node,
|
||||
"qcom,enable-root-clk");
|
||||
|
||||
sc->force_root_en = of_property_read_bool(pdev->dev.of_node,
|
||||
"qcom,force-enable-root-clk");
|
||||
|
||||
if (of_find_property(pdev->dev.of_node, "vdd_parent-supply", NULL)) {
|
||||
sc->parent_regulator = devm_regulator_get(&pdev->dev,
|
||||
"vdd_parent");
|
||||
if (IS_ERR(sc->parent_regulator)) {
|
||||
ret = PTR_ERR(sc->parent_regulator);
|
||||
if (ret != -EPROBE_DEFER)
|
||||
dev_err(&pdev->dev,
|
||||
"Unable to get vdd_parent regulator, err: %d\n",
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
for (i = 0; i < sc->clock_count; i++) {
|
||||
const char *clock_name;
|
||||
|
||||
of_property_read_string_index(pdev->dev.of_node, "clock-names",
|
||||
i, &clock_name);
|
||||
|
||||
sc->clocks[i] = devm_clk_get(&pdev->dev, clock_name);
|
||||
if (IS_ERR(sc->clocks[i])) {
|
||||
int rc = PTR_ERR(sc->clocks[i]);
|
||||
|
||||
if (rc != -EPROBE_DEFER)
|
||||
dev_err(&pdev->dev, "Failed to get %s\n",
|
||||
clock_name);
|
||||
return rc;
|
||||
}
|
||||
|
||||
if (!strcmp(clock_name, "core_root_clk"))
|
||||
sc->root_clk_idx = i;
|
||||
}
|
||||
|
||||
if ((sc->root_en || sc->force_root_en) && (sc->root_clk_idx == -1)) {
|
||||
dev_err(&pdev->dev, "Failed to get root clock name\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
sc->reset_aon = of_property_read_bool(pdev->dev.of_node,
|
||||
"qcom,reset-aon-logic");
|
||||
|
||||
sc->rdesc.id = atomic_inc_return(&gdsc_count);
|
||||
sc->rdesc.ops = &gdsc_ops;
|
||||
sc->rdesc.type = REGULATOR_VOLTAGE;
|
||||
sc->rdesc.owner = THIS_MODULE;
|
||||
platform_set_drvdata(pdev, sc);
|
||||
|
||||
/*
|
||||
* Disable HW trigger: collapse/restore occur based on registers writes.
|
||||
* Disable SW override: Use hardware state-machine for sequencing.
|
||||
*/
|
||||
regmap_read(sc->regmap, REG_OFFSET, ®val);
|
||||
regval &= ~(HW_CONTROL_MASK | SW_OVERRIDE_MASK);
|
||||
|
||||
if (!of_property_read_u32(pdev->dev.of_node, "qcom,clk-dis-wait-val",
|
||||
&clk_dis_wait_val)) {
|
||||
clk_dis_wait_val = clk_dis_wait_val << CLK_DIS_WAIT_SHIFT;
|
||||
|
||||
/* Configure wait time between states. */
|
||||
regval &= ~(CLK_DIS_WAIT_MASK);
|
||||
regval |= clk_dis_wait_val;
|
||||
}
|
||||
|
||||
regmap_write(sc->regmap, REG_OFFSET, regval);
|
||||
|
||||
sc->no_status_check_on_disable =
|
||||
of_property_read_bool(pdev->dev.of_node,
|
||||
"qcom,no-status-check-on-disable");
|
||||
sc->toggle_logic = !of_property_read_bool(pdev->dev.of_node,
|
||||
"qcom,skip-logic-collapse");
|
||||
support_hw_trigger = of_property_read_bool(pdev->dev.of_node,
|
||||
"qcom,support-hw-trigger");
|
||||
if (support_hw_trigger) {
|
||||
init_data->constraints.valid_ops_mask |= REGULATOR_CHANGE_MODE;
|
||||
init_data->constraints.valid_modes_mask |=
|
||||
REGULATOR_MODE_NORMAL | REGULATOR_MODE_FAST;
|
||||
}
|
||||
|
||||
if (!sc->toggle_logic) {
|
||||
sc->reset_count = of_property_count_strings(pdev->dev.of_node,
|
||||
"reset-names");
|
||||
if (sc->reset_count == -EINVAL) {
|
||||
sc->reset_count = 0;
|
||||
} else if (sc->reset_count < 0) {
|
||||
dev_err(&pdev->dev, "Failed to get reset clock names\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
sc->reset_clocks = devm_kzalloc(&pdev->dev,
|
||||
sizeof(struct reset_control *) * sc->reset_count,
|
||||
GFP_KERNEL);
|
||||
if (!sc->reset_clocks)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < sc->reset_count; i++) {
|
||||
const char *reset_name;
|
||||
|
||||
of_property_read_string_index(pdev->dev.of_node,
|
||||
"reset-names", i, &reset_name);
|
||||
sc->reset_clocks[i] = devm_reset_control_get(&pdev->dev,
|
||||
reset_name);
|
||||
if (IS_ERR(sc->reset_clocks[i])) {
|
||||
int rc = PTR_ERR(sc->reset_clocks[i]);
|
||||
|
||||
if (rc != -EPROBE_DEFER)
|
||||
dev_err(&pdev->dev, "Failed to get %s\n",
|
||||
reset_name);
|
||||
return rc;
|
||||
}
|
||||
}
|
||||
|
||||
regval &= ~SW_COLLAPSE_MASK;
|
||||
regmap_write(sc->regmap, REG_OFFSET, regval);
|
||||
|
||||
ret = poll_gdsc_status(sc, ENABLED);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "%s enable timed out: 0x%x\n",
|
||||
sc->rdesc.name, regval);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
reg_config.dev = &pdev->dev;
|
||||
reg_config.init_data = init_data;
|
||||
reg_config.driver_data = sc;
|
||||
reg_config.of_node = pdev->dev.of_node;
|
||||
reg_config.regmap = sc->regmap;
|
||||
|
||||
sc->rdev = regulator_register(&sc->rdesc, ®_config);
|
||||
if (IS_ERR(sc->rdev)) {
|
||||
dev_err(&pdev->dev, "regulator_register(\"%s\") failed.\n",
|
||||
sc->rdesc.name);
|
||||
return PTR_ERR(sc->rdev);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int gdsc_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct gdsc *sc = platform_get_drvdata(pdev);
|
||||
|
||||
regulator_unregister(sc->rdev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id gdsc_match_table[] = {
|
||||
{ .compatible = "qcom,gdsc" },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct platform_driver gdsc_driver = {
|
||||
.probe = gdsc_probe,
|
||||
.remove = gdsc_remove,
|
||||
.driver = {
|
||||
.name = "gdsc",
|
||||
.of_match_table = gdsc_match_table,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init gdsc_init(void)
|
||||
{
|
||||
return platform_driver_register(&gdsc_driver);
|
||||
}
|
||||
subsys_initcall(gdsc_init);
|
||||
|
||||
static void __exit gdsc_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&gdsc_driver);
|
||||
}
|
||||
module_exit(gdsc_exit);
|
||||
Loading…
Reference in a new issue