A-Team_Digital_Solutions/android_kernel_motorola_sm6375
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ARM: dts: msm: add PCIe AUX clk freq for sa6155, sa8155, sa8195

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Replace deprecated PCIe DT entry for PCIe AUX clock controller
setting with the correct entry and value. PCIe core controller
requires AUX clock to be 19.2MHz.

Change-Id: Ia670d8e75f75939c2798d795e21771402d83569c
This commit is contained in:
Rama Krishna Phani A 2021-02-15 21:23:41 +05:30 • committed by Gerrit - the friendly Code Review server
commit 16506136aa
3 changed files with 7 additions and 7 deletions
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2
qcom/sa6155-pcie.dtsi
View file

@ -152,7 +152,7 @@
linux,pci-domain = <0>;
qcom,pcie-phy-ver = <2609>;
qcom,use-19p2mhz-aux-clk;
qcom,aux-clk-freq = <20>; /* 19.2 MHz */
qcom,smmu-sid-base = <0x0400>;

8
qcom/sa8195p-pcie.dtsi
View file

@ -168,7 +168,7 @@
linux,pci-domain = <0>;
qcom,pcie-phy-ver = <2110>;
qcom,use-19p2mhz-aux-clk;
qcom,aux-clk-freq = <20>; /* 19.2 MHz */
qcom,smmu-sid-base = <0x1d80>;
@ -476,7 +476,7 @@
linux,pci-domain = <1>;
qcom,pcie-phy-ver = <2113>;
qcom,use-19p2mhz-aux-clk;
qcom,aux-clk-freq = <20>; /* 19.2 MHz */
qcom,smmu-sid-base = <0x1c80>;
@ -784,7 +784,7 @@
linux,pci-domain = <2>;
qcom,pcie-phy-ver = <2105>;
qcom,use-19p2mhz-aux-clk;
qcom,aux-clk-freq = <20>; /* 19.2 MHz */
qcom,smmu-sid-base = <0x1d00>;
@ -1222,7 +1222,7 @@
linux,pci-domain = <3>;
qcom,pcie-phy-ver = <2105>;
qcom,use-19p2mhz-aux-clk;
qcom,aux-clk-freq = <20>; /* 19.2 MHz */
qcom,smmu-sid-base = <0x1e00>;

4
qcom/sm8150-pcie.dtsi
View file

@ -174,7 +174,7 @@
linux,pci-domain = <0>;
qcom,pcie-phy-ver = <0x40>;
qcom,use-19p2mhz-aux-clk;
qcom,aux-clk-freq = <20>; /* 19.2 MHz */
qcom,smmu-sid-base = <0x1d80>;
@ -494,7 +494,7 @@
linux,pci-domain = <1>;
qcom,pcie-phy-ver = <0x40>;
qcom,use-19p2mhz-aux-clk;
qcom,aux-clk-freq = <20>; /* 19.2 MHz */
qcom,smmu-sid-base = <0x1e00>;